Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	372629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1879751

1

T5

39

T6

20

T1

193

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	570313	1			T5	56		T6	26		T1	55
values[0x0]	775812	1			T5	25		T6	14		T1	200
values[0x1]	906255	1			T5	17		T6	11		T1	190

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	215391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2036989

1

T5

48

T6

24

T1

256

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8538	1			T2	2		T3	293		T10	501
valid_sources[0x01]	8040	1			T23	1		T112	1		T2	1
valid_sources[0x02]	8367	1			T5	2		T1	6		T20	1
valid_sources[0x03]	8717	1			T5	1		T1	4		T20	1
valid_sources[0x04]	8763	1			T1	1		T17	2		T21	17
valid_sources[0x05]	8368	1			T5	1		T1	1		T2	2
valid_sources[0x06]	10137	1			T72	2		T2	2		T3	706
valid_sources[0x07]	9651	1			T2	5		T3	1153		T10	506
valid_sources[0x08]	9876	1			T2	1		T3	358		T10	486
valid_sources[0x09]	8072	1			T4	4		T112	1		T2	2
valid_sources[0x0a]	9476	1			T3	500		T10	497		T32	1
valid_sources[0x0b]	8754	1			T1	2		T2	2		T27	1
valid_sources[0x0c]	8948	1			T17	1		T20	1		T3	350
valid_sources[0x0d]	8105	1			T1	5		T19	1		T111	3
valid_sources[0x0e]	8273	1			T1	4		T3	355		T10	516
valid_sources[0x0f]	8825	1			T2	4		T27	1		T3	220
valid_sources[0x10]	8795	1			T17	2		T3	256		T10	467
valid_sources[0x11]	8559	1			T6	9		T20	1		T2	4
valid_sources[0x12]	8088	1			T5	1		T3	265		T10	507
valid_sources[0x13]	8389	1			T111	1		T2	2		T3	306
valid_sources[0x14]	9147	1			T2	2		T3	391		T10	477
valid_sources[0x15]	8050	1			T3	439		T10	471		T31	1
valid_sources[0x16]	9258	1			T1	6		T2	3		T3	293
valid_sources[0x17]	10500	1			T20	1		T23	1		T94	6
valid_sources[0x18]	8648	1			T5	1		T17	1		T20	1
valid_sources[0x19]	8891	1			T1	2		T19	1		T35	1
valid_sources[0x1a]	8497	1			T2	3		T3	187		T10	454
valid_sources[0x1b]	9150	1			T5	3		T4	2		T19	1
valid_sources[0x1c]	9234	1			T5	1		T21	20		T23	1
valid_sources[0x1d]	9720	1			T17	1		T2	1		T27	3
valid_sources[0x1e]	9171	1			T5	3		T35	2		T3	258
valid_sources[0x1f]	7760	1			T6	3		T2	5		T3	188
valid_sources[0x20]	7564	1			T5	1		T17	1		T2	3
valid_sources[0x21]	8271	1			T17	2		T2	1		T3	361
valid_sources[0x22]	9187	1			T17	1		T94	4		T2	1
valid_sources[0x23]	9120	1			T1	2		T20	1		T2	1
valid_sources[0x24]	7889	1			T5	1		T20	1		T112	1
valid_sources[0x25]	8086	1			T17	1		T4	6		T2	5
valid_sources[0x26]	9358	1			T17	1		T2	1		T3	618
valid_sources[0x27]	9066	1			T19	1		T35	1		T2	2
valid_sources[0x28]	8397	1			T2	1		T3	316		T10	489
valid_sources[0x29]	8564	1			T1	11		T23	1		T72	2
valid_sources[0x2a]	9935	1			T17	1		T20	1		T111	4
valid_sources[0x2b]	9217	1			T5	2		T2	1		T3	346
valid_sources[0x2c]	9131	1			T5	2		T17	1		T3	405
valid_sources[0x2d]	8141	1			T5	1		T19	1		T2	4
valid_sources[0x2e]	8025	1			T1	1		T17	1		T2	2
valid_sources[0x2f]	9474	1			T5	1		T2	3		T3	403
valid_sources[0x30]	9624	1			T1	7		T2	1		T3	359
valid_sources[0x31]	8757	1			T17	1		T23	1		T112	1
valid_sources[0x32]	8408	1			T20	1		T21	30		T2	1
valid_sources[0x33]	9011	1			T1	2		T35	1		T2	2
valid_sources[0x34]	9247	1			T1	14		T2	1		T27	1
valid_sources[0x35]	9344	1			T19	1		T72	1		T3	447
valid_sources[0x36]	8612	1			T5	1		T1	3		T2	2
valid_sources[0x37]	8662	1			T2	1		T3	316		T10	588
valid_sources[0x38]	8246	1			T17	1		T27	1		T3	444
valid_sources[0x39]	9185	1			T17	2		T2	2		T3	349
valid_sources[0x3a]	9355	1			T5	1		T1	1		T2	2
valid_sources[0x3b]	8690	1			T1	2		T35	1		T2	3
valid_sources[0x3c]	8781	1			T5	2		T19	1		T94	2
valid_sources[0x3d]	9201	1			T2	1		T3	161		T10	454
valid_sources[0x3e]	10201	1			T1	2		T2	2		T3	614
valid_sources[0x3f]	8591	1			T35	1		T2	2		T3	640
valid_sources[0x40]	8967	1			T5	1		T1	3		T2	1
valid_sources[0x41]	9433	1			T1	4		T17	1		T2	3
valid_sources[0x42]	8362	1			T111	5		T2	2		T27	1
valid_sources[0x43]	9487	1			T5	5		T111	2		T2	1
valid_sources[0x44]	9549	1			T19	1		T3	642		T10	537
valid_sources[0x45]	9069	1			T5	1		T17	1		T2	1
valid_sources[0x46]	7708	1			T1	1		T17	2		T20	1
valid_sources[0x47]	8847	1			T5	1		T111	1		T3	584
valid_sources[0x48]	9677	1			T17	1		T20	1		T3	652
valid_sources[0x49]	8285	1			T20	1		T2	4		T3	233
valid_sources[0x4a]	9008	1			T17	3		T35	1		T2	1
valid_sources[0x4b]	8626	1			T20	1		T3	439		T10	473
valid_sources[0x4c]	8761	1			T17	1		T3	509		T10	481
valid_sources[0x4d]	8136	1			T1	5		T23	1		T72	1
valid_sources[0x4e]	8935	1			T2	1		T3	405		T10	521
valid_sources[0x4f]	9261	1			T21	6		T2	2		T3	374
valid_sources[0x50]	8622	1			T1	4		T2	5		T3	367
valid_sources[0x51]	9437	1			T5	1		T1	3		T2	2
valid_sources[0x52]	8797	1			T5	2		T1	3		T19	1
valid_sources[0x53]	8641	1			T19	1		T3	641		T10	452
valid_sources[0x54]	9174	1			T35	1		T2	2		T3	349
valid_sources[0x55]	8053	1			T35	1		T2	1		T27	3
valid_sources[0x56]	8229	1			T2	1		T3	367		T10	488
valid_sources[0x57]	9434	1			T1	12		T20	2		T2	4
valid_sources[0x58]	7818	1			T23	1		T2	2		T3	43
valid_sources[0x59]	9283	1			T27	2		T3	352		T10	514
valid_sources[0x5a]	9737	1			T20	1		T2	5		T3	813
valid_sources[0x5b]	8504	1			T1	1		T20	1		T2	4
valid_sources[0x5c]	8496	1			T5	2		T2	2		T3	226
valid_sources[0x5d]	9296	1			T1	14		T35	1		T2	1
valid_sources[0x5e]	9251	1			T4	6		T3	364		T10	473
valid_sources[0x5f]	8700	1			T21	6		T2	2		T3	352
valid_sources[0x60]	8198	1			T1	3		T17	1		T2	1
valid_sources[0x61]	8193	1			T1	5		T22	81		T2	1
valid_sources[0x62]	8926	1			T20	1		T27	2		T3	386
valid_sources[0x63]	8432	1			T1	36		T112	1		T2	4
valid_sources[0x64]	9358	1			T5	2		T1	10		T2	2
valid_sources[0x65]	7916	1			T17	2		T2	2		T27	2
valid_sources[0x66]	8988	1			T2	3		T3	64		T10	503
valid_sources[0x67]	8233	1			T17	1		T20	1		T2	3
valid_sources[0x68]	8296	1			T20	1		T2	2		T3	303
valid_sources[0x69]	9683	1			T5	1		T72	1		T2	2
valid_sources[0x6a]	8926	1			T2	2		T3	499		T28	4
valid_sources[0x6b]	8158	1			T3	361		T10	498		T139	2
valid_sources[0x6c]	8451	1			T2	4		T3	240		T10	503
valid_sources[0x6d]	7888	1			T5	2		T2	2		T27	1
valid_sources[0x6e]	8659	1			T5	1		T112	1		T2	1
valid_sources[0x6f]	8573	1			T23	1		T111	1		T35	1
valid_sources[0x70]	8990	1			T1	6		T17	1		T3	160
valid_sources[0x71]	8946	1			T5	1		T2	2		T3	678
valid_sources[0x72]	9377	1			T20	1		T2	1		T3	610
valid_sources[0x73]	8862	1			T19	1		T35	1		T2	2
valid_sources[0x74]	9067	1			T111	1		T2	1		T27	1
valid_sources[0x75]	7890	1			T17	1		T19	1		T2	1
valid_sources[0x76]	8643	1			T2	1		T3	808		T10	518
valid_sources[0x77]	8621	1			T111	2		T2	1		T3	313
valid_sources[0x78]	9564	1			T1	7		T17	2		T27	1
valid_sources[0x79]	9756	1			T5	1		T1	6		T112	1
valid_sources[0x7a]	9255	1			T1	7		T94	2		T3	764
valid_sources[0x7b]	8962	1			T112	1		T2	4		T3	490
valid_sources[0x7c]	9501	1			T6	14		T17	1		T19	1
valid_sources[0x7d]	8643	1			T17	1		T19	1		T3	148
valid_sources[0x7e]	9547	1			T1	13		T2	1		T3	500
valid_sources[0x7f]	8294	1			T5	3		T19	1		T3	561
valid_sources[0x80]	9769	1			T27	2		T3	638		T10	453

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

481441

1

T5

27

T6

13

T1

27

values[0x0]

all_enables

biggest_size

715460

1

T5

9

T6

6

T1

115

values[0x1]

all_enables

biggest_size

682850

1

T5

3

T6

1

T1

51