Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T22
1	0	Covered	T18,T24,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	547769384	9009	0	0
GateOpen_A	547769384	15457	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547769384	9009	0	0
T1	448132	14	0	0
T3	0	283	0	0
T4	42668	0	0	0
T10	0	172	0	0
T17	14936	4	0	0
T18	5237	20	0	0
T19	20337	0	0	0
T20	18303	0	0	0
T21	19479	0	0	0
T22	44792	4	0	0
T23	4688	0	0	0
T24	2393	3	0	0
T27	0	4	0	0
T31	0	4	0	0
T34	0	5	0	0
T39	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	547769384	15457	0	0
T1	448132	18	0	0
T4	42668	4	0	0
T5	9632	4	0	0
T6	7053	0	0	0
T17	14936	4	0	0
T18	5237	24	0	0
T19	20337	0	0	0
T20	18303	4	0	0
T21	19479	4	0	0
T22	44792	4	0	0
T24	0	7	0	0
T72	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T22
1	0	Covered	T18,T24,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	60262004	2123	0	0
GateOpen_A	60262004	3735	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60262004	2123	0	0
T1	49768	3	0	0
T3	0	71	0	0
T4	4730	0	0	0
T10	0	37	0	0
T17	1651	1	0	0
T18	555	5	0	0
T19	2437	0	0	0
T20	2153	0	0	0
T21	2147	0	0	0
T22	4955	1	0	0
T23	503	0	0	0
T24	255	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T39	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60262004	3735	0	0
T1	49768	4	0	0
T4	4730	1	0	0
T5	1048	1	0	0
T6	819	0	0	0
T17	1651	1	0	0
T18	555	6	0	0
T19	2437	0	0	0
T20	2153	1	0	0
T21	2147	1	0	0
T22	4955	1	0	0
T24	0	2	0	0
T72	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T22
1	0	Covered	T18,T24,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	120524439	2295	0	0
GateOpen_A	120524439	3907	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120524439	2295	0	0
T1	99535	4	0	0
T3	0	70	0	0
T4	9460	0	0	0
T10	0	46	0	0
T17	3302	1	0	0
T18	1109	5	0	0
T19	4875	0	0	0
T20	4308	0	0	0
T21	4293	0	0	0
T22	9909	1	0	0
T23	1006	0	0	0
T24	509	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T39	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120524439	3907	0	0
T1	99535	5	0	0
T4	9460	1	0	0
T5	2096	1	0	0
T6	1638	0	0	0
T17	3302	1	0	0
T18	1109	6	0	0
T19	4875	0	0	0
T20	4308	1	0	0
T21	4293	1	0	0
T22	9909	1	0	0
T24	0	2	0	0
T72	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T22
1	0	Covered	T18,T24,T39
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	242715359	2307	0	0
GateOpen_A	242715359	3919	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242715359	2307	0	0
T1	199216	3	0	0
T3	0	67	0	0
T4	18985	0	0	0
T10	0	45	0	0
T17	6655	1	0	0
T18	2312	5	0	0
T19	8683	0	0	0
T20	7894	0	0	0
T21	8692	0	0	0
T22	19952	1	0	0
T23	2119	0	0	0
T24	1083	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T39	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242715359	3919	0	0
T1	199216	4	0	0
T4	18985	1	0	0
T5	4325	1	0	0
T6	3064	0	0	0
T17	6655	1	0	0
T18	2312	6	0	0
T19	8683	0	0	0
T20	7894	1	0	0
T21	8692	1	0	0
T22	19952	1	0	0
T24	0	2	0	0
T72	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T18
0	1	Covered	T1,T3,T10
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T22
1	0	Covered	T18,T39,T34
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	124267582	2284	0	0
GateOpen_A	124267582	3896	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124267582	2284	0	0
T1	99613	4	0	0
T3	0	75	0	0
T4	9493	0	0	0
T10	0	44	0	0
T17	3328	1	0	0
T18	1261	5	0	0
T19	4342	0	0	0
T20	3948	0	0	0
T21	4347	0	0	0
T22	9976	1	0	0
T23	1060	0	0	0
T24	546	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T34	0	5	0	0
T39	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124267582	3896	0	0
T1	99613	5	0	0
T4	9493	1	0	0
T5	2163	1	0	0
T6	1532	0	0	0
T17	3328	1	0	0
T18	1261	6	0	0
T19	4342	0	0	0
T20	3948	1	0	0
T21	4347	1	0	0
T22	9976	1	0	0
T24	0	1	0	0
T72	0	1	0	0