Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	466726075	39780	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466726075	39780	0	0
T1	249020	134	0	0
T2	0	418	0	0
T3	0	580	0	0
T4	95920	0	0	0
T10	0	926	0	0
T11	0	487	0	0
T12	0	332	0	0
T13	0	91	0	0
T14	0	144	0	0
T15	0	534	0	0
T16	0	381	0	0
T17	8315	0	0	0
T18	6955	0	0	0
T19	7685	0	0	0
T20	9865	0	0	0
T21	10860	0	0	0
T22	6230	0	0	0
T23	10590	0	0	0
T24	5575	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	93345215	5815	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	5815	0	0
T1	49804	21	0	0
T2	0	55	0	0
T3	0	92	0	0
T4	19184	0	0	0
T10	0	121	0	0
T11	0	71	0	0
T12	0	43	0	0
T13	0	14	0	0
T14	0	23	0	0
T15	0	69	0	0
T16	0	57	0	0
T17	1663	0	0	0
T18	1391	0	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	93345215	5744	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	5744	0	0
T1	49804	21	0	0
T2	0	51	0	0
T3	0	91	0	0
T4	19184	0	0	0
T10	0	117	0	0
T11	0	70	0	0
T12	0	48	0	0
T13	0	14	0	0
T14	0	23	0	0
T15	0	77	0	0
T16	0	47	0	0
T17	1663	0	0	0
T18	1391	0	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	93345215	8099	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	8099	0	0
T1	49804	27	0	0
T2	0	85	0	0
T3	0	119	0	0
T4	19184	0	0	0
T10	0	190	0	0
T11	0	98	0	0
T12	0	65	0	0
T13	0	18	0	0
T14	0	29	0	0
T15	0	108	0	0
T16	0	73	0	0
T17	1663	0	0	0
T18	1391	0	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	93345215	7953	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	7953	0	0
T1	49804	27	0	0
T2	0	84	0	0
T3	0	116	0	0
T4	19184	0	0	0
T10	0	191	0	0
T11	0	98	0	0
T12	0	64	0	0
T13	0	19	0	0
T14	0	29	0	0
T15	0	104	0	0
T16	0	81	0	0
T17	1663	0	0	0
T18	1391	0	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	93345215	12169	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	12169	0	0
T1	49804	38	0	0
T2	0	143	0	0
T3	0	162	0	0
T4	19184	0	0	0
T10	0	307	0	0
T11	0	150	0	0
T12	0	112	0	0
T13	0	26	0	0
T14	0	40	0	0
T15	0	176	0	0
T16	0	123	0	0
T17	1663	0	0	0
T18	1391	0	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	0	0	0