Unified Coverage Report :: Module :: clkmgr_reg_top

Module : clkmgr_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	100.00	98.30			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.64	98.39	95.42	100.00		97.91	96.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault	100.00	100.00
u_alert_test_recov_fault	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_clk_enables_clk_io_div2_peri_en	100.00	100.00	100.00			100.00
u_clk_enables_clk_io_div4_peri_en	100.00	100.00	100.00			100.00
u_clk_enables_clk_io_peri_en	100.00	100.00	100.00			100.00
u_clk_enables_clk_usb_peri_en	100.00	100.00	100.00			100.00
u_clk_hints_clk_main_aes_hint	100.00	100.00	100.00			100.00
u_clk_hints_clk_main_hmac_hint	100.00	100.00	100.00			100.00
u_clk_hints_clk_main_kmac_hint	100.00	100.00	100.00			100.00
u_clk_hints_clk_main_otbn_hint	100.00	100.00	100.00			100.00
u_clk_hints_status_clk_main_aes_val	92.59	77.78	100.00			100.00
u_clk_hints_status_clk_main_hmac_val	92.59	77.78	100.00			100.00
u_clk_hints_status_clk_main_kmac_val	92.59	77.78	100.00			100.00
u_clk_hints_status_clk_main_otbn_val	92.59	77.78	100.00			100.00
u_extclk_ctrl_hi_speed_sel	100.00	100.00	100.00			100.00
u_extclk_ctrl_regwen	100.00	100.00	100.00			100.00
u_extclk_ctrl_sel	100.00	100.00	100.00			100.00
u_extclk_status	100.00	100.00
u_fatal_err_code_idle_cnt	96.30	88.89	100.00			100.00
u_fatal_err_code_reg_intg	96.30	88.89	100.00			100.00
u_fatal_err_code_shadow_storage_err	96.30	88.89	100.00			100.00
u_io_div2_meas_ctrl_en	100.00	100.00	100.00			100.00
u_io_div2_meas_ctrl_en_cdc	89.66	96.24	80.88			91.53	90.00
u_io_div2_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_io_div2_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_io_div2_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_div2_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_io_div2_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_div4_meas_ctrl_en	100.00	100.00	100.00			100.00
u_io_div4_meas_ctrl_en_cdc	92.36	97.74	86.76			94.92	90.00
u_io_div4_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_io_div4_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_io_div4_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_div4_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_io_div4_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_meas_ctrl_en	100.00	100.00	100.00			100.00
u_io_meas_ctrl_en_cdc	89.66	96.24	80.88			91.53	90.00
u_io_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_io_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_io_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_io_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_io_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_io_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_io_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_jitter_enable	100.00	100.00	100.00			100.00
u_jitter_regwen	100.00	100.00	100.00			100.00
u_main_meas_ctrl_en	100.00	100.00	100.00			100.00
u_main_meas_ctrl_en_cdc	89.66	96.24	80.88			91.53	90.00
u_main_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_main_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_main_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_main_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_main_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_main_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_main_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_measure_ctrl_regwen	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_recov_err_code_io_div2_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_div2_timeout_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_div4_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_div4_timeout_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_io_timeout_err	100.00	100.00	100.00			100.00
u_recov_err_code_main_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_main_timeout_err	100.00	100.00	100.00			100.00
u_recov_err_code_shadow_update_err	97.22	100.00	91.67			100.00
u_recov_err_code_usb_measure_err	100.00	100.00	100.00			100.00
u_recov_err_code_usb_timeout_err	100.00	100.00	100.00			100.00
u_reg_if	98.98	97.14	98.80			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_usb_meas_ctrl_en	100.00	100.00	100.00			100.00
u_usb_meas_ctrl_en_cdc	89.66	96.24	80.88			91.53	90.00
u_usb_meas_ctrl_shadowed_cdc	98.39	100.00	93.55			100.00	100.00
u_usb_meas_ctrl_shadowed_hi	99.55	100.00	98.21			100.00	100.00
u_usb_meas_ctrl_shadowed_hi_err_storage_sync	100.00	100.00				100.00
u_usb_meas_ctrl_shadowed_hi_err_update_sync	100.00	100.00	100.00			100.00	100.00
u_usb_meas_ctrl_shadowed_lo	99.55	100.00	98.21			100.00	100.00
u_usb_meas_ctrl_shadowed_lo_err_storage_sync	100.00	100.00				100.00
u_usb_meas_ctrl_shadowed_lo_err_update_sync	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : clkmgr_reg_top

	Line No.	Total	Covered	Percent
TOTAL		244	244	100.00
ALWAYS	82	4	4	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
ALWAYS	277	4	4	100.00
CONT_ASSIGN	307	1	1	100.00
ALWAYS	320	3	3	100.00
CONT_ASSIGN	349	1	1	100.00
ALWAYS	363	4	4	100.00
CONT_ASSIGN	393	1	1	100.00
ALWAYS	406	3	3	100.00
CONT_ASSIGN	435	1	1	100.00
ALWAYS	449	4	4	100.00
CONT_ASSIGN	479	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	521	1	1	100.00
ALWAYS	535	4	4	100.00
CONT_ASSIGN	565	1	1	100.00
ALWAYS	578	3	3	100.00
CONT_ASSIGN	607	1	1	100.00
ALWAYS	621	4	4	100.00
CONT_ASSIGN	651	1	1	100.00
ALWAYS	664	3	3	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1410	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1445	1	1	100.00
CONT_ASSIGN	1568	1	1	100.00
CONT_ASSIGN	1571	1	1	100.00
CONT_ASSIGN	1603	1	1	100.00
CONT_ASSIGN	1726	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1761	1	1	100.00
CONT_ASSIGN	1884	1	1	100.00
CONT_ASSIGN	1887	1	1	100.00
CONT_ASSIGN	1918	1	1	100.00
ALWAYS	2424	23	23	100.00
CONT_ASSIGN	2449	1	1	100.00
ALWAYS	2453	1	1	100.00
CONT_ASSIGN	2479	1	1	100.00
CONT_ASSIGN	2481	1	1	100.00
CONT_ASSIGN	2483	1	1	100.00
CONT_ASSIGN	2484	1	1	100.00
CONT_ASSIGN	2486	1	1	100.00
CONT_ASSIGN	2487	1	1	100.00
CONT_ASSIGN	2489	1	1	100.00
CONT_ASSIGN	2491	1	1	100.00
CONT_ASSIGN	2492	1	1	100.00
CONT_ASSIGN	2493	1	1	100.00
CONT_ASSIGN	2495	1	1	100.00
CONT_ASSIGN	2496	1	1	100.00
CONT_ASSIGN	2498	1	1	100.00
CONT_ASSIGN	2499	1	1	100.00
CONT_ASSIGN	2501	1	1	100.00
CONT_ASSIGN	2503	1	1	100.00
CONT_ASSIGN	2505	1	1	100.00
CONT_ASSIGN	2507	1	1	100.00
CONT_ASSIGN	2508	1	1	100.00
CONT_ASSIGN	2510	1	1	100.00
CONT_ASSIGN	2512	1	1	100.00
CONT_ASSIGN	2514	1	1	100.00
CONT_ASSIGN	2516	1	1	100.00
CONT_ASSIGN	2517	1	1	100.00
CONT_ASSIGN	2519	1	1	100.00
CONT_ASSIGN	2520	1	1	100.00
CONT_ASSIGN	2522	1	1	100.00
CONT_ASSIGN	2523	1	1	100.00
CONT_ASSIGN	2526	1	1	100.00
CONT_ASSIGN	2528	1	1	100.00
CONT_ASSIGN	2529	1	1	100.00
CONT_ASSIGN	2532	1	1	100.00
CONT_ASSIGN	2534	1	1	100.00
CONT_ASSIGN	2535	1	1	100.00
CONT_ASSIGN	2538	1	1	100.00
CONT_ASSIGN	2540	1	1	100.00
CONT_ASSIGN	2541	1	1	100.00
CONT_ASSIGN	2544	1	1	100.00
CONT_ASSIGN	2546	1	1	100.00
CONT_ASSIGN	2547	1	1	100.00
CONT_ASSIGN	2550	1	1	100.00
CONT_ASSIGN	2552	1	1	100.00
CONT_ASSIGN	2554	1	1	100.00
CONT_ASSIGN	2556	1	1	100.00
CONT_ASSIGN	2558	1	1	100.00
CONT_ASSIGN	2560	1	1	100.00
CONT_ASSIGN	2562	1	1	100.00
CONT_ASSIGN	2564	1	1	100.00
CONT_ASSIGN	2566	1	1	100.00
CONT_ASSIGN	2568	1	1	100.00
CONT_ASSIGN	2570	1	1	100.00
CONT_ASSIGN	2572	1	1	100.00
ALWAYS	2576	23	23	100.00
ALWAYS	2603	47	47	100.00
ALWAYS	2717	3	3	100.00
ALWAYS	2725	3	3	100.00
CONT_ASSIGN	2733	1	1	100.00
CONT_ASSIGN	2736	1	1	100.00
CONT_ASSIGN	2748	1	1	100.00
CONT_ASSIGN	2763	1	1	100.00
ALWAYS	2765	12	12	100.00
CONT_ASSIGN	2810	1	1	100.00
CONT_ASSIGN	2811	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
91	1	1
103	1	1
104	1	1
132	1	1
133	1	1
277	1	1
278	1	1
279	1	1
280	1	1
307	1	1
320	1	1
321	1	1
322	1	1
349	1	1
363	1	1
364	1	1
365	1	1
366	1	1
393	1	1
406	1	1
407	1	1
408	1	1
435	1	1
449	1	1
450	1	1
451	1	1
452	1	1
479	1	1
492	1	1
493	1	1
494	1	1
521	1	1
535	1	1
536	1	1
537	1	1
538	1	1
565	1	1
578	1	1
579	1	1
580	1	1
607	1	1
621	1	1
622	1	1
623	1	1
624	1	1
651	1	1
664	1	1
665	1	1
666	1	1
693	1	1
700	1	1
715	1	1
731	1	1
765	1	1
1253	1	1
1256	1	1
1287	1	1
1410	1	1
1413	1	1
1445	1	1
1568	1	1
1571	1	1
1603	1	1
1726	1	1
1729	1	1
1761	1	1
1884	1	1
1887	1	1
1918	1	1
2424	1	1
2425	1	1
2426	1	1
2427	1	1
2428	1	1
2429	1	1
2430	1	1
2431	1	1
2432	1	1
2433	1	1
2434	1	1
2435	1	1
2436	1	1
2437	1	1
2438	1	1
2439	1	1
2440	1	1
2441	1	1
2442	1	1
2443	1	1
2444	1	1
2445	1	1
2446	1	1
2449	1	1
2453	1	1
2479	1	1
2481	1	1
2483	1	1
2484	1	1
2486	1	1
2487	1	1
2489	1	1
2491	1	1
2492	1	1
2493	1	1
2495	1	1
2496	1	1
2498	1	1
2499	1	1
2501	1	1
2503	1	1
2505	1	1
2507	1	1
2508	1	1
2510	1	1
2512	1	1
2514	1	1
2516	1	1
2517	1	1
2519	1	1
2520	1	1
2522	1	1
2523	1	1
2526	1	1
2528	1	1
2529	1	1
2532	1	1
2534	1	1
2535	1	1
2538	1	1
2540	1	1
2541	1	1
2544	1	1
2546	1	1
2547	1	1
2550	1	1
2552	1	1
2554	1	1
2556	1	1
2558	1	1
2560	1	1
2562	1	1
2564	1	1
2566	1	1
2568	1	1
2570	1	1
2572	1	1
2576	1	1
2577	1	1
2578	1	1
2579	1	1
2580	1	1
2581	1	1
2582	1	1
2583	1	1
2584	1	1
2585	1	1
2586	1	1
2587	1	1
2588	1	1
2589	1	1
2590	1	1
2591	1	1
2592	1	1
2593	1	1
2594	1	1
2595	1	1
2596	1	1
2597	1	1
2598	1	1
2603	1	1
2604	1	1
2606	1	1
2607	1	1
2611	1	1
2615	1	1
2616	1	1
2620	1	1
2624	1	1
2628	1	1
2632	1	1
2633	1	1
2634	1	1
2635	1	1
2639	1	1
2640	1	1
2641	1	1
2642	1	1
2646	1	1
2647	1	1
2648	1	1
2649	1	1
2653	1	1
2657	1	1
2660	1	1
2663	1	1
2666	1	1
2669	1	1
2672	1	1
2675	1	1
2678	1	1
2681	1	1
2684	1	1
2687	1	1
2688	1	1
2689	1	1
2690	1	1
2691	1	1
2692	1	1
2693	1	1
2694	1	1
2695	1	1
2696	1	1
2697	1	1
2701	1	1
2702	1	1
2703	1	1
2717	1	1
2718	1	1
2720	1	1
2725	1	1
2726	1	1
2728	1	1
2733	1	1
2736	1	1
2748	1	1
2763	1	1
2765	1	1
2766	1	1
2768	1	1
2771	1	1
2774	1	1
2777	1	1
2780	1	1
2783	1	1
2786	1	1
2789	1	1
2792	1	1
2795	1	1
2810	1	1
2811	1	1

---

Cond Coverage for Module : clkmgr_reg_top

	Total	Covered	Percent
Conditions	294	289	98.30
Logical	294	289	98.30
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T3,T10,T11
1	1	Covered	T5,T6,T1

 LINE       84
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T40,T41,T42
1	0	Covered	T95,T96,T97

 LINE       91
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T6,T1
0	0	1	Covered	T40,T41,T42
0	1	0	Covered	T95,T96,T97
1	0	0	Covered	T40,T41,T42

 LINE       133
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T6,T1
0	0	1	Covered	T95,T96,T97
0	1	0	Covered	T3,T10,T11
1	0	0	Covered	T3,T10,T11

 LINE       765
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T73,T74,T98
1	1	Covered	T6,T19,T20

 LINE       1256
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1287
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1413
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1445
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1571
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1603
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1729
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1761
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1887
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1918
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       2425
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T4,T21

 LINE       2426
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T4

 LINE       2427
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T4

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T4

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T4,T21

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T17,T4

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T17

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T17

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T17

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T4,T21

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T3,T10

 LINE       2449
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       2449
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1

 LINE       2453
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T3,T10,T11

 LINE       2453
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T5,T6,T1
22 (addr_hit[21] & ((|(4'...	Covered	T5,T3,T10
21 (addr_hit[20] & ((|(4'...	Covered	T5,T1,T4
20 (addr_hit[19] & ((|(4'...	Covered	T5,T4,T21
19 (addr_hit[18] & ((|(4'...	Covered	T5,T1,T2
18 (addr_hit[17] & ((|(4'...	Covered	T5,T21,T3
17 (addr_hit[16] & ((|(4'...	Covered	T1,T4,T21
16 (addr_hit[15] & ((|(4'...	Covered	T5,T21,T3
15 (addr_hit[14] & ((|(4'...	Covered	T5,T1,T4
14 (addr_hit[13] & ((|(4'...	Covered	T5,T21,T3
13 (addr_hit[12] & ((|(4'...	Covered	T5,T1,T4
12 (addr_hit[11] & ((|(4'...	Covered	T5,T4,T21
11 (addr_hit[10] & ((|(4'...	Covered	T1,T4,T21
10 (addr_hit[9] & ((|(4'b...	Covered	T5,T1,T2
9 (addr_hit[8] & ((|(4'b...	Covered	T5,T1,T4
8 (addr_hit[7] & ((|(4'b...	Covered	T5,T17,T4
7 (addr_hit[6] & ((|(4'b...	Covered	T5,T21,T22
6 (addr_hit[5] & ((|(4'b...	Covered	T17,T22,T27
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T4,T3
4 (addr_hit[3] & ((|(4'b...	Covered	T5,T6,T4
3 (addr_hit[2] & ((|(4'b...	Covered	T6,T19,T20
2 (addr_hit[1] & ((|(4'b...	Covered	T5,T4,T21
1 (addr_hit[0] & ((|(4'b...	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T4,T21
1	1	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T4
1	1	Covered	T6,T19,T20

 LINE       2453
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T21
1	1	Covered	T5,T6,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T4,T21
1	1	Covered	T5,T4,T3

 LINE       2453
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T17,T4
1	1	Covered	T17,T22,T27

 LINE       2453
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T17,T21
1	1	Covered	T5,T21,T22

 LINE       2453
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T17
1	1	Covered	T5,T17,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T17
1	1	Covered	T5,T1,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T1,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T21,T3

 LINE       2453
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T21,T3

 LINE       2453
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T21
1	1	Covered	T1,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T21,T3

 LINE       2453
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T21
1	1	Covered	T5,T1,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T3,T10
1	1	Covered	T5,T3,T10

 LINE       2479
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T4,T21
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T23,T35,T36

 LINE       2484
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T6,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T6,T19,T20

 LINE       2487
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T6,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T6,T19,T20

 LINE       2492
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T6,T4
1	1	0	Covered	T95,T99,T100
1	1	1	Covered	T6,T94,T3

 LINE       2493
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T4,T21
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T77,T78,T101

 LINE       2496
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T17,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T17,T22,T27

 LINE       2499
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T17
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T17,T22

 LINE       2508
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T1,T17
1	0	1	Covered	T5,T1,T17
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T5,T1,T17

 LINE       2517
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2520
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2522
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T95,T102,T100
1	1	1	Covered	T3,T10,T11

 LINE       2523
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2526
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2528
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T103,T104
1	1	1	Covered	T3,T10,T11

 LINE       2529
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2532
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2534
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T97,T105
1	1	1	Covered	T3,T10,T11

 LINE       2535
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2538
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T1,T4,T21
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2540
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T104,T106
1	1	1	Covered	T3,T10,T11

 LINE       2541
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2544
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2546
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T96,T107,T99
1	1	1	Covered	T3,T10,T11

 LINE       2547
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2550
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2733
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T54,T55,T56
1	0	Covered	T108,T109,T110
1	1	Covered	T5,T6,T1

 LINE       2763
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T5,T4,T21
1	0	Covered	T1,T4,T2

---

Branch Coverage for Module : clkmgr_reg_top

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	2449	2	2	100.00
IF	82	3	3	100.00
CASE	2604	23	23	100.00
IF	2717	2	2	100.00
IF	2725	2	2	100.00
CASE	2766	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2449	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	82	if ((!rst_ni))
-2-:	84	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T1
0	1	Covered	T40,T41,T42
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	2604	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T5,T6,T1
addr_hit[1]	Covered	T5,T6,T1
addr_hit[2]	Covered	T5,T6,T1
addr_hit[3]	Covered	T5,T6,T1
addr_hit[4]	Covered	T5,T6,T1
addr_hit[5]	Covered	T5,T6,T1
addr_hit[6]	Covered	T5,T6,T1
addr_hit[7]	Covered	T5,T6,T1
addr_hit[8]	Covered	T5,T6,T1
addr_hit[9]	Covered	T5,T6,T1
addr_hit[10]	Covered	T5,T6,T1
addr_hit[11]	Covered	T5,T6,T1
addr_hit[12]	Covered	T5,T6,T1
addr_hit[13]	Covered	T5,T6,T1
addr_hit[14]	Covered	T5,T6,T1
addr_hit[15]	Covered	T5,T6,T1
addr_hit[16]	Covered	T6,T1,T17
addr_hit[17]	Covered	T5,T6,T1
addr_hit[18]	Covered	T5,T6,T1
addr_hit[19]	Covered	T5,T6,T1
addr_hit[20]	Covered	T5,T6,T1
addr_hit[21]	Covered	T5,T6,T1
default	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	2717	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	2725	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	2766	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[10]	Covered	T5,T6,T1
addr_hit[11]	Covered	T5,T6,T1
addr_hit[12]	Covered	T5,T6,T1
addr_hit[13]	Covered	T5,T6,T1
addr_hit[14]	Covered	T5,T6,T1
addr_hit[15]	Covered	T5,T6,T1
addr_hit[16]	Covered	T6,T1,T17
addr_hit[17]	Covered	T5,T6,T1
addr_hit[18]	Covered	T5,T6,T1
addr_hit[19]	Covered	T5,T6,T1
default	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	94293783	521067	0	0
reAfterRv	94293783	521067	0	0
rePulse	94293783	139175	0	0
wePulse	94293783	381892	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	521067	0	0
T1	49804	445	0	0
T4	19184	52	0	0
T5	2252	98	0	0
T6	1754	51	0	0
T17	1663	81	0	0
T18	1391	0	0	0
T19	1537	28	0	0
T20	1973	40	0	0
T21	2172	119	0	0
T22	1246	81	0	0
T23	0	17	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	521067	0	0
T1	49804	445	0	0
T4	19184	52	0	0
T5	2252	98	0	0
T6	1754	51	0	0
T17	1663	81	0	0
T18	1391	0	0	0
T19	1537	28	0	0
T20	1973	40	0	0
T21	2172	119	0	0
T22	1246	81	0	0
T23	0	17	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	139175	0	0
T1	49804	55	0	0
T4	19184	8	0	0
T5	2252	56	0	0
T6	1754	26	0	0
T17	1663	42	0	0
T18	1391	0	0	0
T19	1537	9	0	0
T20	1973	13	0	0
T21	2172	68	0	0
T22	1246	42	0	0
T72	0	2	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	381892	0	0
T1	49804	390	0	0
T4	19184	44	0	0
T5	2252	42	0	0
T6	1754	25	0	0
T17	1663	39	0	0
T18	1391	0	0	0
T19	1537	19	0	0
T20	1973	27	0	0
T21	2172	51	0	0
T22	1246	39	0	0
T23	0	17	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		244	244	100.00
ALWAYS	82	4	4	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
ALWAYS	277	4	4	100.00
CONT_ASSIGN	307	1	1	100.00
ALWAYS	320	3	3	100.00
CONT_ASSIGN	349	1	1	100.00
ALWAYS	363	4	4	100.00
CONT_ASSIGN	393	1	1	100.00
ALWAYS	406	3	3	100.00
CONT_ASSIGN	435	1	1	100.00
ALWAYS	449	4	4	100.00
CONT_ASSIGN	479	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	521	1	1	100.00
ALWAYS	535	4	4	100.00
CONT_ASSIGN	565	1	1	100.00
ALWAYS	578	3	3	100.00
CONT_ASSIGN	607	1	1	100.00
ALWAYS	621	4	4	100.00
CONT_ASSIGN	651	1	1	100.00
ALWAYS	664	3	3	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	765	1	1	100.00
CONT_ASSIGN	1253	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1410	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1445	1	1	100.00
CONT_ASSIGN	1568	1	1	100.00
CONT_ASSIGN	1571	1	1	100.00
CONT_ASSIGN	1603	1	1	100.00
CONT_ASSIGN	1726	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1761	1	1	100.00
CONT_ASSIGN	1884	1	1	100.00
CONT_ASSIGN	1887	1	1	100.00
CONT_ASSIGN	1918	1	1	100.00
ALWAYS	2424	23	23	100.00
CONT_ASSIGN	2449	1	1	100.00
ALWAYS	2453	1	1	100.00
CONT_ASSIGN	2479	1	1	100.00
CONT_ASSIGN	2481	1	1	100.00
CONT_ASSIGN	2483	1	1	100.00
CONT_ASSIGN	2484	1	1	100.00
CONT_ASSIGN	2486	1	1	100.00
CONT_ASSIGN	2487	1	1	100.00
CONT_ASSIGN	2489	1	1	100.00
CONT_ASSIGN	2491	1	1	100.00
CONT_ASSIGN	2492	1	1	100.00
CONT_ASSIGN	2493	1	1	100.00
CONT_ASSIGN	2495	1	1	100.00
CONT_ASSIGN	2496	1	1	100.00
CONT_ASSIGN	2498	1	1	100.00
CONT_ASSIGN	2499	1	1	100.00
CONT_ASSIGN	2501	1	1	100.00
CONT_ASSIGN	2503	1	1	100.00
CONT_ASSIGN	2505	1	1	100.00
CONT_ASSIGN	2507	1	1	100.00
CONT_ASSIGN	2508	1	1	100.00
CONT_ASSIGN	2510	1	1	100.00
CONT_ASSIGN	2512	1	1	100.00
CONT_ASSIGN	2514	1	1	100.00
CONT_ASSIGN	2516	1	1	100.00
CONT_ASSIGN	2517	1	1	100.00
CONT_ASSIGN	2519	1	1	100.00
CONT_ASSIGN	2520	1	1	100.00
CONT_ASSIGN	2522	1	1	100.00
CONT_ASSIGN	2523	1	1	100.00
CONT_ASSIGN	2526	1	1	100.00
CONT_ASSIGN	2528	1	1	100.00
CONT_ASSIGN	2529	1	1	100.00
CONT_ASSIGN	2532	1	1	100.00
CONT_ASSIGN	2534	1	1	100.00
CONT_ASSIGN	2535	1	1	100.00
CONT_ASSIGN	2538	1	1	100.00
CONT_ASSIGN	2540	1	1	100.00
CONT_ASSIGN	2541	1	1	100.00
CONT_ASSIGN	2544	1	1	100.00
CONT_ASSIGN	2546	1	1	100.00
CONT_ASSIGN	2547	1	1	100.00
CONT_ASSIGN	2550	1	1	100.00
CONT_ASSIGN	2552	1	1	100.00
CONT_ASSIGN	2554	1	1	100.00
CONT_ASSIGN	2556	1	1	100.00
CONT_ASSIGN	2558	1	1	100.00
CONT_ASSIGN	2560	1	1	100.00
CONT_ASSIGN	2562	1	1	100.00
CONT_ASSIGN	2564	1	1	100.00
CONT_ASSIGN	2566	1	1	100.00
CONT_ASSIGN	2568	1	1	100.00
CONT_ASSIGN	2570	1	1	100.00
CONT_ASSIGN	2572	1	1	100.00
ALWAYS	2576	23	23	100.00
ALWAYS	2603	47	47	100.00
ALWAYS	2717	3	3	100.00
ALWAYS	2725	3	3	100.00
CONT_ASSIGN	2733	1	1	100.00
CONT_ASSIGN	2736	1	1	100.00
CONT_ASSIGN	2748	1	1	100.00
CONT_ASSIGN	2763	1	1	100.00
ALWAYS	2765	12	12	100.00
CONT_ASSIGN	2810	1	1	100.00
CONT_ASSIGN	2811	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
91	1	1
103	1	1
104	1	1
132	1	1
133	1	1
277	1	1
278	1	1
279	1	1
280	1	1
307	1	1
320	1	1
321	1	1
322	1	1
349	1	1
363	1	1
364	1	1
365	1	1
366	1	1
393	1	1
406	1	1
407	1	1
408	1	1
435	1	1
449	1	1
450	1	1
451	1	1
452	1	1
479	1	1
492	1	1
493	1	1
494	1	1
521	1	1
535	1	1
536	1	1
537	1	1
538	1	1
565	1	1
578	1	1
579	1	1
580	1	1
607	1	1
621	1	1
622	1	1
623	1	1
624	1	1
651	1	1
664	1	1
665	1	1
666	1	1
693	1	1
700	1	1
715	1	1
731	1	1
765	1	1
1253	1	1
1256	1	1
1287	1	1
1410	1	1
1413	1	1
1445	1	1
1568	1	1
1571	1	1
1603	1	1
1726	1	1
1729	1	1
1761	1	1
1884	1	1
1887	1	1
1918	1	1
2424	1	1
2425	1	1
2426	1	1
2427	1	1
2428	1	1
2429	1	1
2430	1	1
2431	1	1
2432	1	1
2433	1	1
2434	1	1
2435	1	1
2436	1	1
2437	1	1
2438	1	1
2439	1	1
2440	1	1
2441	1	1
2442	1	1
2443	1	1
2444	1	1
2445	1	1
2446	1	1
2449	1	1
2453	1	1
2479	1	1
2481	1	1
2483	1	1
2484	1	1
2486	1	1
2487	1	1
2489	1	1
2491	1	1
2492	1	1
2493	1	1
2495	1	1
2496	1	1
2498	1	1
2499	1	1
2501	1	1
2503	1	1
2505	1	1
2507	1	1
2508	1	1
2510	1	1
2512	1	1
2514	1	1
2516	1	1
2517	1	1
2519	1	1
2520	1	1
2522	1	1
2523	1	1
2526	1	1
2528	1	1
2529	1	1
2532	1	1
2534	1	1
2535	1	1
2538	1	1
2540	1	1
2541	1	1
2544	1	1
2546	1	1
2547	1	1
2550	1	1
2552	1	1
2554	1	1
2556	1	1
2558	1	1
2560	1	1
2562	1	1
2564	1	1
2566	1	1
2568	1	1
2570	1	1
2572	1	1
2576	1	1
2577	1	1
2578	1	1
2579	1	1
2580	1	1
2581	1	1
2582	1	1
2583	1	1
2584	1	1
2585	1	1
2586	1	1
2587	1	1
2588	1	1
2589	1	1
2590	1	1
2591	1	1
2592	1	1
2593	1	1
2594	1	1
2595	1	1
2596	1	1
2597	1	1
2598	1	1
2603	1	1
2604	1	1
2606	1	1
2607	1	1
2611	1	1
2615	1	1
2616	1	1
2620	1	1
2624	1	1
2628	1	1
2632	1	1
2633	1	1
2634	1	1
2635	1	1
2639	1	1
2640	1	1
2641	1	1
2642	1	1
2646	1	1
2647	1	1
2648	1	1
2649	1	1
2653	1	1
2657	1	1
2660	1	1
2663	1	1
2666	1	1
2669	1	1
2672	1	1
2675	1	1
2678	1	1
2681	1	1
2684	1	1
2687	1	1
2688	1	1
2689	1	1
2690	1	1
2691	1	1
2692	1	1
2693	1	1
2694	1	1
2695	1	1
2696	1	1
2697	1	1
2701	1	1
2702	1	1
2703	1	1
2717	1	1
2718	1	1
2720	1	1
2725	1	1
2726	1	1
2728	1	1
2733	1	1
2736	1	1
2748	1	1
2763	1	1
2765	1	1
2766	1	1
2768	1	1
2771	1	1
2774	1	1
2777	1	1
2780	1	1
2783	1	1
2786	1	1
2789	1	1
2792	1	1
2795	1	1
2810	1	1
2811	1	1

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	289	289	100.00
Logical	289	289	100.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T3,T10,T11
1	1	Covered	T5,T6,T1

 LINE       84
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T40,T41,T42
1	0	Covered	T95,T96,T97

 LINE       91
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T6,T1
0	0	1	Covered	T40,T41,T42
0	1	0	Covered	T95,T96,T97
1	0	0	Covered	T40,T41,T42

 LINE       133
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T5,T6,T1
0	0	1	Covered	T95,T96,T97
0	1	0	Covered	T3,T10,T11
1	0	0	Covered	T3,T10,T11

 LINE       765
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T73,T74,T98
1	1	Covered	T6,T19,T20

 LINE       1256
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1287
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1413
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1445
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1571
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1603
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1729
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1761
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1887
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       1918
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T73,T74,T98
1	1	Covered	T1,T4,T2

 LINE       2425
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T4,T21

 LINE       2426
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T4

 LINE       2427
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T4

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T4

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T4,T21

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T17,T4

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T17

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T17

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T17

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T4,T21

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T4

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T3,T10

 LINE       2449
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       2449
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1

 LINE       2453
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T3,T10,T11

 LINE       2453
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T5,T6,T1
22 (addr_hit[21] & ((|(4'...	Covered	T5,T3,T10
21 (addr_hit[20] & ((|(4'...	Covered	T5,T1,T4
20 (addr_hit[19] & ((|(4'...	Covered	T5,T4,T21
19 (addr_hit[18] & ((|(4'...	Covered	T5,T1,T2
18 (addr_hit[17] & ((|(4'...	Covered	T5,T21,T3
17 (addr_hit[16] & ((|(4'...	Covered	T1,T4,T21
16 (addr_hit[15] & ((|(4'...	Covered	T5,T21,T3
15 (addr_hit[14] & ((|(4'...	Covered	T5,T1,T4
14 (addr_hit[13] & ((|(4'...	Covered	T5,T21,T3
13 (addr_hit[12] & ((|(4'...	Covered	T5,T1,T4
12 (addr_hit[11] & ((|(4'...	Covered	T5,T4,T21
11 (addr_hit[10] & ((|(4'...	Covered	T1,T4,T21
10 (addr_hit[9] & ((|(4'b...	Covered	T5,T1,T2
9 (addr_hit[8] & ((|(4'b...	Covered	T5,T1,T4
8 (addr_hit[7] & ((|(4'b...	Covered	T5,T17,T4
7 (addr_hit[6] & ((|(4'b...	Covered	T5,T21,T22
6 (addr_hit[5] & ((|(4'b...	Covered	T17,T22,T27
5 (addr_hit[4] & ((|(4'b...	Covered	T5,T4,T3
4 (addr_hit[3] & ((|(4'b...	Covered	T5,T6,T4
3 (addr_hit[2] & ((|(4'b...	Covered	T6,T19,T20
2 (addr_hit[1] & ((|(4'b...	Covered	T5,T4,T21
1 (addr_hit[0] & ((|(4'b...	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T4,T21
1	1	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T4
1	1	Covered	T6,T19,T20

 LINE       2453
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T21
1	1	Covered	T5,T6,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T4,T21
1	1	Covered	T5,T4,T3

 LINE       2453
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T17,T4
1	1	Covered	T17,T22,T27

 LINE       2453
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T17,T21
1	1	Covered	T5,T21,T22

 LINE       2453
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T17
1	1	Covered	T5,T17,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T17
1	1	Covered	T5,T1,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T1,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T21,T3

 LINE       2453
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T21,T3

 LINE       2453
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T21
1	1	Covered	T1,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T21,T3

 LINE       2453
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T2

 LINE       2453
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T4,T21

 LINE       2453
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T1,T4,T21
1	1	Covered	T5,T1,T4

 LINE       2453
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T3,T10
1	1	Covered	T5,T3,T10

 LINE       2479
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T4,T21
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T23,T35,T36

 LINE       2484
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T6,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T6,T19,T20

 LINE       2487
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T6,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T6,T19,T20

 LINE       2492
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T6,T4
1	1	0	Covered	T95,T99,T100
1	1	1	Covered	T6,T94,T3

 LINE       2493
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T4,T21
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T77,T78,T101

 LINE       2496
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T17,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T17,T22,T27

 LINE       2499
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T17
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T17,T22

 LINE       2508
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T1,T17
1	0	1	Covered	T5,T1,T17
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T5,T1,T17

 LINE       2517
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2520
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2522
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T95,T102,T100
1	1	1	Covered	T3,T10,T11

 LINE       2523
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2526
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2528
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T103,T104
1	1	1	Covered	T3,T10,T11

 LINE       2529
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2532
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2534
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T97,T105
1	1	1	Covered	T3,T10,T11

 LINE       2535
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2538
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T1,T4,T21
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2540
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T104,T106
1	1	1	Covered	T3,T10,T11

 LINE       2541
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2544
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2546
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T96,T107,T99
1	1	1	Covered	T3,T10,T11

 LINE       2547
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2550
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T6,T1
1	0	1	Covered	T5,T1,T4
1	1	0	Covered	T3,T10,T11
1	1	1	Covered	T1,T4,T2

 LINE       2733
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T54,T55,T56
1	0	Covered	T108,T109,T110
1	1	Covered	T5,T6,T1

 LINE       2763
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Covered	T5,T4,T21
1	0	Covered	T1,T4,T2

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	2449	2	2	100.00
IF	82	3	3	100.00
CASE	2604	23	23	100.00
IF	2717	2	2	100.00
IF	2725	2	2	100.00
CASE	2766	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2449	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	82	if ((!rst_ni))
-2-:	84	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T1
0	1	Covered	T40,T41,T42
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	2604	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T5,T6,T1
addr_hit[1]	Covered	T5,T6,T1
addr_hit[2]	Covered	T5,T6,T1
addr_hit[3]	Covered	T5,T6,T1
addr_hit[4]	Covered	T5,T6,T1
addr_hit[5]	Covered	T5,T6,T1
addr_hit[6]	Covered	T5,T6,T1
addr_hit[7]	Covered	T5,T6,T1
addr_hit[8]	Covered	T5,T6,T1
addr_hit[9]	Covered	T5,T6,T1
addr_hit[10]	Covered	T5,T6,T1
addr_hit[11]	Covered	T5,T6,T1
addr_hit[12]	Covered	T5,T6,T1
addr_hit[13]	Covered	T5,T6,T1
addr_hit[14]	Covered	T5,T6,T1
addr_hit[15]	Covered	T5,T6,T1
addr_hit[16]	Covered	T6,T1,T17
addr_hit[17]	Covered	T5,T6,T1
addr_hit[18]	Covered	T5,T6,T1
addr_hit[19]	Covered	T5,T6,T1
addr_hit[20]	Covered	T5,T6,T1
addr_hit[21]	Covered	T5,T6,T1
default	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	2717	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	2725	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	2766	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[10]	Covered	T5,T6,T1
addr_hit[11]	Covered	T5,T6,T1
addr_hit[12]	Covered	T5,T6,T1
addr_hit[13]	Covered	T5,T6,T1
addr_hit[14]	Covered	T5,T6,T1
addr_hit[15]	Covered	T5,T6,T1
addr_hit[16]	Covered	T6,T1,T17
addr_hit[17]	Covered	T5,T6,T1
addr_hit[18]	Covered	T5,T6,T1
addr_hit[19]	Covered	T5,T6,T1
default	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	94293783	521067	0	0
reAfterRv	94293783	521067	0	0
rePulse	94293783	139175	0	0
wePulse	94293783	381892	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	521067	0	0
T1	49804	445	0	0
T4	19184	52	0	0
T5	2252	98	0	0
T6	1754	51	0	0
T17	1663	81	0	0
T18	1391	0	0	0
T19	1537	28	0	0
T20	1973	40	0	0
T21	2172	119	0	0
T22	1246	81	0	0
T23	0	17	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	521067	0	0
T1	49804	445	0	0
T4	19184	52	0	0
T5	2252	98	0	0
T6	1754	51	0	0
T17	1663	81	0	0
T18	1391	0	0	0
T19	1537	28	0	0
T20	1973	40	0	0
T21	2172	119	0	0
T22	1246	81	0	0
T23	0	17	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	139175	0	0
T1	49804	55	0	0
T4	19184	8	0	0
T5	2252	56	0	0
T6	1754	26	0	0
T17	1663	42	0	0
T18	1391	0	0	0
T19	1537	9	0	0
T20	1973	13	0	0
T21	2172	68	0	0
T22	1246	42	0	0
T72	0	2	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	381892	0	0
T1	49804	390	0	0
T4	19184	44	0	0
T5	2252	42	0	0
T6	1754	25	0	0
T17	1663	39	0	0
T18	1391	0	0	0
T19	1537	19	0	0
T20	1973	27	0	0
T21	2172	51	0	0
T22	1246	39	0	0
T23	0	17	0	0