Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Unreachable
1	0	Covered	T1,T3,T10

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	93345215	91085818	0	0
AllClkBypReqTrue_A	93345215	82546	0	0
IoClkBypReqFalse_A	93345215	91029406	0	2334
IoClkBypReqTrue_A	93345215	134556	0	0
LcClkBypAckFalse_A	93345215	91091393	0	0
LcClkBypAckTrue_A	93345215	76971	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	91085818	0	0
T1	49804	49721	0	0
T4	19184	18978	0	0
T5	2252	2167	0	0
T6	1754	1487	0	0
T17	1663	1618	0	0
T18	1391	1294	0	0
T19	1537	1369	0	0
T20	1973	1727	0	0
T21	2172	2110	0	0
T22	1246	1231	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	82546	0	0
T1	49804	0	0	0
T3	0	2469	0	0
T4	19184	0	0	0
T6	1754	181	0	0
T10	0	1698	0	0
T17	1663	0	0	0
T18	1391	0	0	0
T19	1537	124	0	0
T20	1973	222	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T28	0	114	0	0
T72	0	4	0	0
T94	0	71	0	0
T111	0	247	0	0
T112	0	122	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	91029406	0	2334
T1	49804	49717	0	3
T4	19184	18976	0	3
T5	2252	2165	0	3
T6	1754	1383	0	3
T17	1663	1616	0	3
T18	1391	1292	0	3
T19	1537	1187	0	3
T20	1973	1523	0	3
T21	2172	2108	0	3
T22	1246	1229	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	134556	0	0
T1	49804	0	0	0
T3	0	2929	0	0
T4	19184	0	0	0
T6	1754	283	0	0
T10	0	2748	0	0
T17	1663	0	0	0
T18	1391	0	0	0
T19	1537	304	0	0
T20	1973	424	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T28	0	130	0	0
T29	0	331	0	0
T94	0	83	0	0
T111	0	407	0	0
T112	0	139	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	91091393	0	0
T1	49804	49721	0	0
T4	19184	18978	0	0
T5	2252	2167	0	0
T6	1754	1581	0	0
T17	1663	1618	0	0
T18	1391	1294	0	0
T19	1537	1343	0	0
T20	1973	1796	0	0
T21	2172	2110	0	0
T22	1246	1231	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	76971	0	0
T1	49804	0	0	0
T3	0	1921	0	0
T4	19184	0	0	0
T6	1754	87	0	0
T10	0	1631	0	0
T17	1663	0	0	0
T18	1391	0	0	0
T19	1537	150	0	0
T20	1973	153	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T28	0	78	0	0
T29	0	172	0	0
T94	0	46	0	0
T111	0	191	0	0
T112	0	82	0	0