Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1037440948	10132	0	0
TransStop_A	1037440948	5269	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037440948	10132	0	0
T1	830092	4	0	0
T3	0	401	0	0
T4	79108	0	0	0
T5	18024	28	0	0
T6	12768	0	0	0
T10	0	217	0	0
T17	27736	4	0	0
T18	10172	0	0	0
T19	36184	0	0	0
T20	32896	0	0	0
T21	36220	37	0	0
T22	83136	4	0	0
T27	0	4	0	0
T31	0	4	0	0
T85	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1037440948	5269	0	0
T1	830092	0	0	0
T3	0	169	0	0
T4	79108	0	0	0
T5	18024	10	0	0
T6	12768	0	0	0
T10	0	110	0	0
T11	0	45	0	0
T17	27736	4	0	0
T18	10172	0	0	0
T19	36184	0	0	0
T20	32896	0	0	0
T21	36220	25	0	0
T22	83136	4	0	0
T27	0	4	0	0
T31	0	4	0	0
T85	0	4	0	0
T113	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	259360237	2550	0	0
TransStop_A	259360237	1310	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259360237	2550	0	0
T1	207523	1	0	0
T3	0	109	0	0
T4	19777	0	0	0
T5	4506	5	0	0
T6	3192	0	0	0
T10	0	64	0	0
T17	6934	1	0	0
T18	2543	0	0	0
T19	9046	0	0	0
T20	8224	0	0	0
T21	9055	6	0	0
T22	20784	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T85	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259360237	1310	0	0
T1	207523	0	0	0
T3	0	47	0	0
T4	19777	0	0	0
T5	4506	2	0	0
T6	3192	0	0	0
T10	0	30	0	0
T11	0	7	0	0
T17	6934	1	0	0
T18	2543	0	0	0
T19	9046	0	0	0
T20	8224	0	0	0
T21	9055	4	0	0
T22	20784	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	259360237	2560	0	0
TransStop_A	259360237	1316	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259360237	2560	0	0
T1	207523	1	0	0
T3	0	102	0	0
T4	19777	0	0	0
T5	4506	8	0	0
T6	3192	0	0	0
T10	0	58	0	0
T17	6934	1	0	0
T18	2543	0	0	0
T19	9046	0	0	0
T20	8224	0	0	0
T21	9055	10	0	0
T22	20784	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T85	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259360237	1316	0	0
T1	207523	0	0	0
T3	0	42	0	0
T4	19777	0	0	0
T5	4506	3	0	0
T6	3192	0	0	0
T10	0	32	0	0
T11	0	9	0	0
T17	6934	1	0	0
T18	2543	0	0	0
T19	9046	0	0	0
T20	8224	0	0	0
T21	9055	8	0	0
T22	20784	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T85	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	259360237	2516	0	0
TransStop_A	259360237	1319	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259360237	2516	0	0
T1	207523	1	0	0
T3	0	100	0	0
T4	19777	0	0	0
T5	4506	8	0	0
T6	3192	0	0	0
T10	0	47	0	0
T17	6934	1	0	0
T18	2543	0	0	0
T19	9046	0	0	0
T20	8224	0	0	0
T21	9055	13	0	0
T22	20784	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T85	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259360237	1319	0	0
T1	207523	0	0	0
T3	0	38	0	0
T4	19777	0	0	0
T5	4506	3	0	0
T6	3192	0	0	0
T10	0	25	0	0
T11	0	13	0	0
T17	6934	1	0	0
T18	2543	0	0	0
T19	9046	0	0	0
T20	8224	0	0	0
T21	9055	7	0	0
T22	20784	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	259360237	2506	0	0
TransStop_A	259360237	1324	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259360237	2506	0	0
T1	207523	1	0	0
T3	0	90	0	0
T4	19777	0	0	0
T5	4506	7	0	0
T6	3192	0	0	0
T10	0	48	0	0
T17	6934	1	0	0
T18	2543	0	0	0
T19	9046	0	0	0
T20	8224	0	0	0
T21	9055	8	0	0
T22	20784	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T85	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259360237	1324	0	0
T1	207523	0	0	0
T3	0	42	0	0
T4	19777	0	0	0
T5	4506	2	0	0
T6	3192	0	0	0
T10	0	23	0	0
T11	0	16	0	0
T17	6934	1	0	0
T18	2543	0	0	0
T19	9046	0	0	0
T20	8224	0	0	0
T21	9055	6	0	0
T22	20784	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T85	0	2	0	0