Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	94293783	2709497	0	0
clk_enables_rd_A	94293783	23469	0	0
clk_hints_rd_A	94293783	20752	0	0
extclk_ctrl_rd_A	94293783	23887	0	0
extclk_ctrl_regwen_rd_A	94293783	18159	0	0
jitter_enable_rd_A	94293783	29594	0	0
jitter_regwen_rd_A	94293783	20657	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	2709497	0	0
T3	419568	122288	0	0
T10	390529	171129	0	0
T11	0	60571	0	0
T25	13366	0	0	0
T28	1718	0	0	0
T29	1771	0	0	0
T30	25755	0	0	0
T31	1417	0	0	0
T34	1224	0	0	0
T63	0	169490	0	0
T64	0	44708	0	0
T65	0	137986	0	0
T66	0	95688	0	0
T67	0	143337	0	0
T68	0	76974	0	0
T69	0	64380	0	0
T70	2040	0	0	0
T71	1316	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	23469	0	0
T3	419568	4603	0	0
T10	390529	0	0	0
T15	0	4	0	0
T25	13366	0	0	0
T26	0	8	0	0
T28	1718	0	0	0
T29	1771	0	0	0
T30	25755	0	0	0
T31	1417	0	0	0
T34	1224	0	0	0
T70	2040	0	0	0
T71	1316	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	3	0	0
T134	0	2	0	0
T135	0	8	0	0
T136	0	4	0	0
T137	0	2	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	20752	0	0
T3	419568	4011	0	0
T10	390529	0	0	0
T15	0	9	0	0
T25	13366	0	0	0
T26	0	11	0	0
T28	1718	0	0	0
T29	1771	0	0	0
T30	25755	0	0	0
T31	1417	0	0	0
T34	1224	0	0	0
T70	2040	0	0	0
T71	1316	0	0	0
T131	0	3	0	0
T133	0	6	0	0
T134	0	5	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	23887	0	0
T3	0	4733	0	0
T19	1537	31	0	0
T20	1973	42	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	0	0	0
T28	0	7	0	0
T29	0	37	0	0
T35	1534	0	0	0
T71	0	15	0	0
T72	947	0	0	0
T73	0	50	0	0
T94	914	0	0	0
T111	2059	47	0	0
T139	0	30	0	0
T140	0	30	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	18159	0	0
T3	419568	4033	0	0
T10	390529	0	0	0
T25	13366	0	0	0
T28	1718	0	0	0
T29	1771	0	0	0
T30	25755	0	0	0
T31	1417	0	0	0
T34	1224	0	0	0
T67	0	2435	0	0
T68	0	1224	0	0
T69	0	2014	0	0
T70	2040	0	0	0
T71	1316	0	0	0
T73	0	26	0	0
T141	0	39	0	0
T142	0	24	0	0
T143	0	23	0	0
T144	0	77	0	0
T145	0	4	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	29594	0	0
T3	419568	5971	0	0
T10	390529	0	0	0
T15	0	224	0	0
T25	13366	0	0	0
T26	0	224	0	0
T28	1718	0	0	0
T29	1771	0	0	0
T30	25755	0	0	0
T31	1417	0	0	0
T34	1224	0	0	0
T70	2040	0	0	0
T71	1316	0	0	0
T131	0	126	0	0
T132	0	156	0	0
T133	0	108	0	0
T134	0	113	0	0
T135	0	111	0	0
T138	0	71	0	0
T146	0	70	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94293783	20657	0	0
T3	419568	4849	0	0
T10	390529	0	0	0
T25	13366	0	0	0
T28	1718	0	0	0
T29	1771	0	0	0
T30	25755	0	0	0
T31	1417	0	0	0
T34	1224	0	0	0
T67	0	3284	0	0
T68	0	1438	0	0
T69	0	2504	0	0
T70	2040	0	0	0
T71	1316	0	0	0
T80	0	30	0	0
T147	0	3074	0	0
T148	0	1783	0	0
T149	0	1103	0	0
T150	0	13	0	0
T151	0	25	0	0