Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	280035645	365	0	0
StatusRise_A	280035645	365	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280035645	365	0	0
T4	57552	0	0	0
T18	4173	15	0	0
T19	4611	0	0	0
T20	5919	0	0	0
T21	6516	0	0	0
T22	3738	0	0	0
T23	6354	0	0	0
T24	3345	2	0	0
T34	0	16	0	0
T39	0	6	0	0
T72	2841	0	0	0
T94	2742	0	0	0
T152	0	3	0	0
T153	0	2	0	0
T154	0	9	0	0
T155	0	6	0	0
T156	0	6	0	0
T157	0	7	0	0
T158	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	280035645	365	0	0
T4	57552	0	0	0
T18	4173	15	0	0
T19	4611	0	0	0
T20	5919	0	0	0
T21	6516	0	0	0
T22	3738	0	0	0
T23	6354	0	0	0
T24	3345	2	0	0
T34	0	16	0	0
T39	0	6	0	0
T72	2841	0	0	0
T94	2742	0	0	0
T152	0	3	0	0
T153	0	2	0	0
T154	0	9	0	0
T155	0	6	0	0
T156	0	6	0	0
T157	0	7	0	0
T158	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	93345215	129	0	0
StatusRise_A	93345215	129	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	129	0	0
T4	19184	0	0	0
T18	1391	5	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	1	0	0
T34	0	6	0	0
T39	0	3	0	0
T72	947	0	0	0
T94	914	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	129	0	0
T4	19184	0	0	0
T18	1391	5	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	1	0	0
T34	0	6	0	0
T39	0	3	0	0
T72	947	0	0	0
T94	914	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	93345215	114	0	0
StatusRise_A	93345215	114	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	114	0	0
T4	19184	0	0	0
T18	1391	5	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	947	0	0	0
T94	914	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	114	0	0
T4	19184	0	0	0
T18	1391	5	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	947	0	0	0
T94	914	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	93345215	122	0	0
StatusRise_A	93345215	122	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	122	0	0
T4	19184	0	0	0
T18	1391	5	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	0	0	0
T34	0	5	0	0
T39	0	2	0	0
T72	947	0	0	0
T94	914	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93345215	122	0	0
T4	19184	0	0	0
T18	1391	5	0	0
T19	1537	0	0	0
T20	1973	0	0	0
T21	2172	0	0	0
T22	1246	0	0	0
T23	2118	0	0	0
T24	1115	0	0	0
T34	0	5	0	0
T39	0	2	0	0
T72	947	0	0	0
T94	914	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	6	0	0