Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	34410	0	0
CgEnOn_A	2147483647	25608	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34410	0	0
T1	1278220	32	0	0
T3	0	109	0	0
T4	213446	3	0	0
T5	27650	8	0	0
T6	19814	3	0	0
T17	42667	7	0	0
T18	26834	48	0	0
T19	99822	3	0	0
T20	90246	3	0	0
T21	97566	9	0	0
T22	224188	7	0	0
T23	10106	0	0	0
T24	5101	6	0	0
T27	0	1	0	0
T34	0	25	0	0
T39	0	8	0	0
T72	19230	0	0	0
T94	27947	0	0	0
T152	0	5	0	0
T154	0	15	0	0
T155	0	5	0	0
T156	0	10	0	0
T157	0	10	0	0
T158	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25608	0	0
T1	1278220	37	0	0
T3	0	860	0	0
T4	213446	0	0	0
T5	18020	28	0	0
T6	12764	0	0	0
T10	0	289	0	0
T17	42667	8	0	0
T18	26834	80	0	0
T19	99822	0	0	0
T20	90246	0	0	0
T21	97566	37	0	0
T22	224188	8	0	0
T23	14792	0	0	0
T24	7490	14	0	0
T27	0	8	0	0
T31	0	4	0	0
T34	0	47	0	0
T39	0	30	0	0
T72	19230	0	0	0
T94	27947	0	0	0
T152	0	8	0	0
T153	0	3	0	0
T154	0	24	0	0
T155	0	13	0	0
T156	0	16	0	0
T157	0	17	0	0
T158	0	21	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120524037	116	0	0
CgEnOn_A	120524037	116	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120524037	116	0	0
T4	9459	0	0	0
T18	1109	5	0	0
T19	4874	0	0	0
T20	4307	0	0	0
T21	4292	0	0	0
T22	9909	0	0	0
T23	1006	0	0	0
T24	508	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	2025	0	0	0
T94	4185	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120524037	116	0	0
T4	9459	0	0	0
T18	1109	5	0	0
T19	4874	0	0	0
T20	4307	0	0	0
T21	4292	0	0	0
T22	9909	0	0	0
T23	1006	0	0	0
T24	508	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	2025	0	0	0
T94	4185	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	60261620	116	0	0
CgEnOn_A	60261620	116	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60261620	116	0	0
T4	4730	0	0	0
T18	554	5	0	0
T19	2437	0	0	0
T20	2153	0	0	0
T21	2146	0	0	0
T22	4954	0	0	0
T23	503	0	0	0
T24	254	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	1012	0	0	0
T94	2093	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60261620	116	0	0
T4	4730	0	0	0
T18	554	5	0	0
T19	2437	0	0	0
T20	2153	0	0	0
T21	2146	0	0	0
T22	4954	0	0	0
T23	503	0	0	0
T24	254	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	1012	0	0	0
T94	2093	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	60261620	116	0	0
CgEnOn_A	60261620	116	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60261620	116	0	0
T4	4730	0	0	0
T18	554	5	0	0
T19	2437	0	0	0
T20	2153	0	0	0
T21	2146	0	0	0
T22	4954	0	0	0
T23	503	0	0	0
T24	254	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	1012	0	0	0
T94	2093	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60261620	116	0	0
T4	4730	0	0	0
T18	554	5	0	0
T19	2437	0	0	0
T20	2153	0	0	0
T21	2146	0	0	0
T22	4954	0	0	0
T23	503	0	0	0
T24	254	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	1012	0	0	0
T94	2093	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	60261620	116	0	0
CgEnOn_A	60261620	116	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60261620	116	0	0
T4	4730	0	0	0
T18	554	5	0	0
T19	2437	0	0	0
T20	2153	0	0	0
T21	2146	0	0	0
T22	4954	0	0	0
T23	503	0	0	0
T24	254	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	1012	0	0	0
T94	2093	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60261620	116	0	0
T4	4730	0	0	0
T18	554	5	0	0
T19	2437	0	0	0
T20	2153	0	0	0
T21	2146	0	0	0
T22	4954	0	0	0
T23	503	0	0	0
T24	254	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	1012	0	0	0
T94	2093	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	242714931	116	0	0
CgEnOn_A	242714931	114	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242714931	116	0	0
T4	18984	0	0	0
T18	2311	5	0	0
T19	8683	0	0	0
T20	7894	0	0	0
T21	8691	0	0	0
T22	19952	0	0	0
T23	2118	0	0	0
T24	1082	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	3954	0	0	0
T94	4879	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242714931	114	0	0
T4	18984	0	0	0
T18	2311	5	0	0
T19	8683	0	0	0
T20	7894	0	0	0
T21	8691	0	0	0
T22	19952	0	0	0
T23	2118	0	0	0
T24	1082	1	0	0
T34	0	5	0	0
T39	0	1	0	0
T72	3954	0	0	0
T94	4879	0	0	0
T152	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	259359799	129	0	0
CgEnOn_A	259359799	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	129	0	0
T4	19776	0	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	0	0	0
T22	20783	0	0	0
T23	2207	0	0	0
T24	1102	1	0	0
T34	0	6	0	0
T39	0	3	0	0
T72	4119	0	0	0
T94	5082	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	129	0	0
T4	19776	0	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	0	0	0
T22	20783	0	0	0
T23	2207	0	0	0
T24	1102	1	0	0
T34	0	6	0	0
T39	0	3	0	0
T72	4119	0	0	0
T94	5082	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	259359799	129	0	0
CgEnOn_A	259359799	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	129	0	0
T4	19776	0	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	0	0	0
T22	20783	0	0	0
T23	2207	0	0	0
T24	1102	1	0	0
T34	0	6	0	0
T39	0	3	0	0
T72	4119	0	0	0
T94	5082	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	129	0	0
T4	19776	0	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	0	0	0
T22	20783	0	0	0
T23	2207	0	0	0
T24	1102	1	0	0
T34	0	6	0	0
T39	0	3	0	0
T72	4119	0	0	0
T94	5082	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T39
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	124267169	122	0	0
CgEnOn_A	124267169	122	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124267169	122	0	0
T4	9492	0	0	0
T18	1260	5	0	0
T19	4342	0	0	0
T20	3947	0	0	0
T21	4346	0	0	0
T22	9976	0	0	0
T23	1059	0	0	0
T24	545	0	0	0
T34	0	5	0	0
T39	0	2	0	0
T72	1977	0	0	0
T94	2440	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124267169	122	0	0
T4	9492	0	0	0
T18	1260	5	0	0
T19	4342	0	0	0
T20	3947	0	0	0
T21	4346	0	0	0
T22	9976	0	0	0
T23	1059	0	0	0
T24	545	0	0	0
T34	0	5	0	0
T39	0	2	0	0
T72	1977	0	0	0
T94	2440	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T24,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	60261620	5665	0	0
CgEnOn_A	60261620	3466	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60261620	5665	0	0
T1	49767	10	0	0
T4	4730	1	0	0
T5	1048	1	0	0
T6	819	1	0	0
T17	1651	2	0	0
T18	554	6	0	0
T19	2437	1	0	0
T20	2153	1	0	0
T21	2146	1	0	0
T22	4954	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60261620	3466	0	0
T1	49767	8	0	0
T3	0	111	0	0
T4	4730	0	0	0
T10	0	69	0	0
T17	1651	1	0	0
T18	554	5	0	0
T19	2437	0	0	0
T20	2153	0	0	0
T21	2146	0	0	0
T22	4954	1	0	0
T23	503	0	0	0
T24	254	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T24,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	120524037	5719	0	0
CgEnOn_A	120524037	3520	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120524037	5719	0	0
T1	99534	11	0	0
T4	9459	1	0	0
T5	2095	1	0	0
T6	1637	1	0	0
T17	3302	2	0	0
T18	1109	6	0	0
T19	4874	1	0	0
T20	4307	1	0	0
T21	4292	1	0	0
T22	9909	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120524037	3520	0	0
T1	99534	9	0	0
T3	0	116	0	0
T4	9459	0	0	0
T10	0	76	0	0
T17	3302	1	0	0
T18	1109	5	0	0
T19	4874	0	0	0
T20	4307	0	0	0
T21	4292	0	0	0
T22	9909	1	0	0
T23	1006	0	0	0
T24	508	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T24,T39
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	242714931	5718	0	0
CgEnOn_A	242714931	3517	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242714931	5718	0	0
T1	199215	10	0	0
T4	18984	1	0	0
T5	4324	1	0	0
T6	3063	1	0	0
T17	6655	2	0	0
T18	2311	6	0	0
T19	8683	1	0	0
T20	7894	1	0	0
T21	8691	1	0	0
T22	19952	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242714931	3517	0	0
T1	199215	8	0	0
T3	0	112	0	0
T4	18984	0	0	0
T10	0	71	0	0
T17	6655	1	0	0
T18	2311	5	0	0
T19	8683	0	0	0
T20	7894	0	0	0
T21	8691	0	0	0
T22	19952	1	0	0
T23	2118	0	0	0
T24	1082	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T39	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T39,T34
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	124267169	5700	0	0
CgEnOn_A	124267169	3499	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124267169	5700	0	0
T1	99612	10	0	0
T4	9492	1	0	0
T5	2163	1	0	0
T6	1531	1	0	0
T17	3327	2	0	0
T18	1260	6	0	0
T19	4342	1	0	0
T20	3947	1	0	0
T21	4346	1	0	0
T22	9976	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124267169	3499	0	0
T1	99612	8	0	0
T3	0	120	0	0
T4	9492	0	0	0
T10	0	73	0	0
T17	3327	1	0	0
T18	1260	5	0	0
T19	4342	0	0	0
T20	3947	0	0	0
T21	4346	0	0	0
T22	9976	1	0	0
T23	1059	0	0	0
T24	545	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T34	0	5	0	0
T39	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T5,T1,T17
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	259359799	2679	0	0
CgEnOn_A	259359799	2679	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	2679	0	0
T1	207523	1	0	0
T3	0	109	0	0
T4	19776	0	0	0
T5	4505	5	0	0
T6	3191	0	0	0
T17	6933	1	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	6	0	0
T22	20783	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T39	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	2679	0	0
T1	207523	1	0	0
T3	0	109	0	0
T4	19776	0	0	0
T5	4505	5	0	0
T6	3191	0	0	0
T17	6933	1	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	6	0	0
T22	20783	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T39	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T5,T1,T17
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	259359799	2689	0	0
CgEnOn_A	259359799	2689	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	2689	0	0
T1	207523	1	0	0
T3	0	102	0	0
T4	19776	0	0	0
T5	4505	8	0	0
T6	3191	0	0	0
T17	6933	1	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	10	0	0
T22	20783	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T39	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	2689	0	0
T1	207523	1	0	0
T3	0	102	0	0
T4	19776	0	0	0
T5	4505	8	0	0
T6	3191	0	0	0
T17	6933	1	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	10	0	0
T22	20783	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T39	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T5,T1,T17
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	259359799	2645	0	0
CgEnOn_A	259359799	2645	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	2645	0	0
T1	207523	1	0	0
T3	0	100	0	0
T4	19776	0	0	0
T5	4505	8	0	0
T6	3191	0	0	0
T17	6933	1	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	13	0	0
T22	20783	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T39	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	2645	0	0
T1	207523	1	0	0
T3	0	100	0	0
T4	19776	0	0	0
T5	4505	8	0	0
T6	3191	0	0	0
T17	6933	1	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	13	0	0
T22	20783	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T39	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T24
1	0	Covered	T5,T1,T17
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	259359799	2635	0	0
CgEnOn_A	259359799	2635	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	2635	0	0
T1	207523	1	0	0
T3	0	90	0	0
T4	19776	0	0	0
T5	4505	7	0	0
T6	3191	0	0	0
T17	6933	1	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	8	0	0
T22	20783	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T39	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	259359799	2635	0	0
T1	207523	1	0	0
T3	0	90	0	0
T4	19776	0	0	0
T5	4505	7	0	0
T6	3191	0	0	0
T17	6933	1	0	0
T18	2543	5	0	0
T19	9046	0	0	0
T20	8223	0	0	0
T21	9054	8	0	0
T22	20783	1	0	0
T24	0	1	0	0
T27	0	1	0	0
T39	0	3	0	0