Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 137704506 1 T7 38980 T10 3834 T11 4152
auto[1] 246060 1 T10 900 T28 618 T29 1022


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 137669230 1 T7 38980 T10 3992 T11 4152
auto[1] 281336 1 T10 742 T28 540 T29 888


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 137615686 1 T7 38980 T10 3810 T11 4152
auto[1] 334880 1 T10 924 T28 766 T29 946


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 134279680 1 T7 38980 T10 750 T11 4152
auto[1] 3670886 1 T10 3984 T28 4298 T29 2164


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 91194398 1 T7 38980 T10 4024 T11 4116
auto[1] 46756168 1 T10 710 T11 36 T28 524


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 88948758 1 T7 38980 T10 308 T11 4116
auto[0] auto[0] auto[0] auto[0] auto[1] 45075004 1 T10 92 T11 36 T28 70
auto[0] auto[0] auto[0] auto[1] auto[0] 18544 1 T10 46 T28 46 T29 118
auto[0] auto[0] auto[0] auto[1] auto[1] 4666 1 T10 16 T29 8 T33 8
auto[0] auto[0] auto[1] auto[0] auto[0] 1854050 1 T10 2766 T28 3224 T29 722
auto[0] auto[0] auto[1] auto[0] auto[1] 1608810 1 T10 334 T28 306 T29 448
auto[0] auto[0] auto[1] auto[1] auto[0] 27516 1 T10 84 T28 64 T29 68
auto[0] auto[0] auto[1] auto[1] auto[1] 7874 1 T10 20 T28 86 T29 76
auto[0] auto[1] auto[0] auto[0] auto[0] 37566 1 T10 8 T28 40 T29 56
auto[0] auto[1] auto[0] auto[0] auto[1] 1002 1 T29 36 T33 16 T91 58
auto[0] auto[1] auto[0] auto[1] auto[0] 7444 1 T10 66 T102 76 T139 68
auto[0] auto[1] auto[0] auto[1] auto[1] 1672 1 T33 66 T91 156 T18 62
auto[0] auto[1] auto[1] auto[0] auto[0] 5950 1 T28 18 T29 38 T97 2
auto[0] auto[1] auto[1] auto[0] auto[1] 1520 1 T10 8 T29 28 T99 34
auto[0] auto[1] auto[1] auto[1] auto[0] 11978 1 T28 58 T29 86 T97 40
auto[0] auto[1] auto[1] auto[1] auto[1] 3332 1 T10 62 T179 40 T180 54
auto[1] auto[0] auto[0] auto[0] auto[0] 38788 1 T28 8 T29 8 T31 66
auto[1] auto[0] auto[0] auto[0] auto[1] 2882 1 T160 66 T91 12 T92 70
auto[1] auto[0] auto[0] auto[1] auto[0] 17688 1 T28 68 T29 90 T33 50
auto[1] auto[0] auto[0] auto[1] auto[1] 4808 1 T91 74 T92 62 T96 66
auto[1] auto[0] auto[1] auto[0] auto[0] 15898 1 T10 52 T28 132 T29 56
auto[1] auto[0] auto[1] auto[0] auto[1] 4292 1 T10 64 T28 14 T29 14
auto[1] auto[0] auto[1] auto[1] auto[0] 31086 1 T10 210 T28 120 T29 66
auto[1] auto[0] auto[1] auto[1] auto[1] 8566 1 T29 68 T97 42 T140 42
auto[1] auto[1] auto[0] auto[0] auto[0] 75990 1 T10 60 T28 58 T31 62
auto[1] auto[1] auto[0] auto[0] auto[1] 3968 1 T10 8 T28 34 T29 66
auto[1] auto[1] auto[0] auto[1] auto[0] 33026 1 T10 66 T28 56 T102 116
auto[1] auto[1] auto[0] auto[1] auto[1] 7874 1 T10 80 T29 84 T102 70
auto[1] auto[1] auto[1] auto[0] auto[0] 23272 1 T10 108 T28 142 T29 102
auto[1] auto[1] auto[1] auto[0] auto[1] 6756 1 T10 26 T28 14 T29 34
auto[1] auto[1] auto[1] auto[1] auto[0] 46844 1 T10 250 T28 120 T29 156
auto[1] auto[1] auto[1] auto[1] auto[1] 13142 1 T29 202 T50 124 T14 282

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