| | | | | | | |
tb.dut.AlertsKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.AllClkBypReqKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.CgEnKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.ClocksKownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.FpvSecCmClkMainAesCountCheck_A
| 0 | 0 | 70281161 | 36 | 0 | 0 |
|
tb.dut.FpvSecCmClkMainHmacCountCheck_A
| 0 | 0 | 70281161 | 36 | 0 | 0 |
|
tb.dut.FpvSecCmClkMainKmacCountCheck_A
| 0 | 0 | 70281161 | 34 | 0 | 0 |
|
tb.dut.FpvSecCmClkMainOtbnCountCheck_A
| 0 | 0 | 70281161 | 38 | 0 | 0 |
|
tb.dut.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 70281161 | 70 | 0 | 0 |
|
tb.dut.IoClkBypReqKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.JitterEnableKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.LcCtrlClkBypAckKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.PwrMgrKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.TlAReadyKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.TlDValidKnownO_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A
| 0 | 0 | 240016220 | 2044 | 0 | 0 |
|
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A
| 0 | 0 | 240016220 | 1101 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A
| 0 | 0 | 111800817 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A
| 0 | 0 | 111800817 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A
| 0 | 0 | 111800817 | 4908 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A
| 0 | 0 | 111800817 | 2840 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A
| 0 | 0 | 55900042 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A
| 0 | 0 | 55900042 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A
| 0 | 0 | 55900042 | 4862 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A
| 0 | 0 | 55900042 | 2794 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A
| 0 | 0 | 55900042 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A
| 0 | 0 | 55900042 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A
| 0 | 0 | 55900042 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A
| 0 | 0 | 55900042 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_infra.CgEnOff_A
| 0 | 0 | 225073845 | 154 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_infra.CgEnOn_A
| 0 | 0 | 225073845 | 151 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_peri.CgEnOff_A
| 0 | 0 | 225073845 | 4881 | 0 | 0 |
|
tb.dut.clkmgr_cg_io_peri.CgEnOn_A
| 0 | 0 | 225073845 | 2810 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_aes.CgEnOff_A
| 0 | 0 | 240015796 | 2187 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_aes.CgEnOn_A
| 0 | 0 | 240015796 | 2187 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A
| 0 | 0 | 240015796 | 2261 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A
| 0 | 0 | 240015796 | 2261 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_infra.CgEnOff_A
| 0 | 0 | 240015796 | 143 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_infra.CgEnOn_A
| 0 | 0 | 240015796 | 143 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A
| 0 | 0 | 240015796 | 2164 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A
| 0 | 0 | 240015796 | 2164 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A
| 0 | 0 | 240015796 | 2165 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A
| 0 | 0 | 240015796 | 2165 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_secure.CgEnOff_A
| 0 | 0 | 240015796 | 143 | 0 | 0 |
|
tb.dut.clkmgr_cg_main_secure.CgEnOn_A
| 0 | 0 | 240015796 | 143 | 0 | 0 |
|
tb.dut.clkmgr_cg_usb_infra.CgEnOff_A
| 0 | 0 | 115245515 | 141 | 0 | 0 |
|
tb.dut.clkmgr_cg_usb_infra.CgEnOn_A
| 0 | 0 | 115245515 | 141 | 0 | 0 |
|
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A
| 0 | 0 | 115245515 | 4859 | 0 | 0 |
|
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A
| 0 | 0 | 115245515 | 2787 | 0 | 0 |
|
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A
| 0 | 0 | 71256824 | 1803638 | 0 | 0 |
|
tb.dut.clkmgr_csr_assert.clk_enables_rd_A
| 0 | 0 | 71256824 | 19421 | 0 | 0 |
|
tb.dut.clkmgr_csr_assert.clk_hints_rd_A
| 0 | 0 | 71256824 | 17341 | 0 | 0 |
|
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A
| 0 | 0 | 71256824 | 21499 | 0 | 0 |
|
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A
| 0 | 0 | 71256824 | 16524 | 0 | 0 |
|
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A
| 0 | 0 | 71256824 | 25004 | 0 | 0 |
|
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A
| 0 | 0 | 71256824 | 17402 | 0 | 0 |
|
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A
| 0 | 0 | 225074271 | 2714 | 0 | 0 |
|
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A
| 0 | 0 | 225074271 | 3264 | 0 | 0 |
|
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A
| 0 | 0 | 111801211 | 2661 | 0 | 0 |
|
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A
| 0 | 0 | 111801211 | 3117 | 0 | 0 |
|
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A
| 0 | 0 | 70281161 | 2600 | 0 | 0 |
|
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A
| 0 | 0 | 70281161 | 2600 | 0 | 0 |
|
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A
| 0 | 0 | 70281161 | 1549 | 0 | 0 |
|
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A
| 0 | 0 | 70281161 | 1549 | 0 | 0 |
|
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A
| 0 | 0 | 70281161 | 3201 | 0 | 0 |
|
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A
| 0 | 0 | 70281161 | 3201 | 0 | 0 |
|
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A
| 0 | 0 | 240016220 | 2118 | 0 | 0 |
|
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A
| 0 | 0 | 240016220 | 1145 | 0 | 0 |
|
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A
| 0 | 0 | 111801211 | 1863 | 0 | 0 |
|
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A
| 0 | 0 | 111801211 | 3391 | 0 | 0 |
|
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A
| 0 | 0 | 55900434 | 1736 | 0 | 0 |
|
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A
| 0 | 0 | 55900434 | 3264 | 0 | 0 |
|
tb.dut.clkmgr_io_peri_sva_if.GateClose_A
| 0 | 0 | 225074271 | 1818 | 0 | 0 |
|
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A
| 0 | 0 | 225074271 | 3348 | 0 | 0 |
|
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A
| 0 | 0 | 240016220 | 2021 | 0 | 0 |
|
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A
| 0 | 0 | 240016220 | 1103 | 0 | 0 |
|
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A
| 0 | 0 | 70281161 | 6333 | 0 | 0 |
|
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A
| 0 | 0 | 70281161 | 8660 | 0 | 0 |
|
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A
| 0 | 0 | 70281161 | 13060 | 0 | 0 |
|
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A
| 0 | 0 | 70281161 | 6172 | 0 | 0 |
|
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A
| 0 | 0 | 70281161 | 10009526 | 0 | 56 |
|
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A
| 0 | 0 | 70281161 | 8635 | 0 | 0 |
|
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A
| 0 | 0 | 240016220 | 2022 | 0 | 0 |
|
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A
| 0 | 0 | 240016220 | 1110 | 0 | 0 |
|
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A
| 0 | 0 | 70281161 | 150 | 0 | 0 |
|
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A
| 0 | 0 | 70281161 | 150 | 0 | 0 |
|
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A
| 0 | 0 | 70281161 | 143 | 0 | 0 |
|
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A
| 0 | 0 | 70281161 | 143 | 0 | 0 |
|
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A
| 0 | 0 | 70281161 | 141 | 0 | 0 |
|
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A
| 0 | 0 | 70281161 | 141 | 0 | 0 |
|
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A
| 0 | 0 | 70281161 | 68034347 | 0 | 0 |
|
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A
| 0 | 0 | 70281161 | 74928 | 0 | 0 |
|
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A
| 0 | 0 | 70281161 | 67982101 | 0 | 2316 |
|
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A
| 0 | 0 | 70281161 | 123030 | 0 | 0 |
|
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A
| 0 | 0 | 70281161 | 68040756 | 0 | 0 |
|
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A
| 0 | 0 | 70281161 | 68519 | 0 | 0 |
|
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A
| 0 | 0 | 115245911 | 1820 | 0 | 0 |
|
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A
| 0 | 0 | 115245911 | 3351 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_A
| 0 | 0 | 71256824 | 7495709 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_AKnownEnable
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.tlul_assert_device.aReadyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_A
| 0 | 0 | 71256824 | 7733085 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_AKnownEnable
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.tlul_assert_device.dReadyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 71257431 | 6140543 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 71256824 | 973454 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 71257431 | 213645 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 71257431 | 140934 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 71256824 | 1077542 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 71257431 | 7495709 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 71257431 | 7733085 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 71257431 | 7495709 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 71257431 | 7733085 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 71257431 | 7733085 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 71257431 | 7733085 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 71256824 | 580457 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 71256824 | 439043 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_calib_rdy_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A
| 0 | 0 | 240015796 | 236194854 | 0 | 2316 |
|
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A
| 0 | 0 | 240015796 | 18713 | 0 | 0 |
|
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A
| 0 | 0 | 240015796 | 236194854 | 0 | 2316 |
|
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A
| 0 | 0 | 240015796 | 18963 | 0 | 0 |
|
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A
| 0 | 0 | 240015796 | 236194854 | 0 | 2316 |
|
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A
| 0 | 0 | 240015796 | 18683 | 0 | 0 |
|
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A
| 0 | 0 | 240015796 | 236194854 | 0 | 2316 |
|
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A
| 0 | 0 | 240015796 | 18822 | 0 | 0 |
|
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A
| 0 | 0 | 70281161 | 12309 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A
| 0 | 0 | 70281161 | 10741 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 70281161 | 1468 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq
| 0 | 0 | 111800817 | 1468 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq
| 0 | 0 | 111800817 | 1580051 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A
| 0 | 0 | 111800817 | 49328 | 0 | 0 |
|
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M
| 0 | 0 | 7112361 | 48688 | 0 | 0 |
|
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 111800817 | 111800817 | 0 | 0 |
|
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 111800817 | 111800817 | 0 | 0 |
|
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 70281161 | 1467 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq
| 0 | 0 | 55900042 | 1467 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq
| 0 | 0 | 55900042 | 1508551 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A
| 0 | 0 | 55900042 | 48865 | 0 | 0 |
|
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M
| 0 | 0 | 7112361 | 48232 | 0 | 0 |
|
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 55900042 | 55900042 | 0 | 0 |
|
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 55900042 | 55900042 | 0 | 0 |
|
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 70281161 | 1605 | 0 | 0 |
|
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq
| 0 | 0 | 225073845 | 1605 | 0 | 0 |
|
tb.dut.u_io_meas.u_meas.RefCntVal_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq
| 0 | 0 | 225073845 | 1580150 | 0 | 0 |
|
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A
| 0 | 0 | 225073845 | 49519 | 0 | 0 |
|
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M
| 0 | 0 | 7112361 | 48872 | 0 | 0 |
|
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 225073845 | 223254784 | 0 | 0 |
|
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 225073845 | 223254784 | 0 | 0 |
|
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_io_step_down_req_sync.OutputsKnown_A
| 0 | 0 | 225073845 | 221428594 | 0 | 0 |
|
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A
| 0 | 0 | 225073845 | 221422377 | 0 | 2316 |
|
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A
| 0 | 0 | 225073845 | 17636 | 0 | 0 |
|
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 70281161 | 1522 | 0 | 0 |
|
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq
| 0 | 0 | 240015796 | 1522 | 0 | 0 |
|
tb.dut.u_main_meas.u_meas.RefCntVal_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq
| 0 | 0 | 240015796 | 1582279 | 0 | 0 |
|
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A
| 0 | 0 | 240015796 | 59192 | 0 | 0 |
|
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M
| 0 | 0 | 7137656 | 58809 | 0 | 0 |
|
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 240015796 | 238115924 | 0 | 0 |
|
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 240015796 | 238115924 | 0 | 0 |
|
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.DivEven_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 111627889 | 111627117 | 0 | 0 |
|
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 225073845 | 225073073 | 0 | 0 |
|
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 111800817 | 111800045 | 0 | 0 |
|
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 225073845 | 225073073 | 0 | 0 |
|
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.DivEven_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 55900042 | 55899270 | 0 | 0 |
|
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 225073845 | 225073073 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A
| 0 | 0 | 111800817 | 110887301 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A
| 0 | 0 | 111800817 | 110887301 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A
| 0 | 0 | 55900042 | 55443346 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A
| 0 | 0 | 55900042 | 55443346 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A
| 0 | 0 | 55900042 | 55443346 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A
| 0 | 0 | 55900042 | 55443346 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A
| 0 | 0 | 225073845 | 221428594 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A
| 0 | 0 | 225073845 | 221428594 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A
| 0 | 0 | 240015796 | 236201146 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A
| 0 | 0 | 115245515 | 113414179 | 0 | 0 |
|
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A
| 0 | 0 | 115245515 | 113414179 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 71256824 | 428767 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 71256824 | 428767 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 71256824 | 120817 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 69961 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A
| 0 | 0 | 113276091 | 112315055 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 113276091 | 659 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 71256824 | 14476 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 113276091 | 13813 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 113276091 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 100689 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A
| 0 | 0 | 113276091 | 112315055 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 19457 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 71256824 | 19456 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 113276091 | 19461 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 113276091 | 19459 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 19488 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A
| 0 | 0 | 113276091 | 112315055 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 36 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 113276091 | 36 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A
| 0 | 0 | 113276091 | 112315055 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 35 | 0 | 0 |
|
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 113276091 | 35 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 110905 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A
| 0 | 0 | 56637693 | 56157267 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 56637693 | 659 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 71256824 | 14476 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 56637693 | 13772 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 56637693 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 161794 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A
| 0 | 0 | 56637693 | 56157267 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 19547 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 71256824 | 19543 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 56637693 | 19554 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 56637693 | 19548 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 19589 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A
| 0 | 0 | 56637693 | 56157267 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 41 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 56637693 | 41 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A
| 0 | 0 | 56637693 | 56157267 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 34 | 0 | 0 |
|
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 56637693 | 34 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 48513 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A
| 0 | 0 | 228117875 | 224284124 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 228117875 | 659 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 71256824 | 14476 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 228117875 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 228117875 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 70421 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A
| 0 | 0 | 228117875 | 224284124 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 19561 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 71256824 | 19558 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 228117875 | 19577 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 228117875 | 19569 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 19592 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A
| 0 | 0 | 228117875 | 224284124 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 43 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 228117875 | 43 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A
| 0 | 0 | 228117875 | 224284124 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 45 | 0 | 0 |
|
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 228117875 | 45 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 47478 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A
| 0 | 0 | 243186787 | 239175812 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 243186787 | 659 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 71256824 | 14476 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 243186787 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 243186787 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 68906 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A
| 0 | 0 | 243186787 | 239175812 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 19556 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 71256824 | 19556 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 243186787 | 19567 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 243186787 | 19564 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 19577 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A
| 0 | 0 | 243186787 | 239175812 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 26 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 243186787 | 26 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A
| 0 | 0 | 243186787 | 239175812 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 32 | 0 | 0 |
|
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 243186787 | 32 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 67445 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A
| 0 | 0 | 116767562 | 114842037 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 13307 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 116767562 | 659 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 71256824 | 13966 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 116767562 | 13175 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 116767562 | 13353 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 13817 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A
| 0 | 0 | 71256824 | 99963 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A
| 0 | 0 | 116767562 | 114842037 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A
| 0 | 0 | 71256824 | 19153 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A
| 0 | 0 | 71256824 | 68975283 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 71256824 | 19130 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 116767562 | 19343 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 116767562 | 19319 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 71256824 | 19499 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A
| 0 | 0 | 116767562 | 114842037 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 40 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 116767562 | 40 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A
| 0 | 0 | 977 | 977 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A
| 0 | 0 | 116767562 | 114842037 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A
| 0 | 0 | 71256824 | 37 | 0 | 0 |
|
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M
| 0 | 0 | 116767562 | 37 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 71256824 | 307950 | 0 | 0 |
|
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A
| 0 | 0 | 70281161 | 68111347 | 0 | 0 |
|
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A
| 0 | 0 | 70281161 | 68104924 | 0 | 2316 |
|
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 70281161 | 1427 | 0 | 0 |
|
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq
| 0 | 0 | 115245515 | 1427 | 0 | 0 |
|
tb.dut.u_usb_meas.u_meas.RefCntVal_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq
| 0 | 0 | 115245515 | 1582279 | 0 | 0 |
|
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A
| 0 | 0 | 115245515 | 58697 | 0 | 0 |
|
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M
| 0 | 0 | 7140714 | 58697 | 0 | 0 |
|
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 772 | 772 | 0 | 0 |
|
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 115245515 | 114333732 | 0 | 0 |
|
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 115245515 | 114333732 | 0 | 0 |
|