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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 977
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T801 /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3038749350 Aug 02 07:24:04 PM PDT 24 Aug 02 07:24:05 PM PDT 24 46987353 ps
T802 /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1984648028 Aug 02 07:23:28 PM PDT 24 Aug 02 07:23:29 PM PDT 24 100473591 ps
T803 /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.1656521581 Aug 02 07:23:01 PM PDT 24 Aug 02 07:23:02 PM PDT 24 15026306 ps
T804 /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3065418835 Aug 02 07:24:03 PM PDT 24 Aug 02 07:24:04 PM PDT 24 13668757 ps
T805 /workspace/coverage/default/16.clkmgr_stress_all.535466720 Aug 02 07:23:28 PM PDT 24 Aug 02 07:23:44 PM PDT 24 3585236734 ps
T806 /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.3314691224 Aug 02 07:24:13 PM PDT 24 Aug 02 07:24:14 PM PDT 24 42824598 ps
T807 /workspace/coverage/default/27.clkmgr_alert_test.3257604596 Aug 02 07:24:04 PM PDT 24 Aug 02 07:24:04 PM PDT 24 16593380 ps
T808 /workspace/coverage/default/35.clkmgr_alert_test.1929354784 Aug 02 07:24:39 PM PDT 24 Aug 02 07:24:40 PM PDT 24 77020310 ps
T809 /workspace/coverage/default/33.clkmgr_smoke.3782687036 Aug 02 07:24:28 PM PDT 24 Aug 02 07:24:29 PM PDT 24 18757043 ps
T810 /workspace/coverage/default/8.clkmgr_trans.2796212301 Aug 02 07:22:52 PM PDT 24 Aug 02 07:22:55 PM PDT 24 414497194 ps
T811 /workspace/coverage/default/16.clkmgr_div_intersig_mubi.874096931 Aug 02 07:23:17 PM PDT 24 Aug 02 07:23:18 PM PDT 24 84163164 ps
T812 /workspace/coverage/default/47.clkmgr_smoke.4060947736 Aug 02 07:25:24 PM PDT 24 Aug 02 07:25:25 PM PDT 24 22815933 ps
T813 /workspace/coverage/default/14.clkmgr_div_intersig_mubi.3898982092 Aug 02 07:23:14 PM PDT 24 Aug 02 07:23:15 PM PDT 24 59994149 ps
T814 /workspace/coverage/default/39.clkmgr_peri.317712638 Aug 02 07:24:49 PM PDT 24 Aug 02 07:24:50 PM PDT 24 17164032 ps
T815 /workspace/coverage/default/39.clkmgr_frequency_timeout.3920207159 Aug 02 07:24:52 PM PDT 24 Aug 02 07:24:58 PM PDT 24 741649675 ps
T816 /workspace/coverage/default/25.clkmgr_peri.3506092992 Aug 02 07:24:00 PM PDT 24 Aug 02 07:24:02 PM PDT 24 24726630 ps
T817 /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1039437711 Aug 02 07:24:55 PM PDT 24 Aug 02 07:24:56 PM PDT 24 30492253 ps
T818 /workspace/coverage/default/34.clkmgr_alert_test.3881020010 Aug 02 07:24:38 PM PDT 24 Aug 02 07:24:39 PM PDT 24 38126699 ps
T819 /workspace/coverage/default/42.clkmgr_frequency.3794535139 Aug 02 07:24:59 PM PDT 24 Aug 02 07:25:01 PM PDT 24 202067058 ps
T820 /workspace/coverage/default/16.clkmgr_frequency_timeout.777871504 Aug 02 07:23:07 PM PDT 24 Aug 02 07:23:16 PM PDT 24 1951689153 ps
T821 /workspace/coverage/default/48.clkmgr_smoke.888725782 Aug 02 07:25:21 PM PDT 24 Aug 02 07:25:22 PM PDT 24 20633976 ps
T822 /workspace/coverage/default/5.clkmgr_frequency_timeout.3040511770 Aug 02 07:22:50 PM PDT 24 Aug 02 07:22:59 PM PDT 24 2410320340 ps
T823 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.574397440 Aug 02 07:20:04 PM PDT 24 Aug 02 07:20:07 PM PDT 24 239864549 ps
T105 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1142401780 Aug 02 07:21:02 PM PDT 24 Aug 02 07:21:04 PM PDT 24 47853156 ps
T824 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1689304391 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:54 PM PDT 24 16821634 ps
T129 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.533764804 Aug 02 07:20:05 PM PDT 24 Aug 02 07:20:06 PM PDT 24 68302632 ps
T130 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2075037304 Aug 02 07:20:02 PM PDT 24 Aug 02 07:20:03 PM PDT 24 37716619 ps
T825 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.18077929 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:53 PM PDT 24 15011666 ps
T826 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1452722768 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:03 PM PDT 24 143482441 ps
T106 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3664288429 Aug 02 07:20:05 PM PDT 24 Aug 02 07:20:06 PM PDT 24 116426186 ps
T827 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.183059131 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:01 PM PDT 24 16586814 ps
T107 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2119245677 Aug 02 07:20:57 PM PDT 24 Aug 02 07:20:58 PM PDT 24 45376911 ps
T108 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.4038156381 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:57 PM PDT 24 152775364 ps
T124 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2829007701 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:57 PM PDT 24 127448629 ps
T166 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.509347830 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:01 PM PDT 24 61860554 ps
T74 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3140127851 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:56 PM PDT 24 71398848 ps
T167 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.219184278 Aug 02 07:19:58 PM PDT 24 Aug 02 07:20:08 PM PDT 24 2036920595 ps
T109 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1049050333 Aug 02 07:19:58 PM PDT 24 Aug 02 07:20:00 PM PDT 24 49620576 ps
T110 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3840600930 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:56 PM PDT 24 186441584 ps
T828 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2830261428 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:54 PM PDT 24 49920651 ps
T829 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3461507543 Aug 02 07:21:02 PM PDT 24 Aug 02 07:21:02 PM PDT 24 12627446 ps
T830 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.712200582 Aug 02 07:20:22 PM PDT 24 Aug 02 07:20:26 PM PDT 24 131098038 ps
T77 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1151394970 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:02 PM PDT 24 67174968 ps
T111 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2817816703 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:58 PM PDT 24 197907285 ps
T112 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3298473526 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:55 PM PDT 24 195602927 ps
T831 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.356991462 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 25141490 ps
T113 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.2783047955 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:55 PM PDT 24 23919605 ps
T832 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.340334445 Aug 02 07:21:11 PM PDT 24 Aug 02 07:21:12 PM PDT 24 97762931 ps
T833 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.882296244 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:00 PM PDT 24 74868343 ps
T75 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.58948868 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:56 PM PDT 24 121473744 ps
T125 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.943039754 Aug 02 07:19:56 PM PDT 24 Aug 02 07:19:59 PM PDT 24 346041444 ps
T834 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.667051664 Aug 02 07:21:02 PM PDT 24 Aug 02 07:21:03 PM PDT 24 22856898 ps
T82 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3981766885 Aug 02 07:20:50 PM PDT 24 Aug 02 07:20:52 PM PDT 24 263799591 ps
T835 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.437808976 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:56 PM PDT 24 122984631 ps
T836 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1278008284 Aug 02 07:21:03 PM PDT 24 Aug 02 07:21:03 PM PDT 24 11503180 ps
T837 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3838220916 Aug 02 07:20:05 PM PDT 24 Aug 02 07:20:09 PM PDT 24 287590135 ps
T838 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1033150202 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:23 PM PDT 24 6597125533 ps
T839 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1115019385 Aug 02 07:21:03 PM PDT 24 Aug 02 07:21:04 PM PDT 24 30654705 ps
T840 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2133356938 Aug 02 07:20:04 PM PDT 24 Aug 02 07:20:06 PM PDT 24 55403258 ps
T841 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.508370065 Aug 02 07:20:05 PM PDT 24 Aug 02 07:20:07 PM PDT 24 261345248 ps
T842 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.42436342 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:54 PM PDT 24 102327632 ps
T843 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3472445867 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 25190734 ps
T844 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1123533707 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:02 PM PDT 24 21677992 ps
T845 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.427975428 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:55 PM PDT 24 31464775 ps
T126 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1608773343 Aug 02 07:20:21 PM PDT 24 Aug 02 07:20:24 PM PDT 24 127960321 ps
T76 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2668789080 Aug 02 07:21:02 PM PDT 24 Aug 02 07:21:05 PM PDT 24 150251693 ps
T846 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3046504861 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:57 PM PDT 24 512177515 ps
T81 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.4220804729 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:54 PM PDT 24 74886433 ps
T847 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3045248380 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 28495089 ps
T848 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.658080219 Aug 02 07:20:22 PM PDT 24 Aug 02 07:20:23 PM PDT 24 26375197 ps
T849 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.823484563 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:02 PM PDT 24 22610201 ps
T79 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3710089030 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:02 PM PDT 24 100345335 ps
T850 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3570829107 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:54 PM PDT 24 32843460 ps
T851 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2039048367 Aug 02 07:20:10 PM PDT 24 Aug 02 07:20:11 PM PDT 24 49543016 ps
T131 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1184741248 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:02 PM PDT 24 93873547 ps
T852 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.420375292 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:56 PM PDT 24 105130617 ps
T78 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.53665034 Aug 02 07:21:02 PM PDT 24 Aug 02 07:21:04 PM PDT 24 164327953 ps
T853 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3548112761 Aug 02 07:21:10 PM PDT 24 Aug 02 07:21:11 PM PDT 24 22509170 ps
T80 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1255774845 Aug 02 07:20:59 PM PDT 24 Aug 02 07:21:01 PM PDT 24 131973186 ps
T149 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2858866272 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:58 PM PDT 24 270204729 ps
T854 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3804457462 Aug 02 07:20:57 PM PDT 24 Aug 02 07:20:58 PM PDT 24 39163068 ps
T855 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3410686020 Aug 02 07:20:58 PM PDT 24 Aug 02 07:20:59 PM PDT 24 39939548 ps
T856 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2205891072 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 172705038 ps
T857 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1995040832 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:01 PM PDT 24 24831883 ps
T132 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1680573835 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:58 PM PDT 24 490312720 ps
T858 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.4232610172 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:57 PM PDT 24 732501106 ps
T859 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2598066190 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:05 PM PDT 24 368533150 ps
T83 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1469732374 Aug 02 07:20:58 PM PDT 24 Aug 02 07:21:00 PM PDT 24 109990148 ps
T151 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2364752278 Aug 02 07:20:03 PM PDT 24 Aug 02 07:20:05 PM PDT 24 305684193 ps
T137 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.678953712 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:58 PM PDT 24 351438261 ps
T860 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1648174354 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:56 PM PDT 24 236353953 ps
T152 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2304573917 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:57 PM PDT 24 101641060 ps
T861 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2338345818 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:56 PM PDT 24 55682752 ps
T143 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.4102348108 Aug 02 07:20:04 PM PDT 24 Aug 02 07:20:07 PM PDT 24 152670183 ps
T862 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.3158727634 Aug 02 07:21:04 PM PDT 24 Aug 02 07:21:05 PM PDT 24 16608506 ps
T144 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3702388492 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:57 PM PDT 24 108314493 ps
T863 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1313506723 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:02 PM PDT 24 161597268 ps
T864 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2864400557 Aug 02 07:21:10 PM PDT 24 Aug 02 07:21:11 PM PDT 24 21216006 ps
T865 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2344261790 Aug 02 07:20:57 PM PDT 24 Aug 02 07:20:58 PM PDT 24 29733629 ps
T176 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2892300925 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:54 PM PDT 24 122933770 ps
T866 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.744983245 Aug 02 07:19:58 PM PDT 24 Aug 02 07:19:59 PM PDT 24 14293066 ps
T867 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.4016174295 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:01 PM PDT 24 17668477 ps
T868 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.483158854 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:56 PM PDT 24 36490033 ps
T145 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1750458658 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:55 PM PDT 24 89662033 ps
T134 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1856734633 Aug 02 07:21:01 PM PDT 24 Aug 02 07:21:04 PM PDT 24 113818208 ps
T869 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.547942111 Aug 02 07:19:57 PM PDT 24 Aug 02 07:19:59 PM PDT 24 73880939 ps
T870 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.801839945 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:00 PM PDT 24 142322380 ps
T871 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3580783207 Aug 02 07:21:15 PM PDT 24 Aug 02 07:21:16 PM PDT 24 51101461 ps
T872 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1462436887 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:03 PM PDT 24 220594639 ps
T873 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3292937954 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:57 PM PDT 24 201091995 ps
T154 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2422362021 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:57 PM PDT 24 98660712 ps
T874 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1186568663 Aug 02 07:20:58 PM PDT 24 Aug 02 07:20:59 PM PDT 24 19846114 ps
T875 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.4282476489 Aug 02 07:19:56 PM PDT 24 Aug 02 07:19:57 PM PDT 24 44330441 ps
T876 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.4167332786 Aug 02 07:20:05 PM PDT 24 Aug 02 07:20:06 PM PDT 24 19897449 ps
T877 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2621372226 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:56 PM PDT 24 67705105 ps
T878 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4130942362 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:01 PM PDT 24 17699989 ps
T146 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1707953779 Aug 02 07:20:12 PM PDT 24 Aug 02 07:20:14 PM PDT 24 260444883 ps
T879 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3659099560 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:55 PM PDT 24 24657598 ps
T147 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.4252575964 Aug 02 07:20:57 PM PDT 24 Aug 02 07:20:59 PM PDT 24 156644864 ps
T880 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2962631868 Aug 02 07:20:38 PM PDT 24 Aug 02 07:20:39 PM PDT 24 127727312 ps
T881 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2976527536 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:57 PM PDT 24 28500864 ps
T882 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2397303840 Aug 02 07:20:58 PM PDT 24 Aug 02 07:20:59 PM PDT 24 80471843 ps
T150 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1960194064 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:55 PM PDT 24 269819291 ps
T883 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.463475890 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:57 PM PDT 24 27554355 ps
T884 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1037237805 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:05 PM PDT 24 590039240 ps
T885 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.57687878 Aug 02 07:20:02 PM PDT 24 Aug 02 07:20:03 PM PDT 24 18624833 ps
T886 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.4039767750 Aug 02 07:20:40 PM PDT 24 Aug 02 07:20:41 PM PDT 24 50197677 ps
T148 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.675950910 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:57 PM PDT 24 241199524 ps
T887 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2690216794 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:52 PM PDT 24 21921699 ps
T888 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3451701390 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:54 PM PDT 24 23666539 ps
T889 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.612650987 Aug 02 07:20:58 PM PDT 24 Aug 02 07:21:00 PM PDT 24 83609456 ps
T890 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3235133976 Aug 02 07:21:01 PM PDT 24 Aug 02 07:21:03 PM PDT 24 30184497 ps
T891 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1776726954 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 39463569 ps
T892 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3433955302 Aug 02 07:19:58 PM PDT 24 Aug 02 07:19:59 PM PDT 24 141213124 ps
T893 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.318117847 Aug 02 07:20:57 PM PDT 24 Aug 02 07:21:00 PM PDT 24 191449507 ps
T894 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1539846297 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:54 PM PDT 24 61345644 ps
T135 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1804420831 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:55 PM PDT 24 114532845 ps
T895 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1470916781 Aug 02 07:21:12 PM PDT 24 Aug 02 07:21:13 PM PDT 24 25298681 ps
T896 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1043927500 Aug 02 07:19:57 PM PDT 24 Aug 02 07:19:58 PM PDT 24 21702009 ps
T897 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.1391708124 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:54 PM PDT 24 17356387 ps
T898 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1471120603 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:01 PM PDT 24 39235366 ps
T899 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3065423563 Aug 02 07:20:04 PM PDT 24 Aug 02 07:20:07 PM PDT 24 202147222 ps
T900 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3915462563 Aug 02 07:20:56 PM PDT 24 Aug 02 07:21:00 PM PDT 24 342665419 ps
T133 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.295124991 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:02 PM PDT 24 143496231 ps
T901 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2359299810 Aug 02 07:20:12 PM PDT 24 Aug 02 07:20:14 PM PDT 24 57746805 ps
T902 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.475611076 Aug 02 07:20:57 PM PDT 24 Aug 02 07:20:58 PM PDT 24 13762099 ps
T903 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1635109876 Aug 02 07:21:04 PM PDT 24 Aug 02 07:21:05 PM PDT 24 43793179 ps
T904 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3172015920 Aug 02 07:21:12 PM PDT 24 Aug 02 07:21:13 PM PDT 24 11836730 ps
T905 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1668733044 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 94120111 ps
T906 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.742595661 Aug 02 07:20:51 PM PDT 24 Aug 02 07:20:52 PM PDT 24 15566921 ps
T907 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2385510709 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:56 PM PDT 24 179253723 ps
T908 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.4234950268 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:54 PM PDT 24 133983493 ps
T909 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1545224753 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:58 PM PDT 24 153010490 ps
T910 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2349009182 Aug 02 07:20:58 PM PDT 24 Aug 02 07:21:01 PM PDT 24 62465708 ps
T911 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2950128795 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:00 PM PDT 24 33047750 ps
T912 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2828741072 Aug 02 07:20:58 PM PDT 24 Aug 02 07:20:59 PM PDT 24 30244794 ps
T913 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.83346663 Aug 02 07:21:08 PM PDT 24 Aug 02 07:21:09 PM PDT 24 12685333 ps
T914 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3915657186 Aug 02 07:20:59 PM PDT 24 Aug 02 07:21:01 PM PDT 24 158710512 ps
T915 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.256145696 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:56 PM PDT 24 28472327 ps
T916 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3513224742 Aug 02 07:19:57 PM PDT 24 Aug 02 07:20:05 PM PDT 24 729607093 ps
T917 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.4021613794 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:55 PM PDT 24 67797923 ps
T918 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2506654437 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:02 PM PDT 24 30434247 ps
T919 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1921734980 Aug 02 07:20:57 PM PDT 24 Aug 02 07:20:58 PM PDT 24 41004980 ps
T920 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3510279686 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:57 PM PDT 24 287723710 ps
T921 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3461560533 Aug 02 07:20:58 PM PDT 24 Aug 02 07:20:59 PM PDT 24 79645470 ps
T922 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3798592717 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:55 PM PDT 24 52209979 ps
T923 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.7874649 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:55 PM PDT 24 16238455 ps
T924 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1161877425 Aug 02 07:20:56 PM PDT 24 Aug 02 07:21:00 PM PDT 24 545737234 ps
T925 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2979634032 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:55 PM PDT 24 100510536 ps
T138 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1066406764 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:59 PM PDT 24 100401704 ps
T926 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2779267031 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:56 PM PDT 24 25194054 ps
T927 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.792757682 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:01 PM PDT 24 91837100 ps
T928 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3979401325 Aug 02 07:20:58 PM PDT 24 Aug 02 07:20:59 PM PDT 24 15224861 ps
T929 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3744419168 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:00 PM PDT 24 22253641 ps
T930 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1298833085 Aug 02 07:20:58 PM PDT 24 Aug 02 07:20:59 PM PDT 24 45046281 ps
T931 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.4027310157 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:03 PM PDT 24 117672719 ps
T932 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3333778468 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:56 PM PDT 24 31726549 ps
T933 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4121779314 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:04 PM PDT 24 278995161 ps
T934 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3048757361 Aug 02 07:21:10 PM PDT 24 Aug 02 07:21:11 PM PDT 24 13269477 ps
T935 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1030541080 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 25688618 ps
T178 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.2136483779 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:03 PM PDT 24 71763025 ps
T936 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1490395467 Aug 02 07:20:04 PM PDT 24 Aug 02 07:20:06 PM PDT 24 59771412 ps
T937 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.974365940 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:02 PM PDT 24 55385619 ps
T938 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1460112893 Aug 02 07:21:07 PM PDT 24 Aug 02 07:21:08 PM PDT 24 11943741 ps
T939 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3026089947 Aug 02 07:19:57 PM PDT 24 Aug 02 07:19:59 PM PDT 24 120468026 ps
T940 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.947876230 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 57073176 ps
T941 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1880637695 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:03 PM PDT 24 153512569 ps
T942 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2415502548 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 21035690 ps
T136 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2373083155 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:54 PM PDT 24 207224137 ps
T943 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3473325128 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:55 PM PDT 24 217536066 ps
T944 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3348183937 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:55 PM PDT 24 37387206 ps
T945 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.1521543446 Aug 02 07:21:02 PM PDT 24 Aug 02 07:21:04 PM PDT 24 200525120 ps
T946 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3092251293 Aug 02 07:21:05 PM PDT 24 Aug 02 07:21:05 PM PDT 24 32289412 ps
T947 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3358118833 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:57 PM PDT 24 36708005 ps
T948 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.981593425 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:58 PM PDT 24 73271706 ps
T949 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3601415322 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:58 PM PDT 24 538214421 ps
T950 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3111639662 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:02 PM PDT 24 99808695 ps
T951 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.222694895 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:01 PM PDT 24 17209720 ps
T952 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.636015163 Aug 02 07:21:07 PM PDT 24 Aug 02 07:21:08 PM PDT 24 17314155 ps
T953 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2949532381 Aug 02 07:20:57 PM PDT 24 Aug 02 07:20:57 PM PDT 24 13796710 ps
T954 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.205277694 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:56 PM PDT 24 63755036 ps
T955 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.585558476 Aug 02 07:19:57 PM PDT 24 Aug 02 07:19:58 PM PDT 24 39950279 ps
T956 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1860964085 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:02 PM PDT 24 116143922 ps
T957 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1802227 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:57 PM PDT 24 410215201 ps
T958 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1496190328 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:57 PM PDT 24 64832210 ps
T959 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.496301899 Aug 02 07:21:11 PM PDT 24 Aug 02 07:21:12 PM PDT 24 26880855 ps
T960 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2838688074 Aug 02 07:20:40 PM PDT 24 Aug 02 07:20:42 PM PDT 24 34769277 ps
T961 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2688883952 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:57 PM PDT 24 12376931 ps
T153 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.782695548 Aug 02 07:20:53 PM PDT 24 Aug 02 07:20:56 PM PDT 24 168471479 ps
T962 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3979877805 Aug 02 07:20:52 PM PDT 24 Aug 02 07:20:53 PM PDT 24 29485272 ps
T963 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1624830559 Aug 02 07:21:07 PM PDT 24 Aug 02 07:21:11 PM PDT 24 423828651 ps
T177 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1815417885 Aug 02 07:21:00 PM PDT 24 Aug 02 07:21:03 PM PDT 24 229431097 ps
T964 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1233573308 Aug 02 07:20:13 PM PDT 24 Aug 02 07:20:14 PM PDT 24 28127561 ps
T965 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1634856835 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:57 PM PDT 24 16602914 ps
T966 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3657446936 Aug 02 07:20:00 PM PDT 24 Aug 02 07:20:01 PM PDT 24 73980638 ps
T967 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1077177299 Aug 02 07:20:59 PM PDT 24 Aug 02 07:21:01 PM PDT 24 139378827 ps
T968 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.767317197 Aug 02 07:20:54 PM PDT 24 Aug 02 07:20:58 PM PDT 24 376362658 ps
T969 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2096973058 Aug 02 07:20:56 PM PDT 24 Aug 02 07:20:58 PM PDT 24 60129076 ps
T970 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3456260353 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:02 PM PDT 24 60954620 ps
T971 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3196106903 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:56 PM PDT 24 11757035 ps
T972 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1691761752 Aug 02 07:19:59 PM PDT 24 Aug 02 07:20:01 PM PDT 24 172798460 ps
T973 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3876126453 Aug 02 07:20:01 PM PDT 24 Aug 02 07:20:03 PM PDT 24 110152390 ps
T974 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.215915682 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:57 PM PDT 24 121948623 ps
T127 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2543496074 Aug 02 07:19:58 PM PDT 24 Aug 02 07:20:00 PM PDT 24 56149116 ps
T975 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2155271368 Aug 02 07:20:05 PM PDT 24 Aug 02 07:20:06 PM PDT 24 41618667 ps
T976 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1120095867 Aug 02 07:20:55 PM PDT 24 Aug 02 07:20:58 PM PDT 24 166602579 ps
T977 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1829169543 Aug 02 07:20:04 PM PDT 24 Aug 02 07:20:05 PM PDT 24 98263522 ps

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.1233818023
Short name T8
Test name
Test status
Simulation time 2508395873 ps
CPU time 8.47 seconds
Started Aug 02 07:25:01 PM PDT 24
Finished Aug 02 07:25:09 PM PDT 24
Peak memory 201528 kb
Host smart-715c8707-17e5-49ee-a3ec-f6c5dd3caf54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233818023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.1233818023
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.1368364898
Short name T14
Test name
Test status
Simulation time 96163087895 ps
CPU time 567.14 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:33:24 PM PDT 24
Peak memory 217876 kb
Host smart-2c0f9ad3-f3d1-4d74-a8c4-9d2f7657dbb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1368364898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.1368364898
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.1108819864
Short name T50
Test name
Test status
Simulation time 36578639 ps
CPU time 0.92 seconds
Started Aug 02 07:24:54 PM PDT 24
Finished Aug 02 07:24:55 PM PDT 24
Peak memory 201160 kb
Host smart-7f6a943b-a874-4485-bc5d-685fc869c164
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108819864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.1108819864
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.2343923271
Short name T46
Test name
Test status
Simulation time 47389007 ps
CPU time 0.87 seconds
Started Aug 02 07:24:51 PM PDT 24
Finished Aug 02 07:24:52 PM PDT 24
Peak memory 201148 kb
Host smart-44730db5-224d-4bef-83aa-b8758de88879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343923271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2343923271
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.53665034
Short name T78
Test name
Test status
Simulation time 164327953 ps
CPU time 1.97 seconds
Started Aug 02 07:21:02 PM PDT 24
Finished Aug 02 07:21:04 PM PDT 24
Peak memory 200808 kb
Host smart-319f647c-4ba7-4087-9dba-7e0b128be453
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53665034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.clkmgr_shadow_reg_errors.53665034
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.556042900
Short name T5
Test name
Test status
Simulation time 1211140868 ps
CPU time 5.47 seconds
Started Aug 02 07:22:14 PM PDT 24
Finished Aug 02 07:22:20 PM PDT 24
Peak memory 201408 kb
Host smart-80538577-5abc-49c6-bcae-3148d7e34a86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556042900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.556042900
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.2892662302
Short name T65
Test name
Test status
Simulation time 353169859 ps
CPU time 2.5 seconds
Started Aug 02 07:22:12 PM PDT 24
Finished Aug 02 07:22:15 PM PDT 24
Peak memory 216596 kb
Host smart-d14f657a-a87b-4a66-80be-475aad79efae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892662302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.2892662302
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.4142868937
Short name T168
Test name
Test status
Simulation time 17080500 ps
CPU time 0.77 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 200332 kb
Host smart-a545ffb1-556f-4297-810c-e4a2dbd542fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142868937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.4142868937
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.2295604346
Short name T182
Test name
Test status
Simulation time 127576679 ps
CPU time 1.21 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201040 kb
Host smart-7606376c-983d-4cfb-84b7-e65dc44c8ea0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295604346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.2295604346
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1750458658
Short name T145
Test name
Test status
Simulation time 89662033 ps
CPU time 1.6 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200940 kb
Host smart-1d62629c-a177-4fde-86cf-3abe987a1ef0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750458658 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.1750458658
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.1668740904
Short name T18
Test name
Test status
Simulation time 6111409227 ps
CPU time 45.52 seconds
Started Aug 02 07:24:51 PM PDT 24
Finished Aug 02 07:25:37 PM PDT 24
Peak memory 201480 kb
Host smart-864e84fd-5834-4d32-859f-1fe320bb174e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668740904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.1668740904
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1608773343
Short name T126
Test name
Test status
Simulation time 127960321 ps
CPU time 2.78 seconds
Started Aug 02 07:20:21 PM PDT 24
Finished Aug 02 07:20:24 PM PDT 24
Peak memory 200632 kb
Host smart-546eabd2-0917-413b-b4e3-dab2433d27ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608773343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.1608773343
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.2761920159
Short name T10
Test name
Test status
Simulation time 52149891 ps
CPU time 1.04 seconds
Started Aug 02 07:23:45 PM PDT 24
Finished Aug 02 07:23:46 PM PDT 24
Peak memory 201096 kb
Host smart-a645aa9a-ee69-4688-84b6-dac01544b93d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761920159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2761920159
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.1490040755
Short name T54
Test name
Test status
Simulation time 170768558 ps
CPU time 2.18 seconds
Started Aug 02 07:22:00 PM PDT 24
Finished Aug 02 07:22:03 PM PDT 24
Peak memory 216560 kb
Host smart-886edefd-7ca0-4b9f-8e48-043bca91e5b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490040755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.1490040755
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1142401780
Short name T105
Test name
Test status
Simulation time 47853156 ps
CPU time 1.12 seconds
Started Aug 02 07:21:02 PM PDT 24
Finished Aug 02 07:21:04 PM PDT 24
Peak memory 200368 kb
Host smart-bae3e676-3b97-4021-91ad-3e44dfa46fa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142401780 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.1142401780
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.2042251823
Short name T42
Test name
Test status
Simulation time 16660497 ps
CPU time 0.78 seconds
Started Aug 02 07:23:10 PM PDT 24
Finished Aug 02 07:23:11 PM PDT 24
Peak memory 201056 kb
Host smart-6f842b99-bd38-4745-b12e-205514bf7ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042251823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.2042251823
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.3631582312
Short name T35
Test name
Test status
Simulation time 40420017144 ps
CPU time 592.56 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:32:52 PM PDT 24
Peak memory 217964 kb
Host smart-a3b56a7a-12fe-42aa-8578-8ddaf59c8cd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3631582312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3631582312
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3140127851
Short name T74
Test name
Test status
Simulation time 71398848 ps
CPU time 1.45 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200640 kb
Host smart-6fd139fd-5c19-4253-b500-ebb8975fc236
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140127851 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3140127851
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.4108611419
Short name T13
Test name
Test status
Simulation time 673745905 ps
CPU time 4.04 seconds
Started Aug 02 07:24:12 PM PDT 24
Finished Aug 02 07:24:16 PM PDT 24
Peak memory 201384 kb
Host smart-a9eac8a3-8045-4c9c-b81e-76b86776cf19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108611419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.4108611419
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2373083155
Short name T136
Test name
Test status
Simulation time 207224137 ps
CPU time 2 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200084 kb
Host smart-24012d14-424e-4275-9542-dc6a190bb2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373083155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.2373083155
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2892300925
Short name T176
Test name
Test status
Simulation time 122933770 ps
CPU time 1.6 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200620 kb
Host smart-1ee49298-b99f-4d91-a003-63f4480eb392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892300925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.2892300925
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.2184654153
Short name T28
Test name
Test status
Simulation time 27225010 ps
CPU time 0.92 seconds
Started Aug 02 07:22:12 PM PDT 24
Finished Aug 02 07:22:13 PM PDT 24
Peak memory 201140 kb
Host smart-c299975b-fc83-4306-b7df-59a03217d549
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184654153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.2184654153
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2196311859
Short name T117
Test name
Test status
Simulation time 22531974 ps
CPU time 0.82 seconds
Started Aug 02 07:22:19 PM PDT 24
Finished Aug 02 07:22:20 PM PDT 24
Peak memory 201108 kb
Host smart-987b9747-a304-4643-9b0a-06023aa32571
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196311859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.2196311859
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.943039754
Short name T125
Test name
Test status
Simulation time 346041444 ps
CPU time 3.14 seconds
Started Aug 02 07:19:56 PM PDT 24
Finished Aug 02 07:19:59 PM PDT 24
Peak memory 200580 kb
Host smart-396a4135-a4ba-4d08-8c06-41a98859b2ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943039754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_tl_intg_err.943039754
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.782695548
Short name T153
Test name
Test status
Simulation time 168471479 ps
CPU time 2.15 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200804 kb
Host smart-a17f7ec9-aaf9-487f-8d5e-980c2867fd02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782695548 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.clkmgr_shadow_reg_errors.782695548
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.1459291569
Short name T45
Test name
Test status
Simulation time 11573542313 ps
CPU time 83.27 seconds
Started Aug 02 07:23:16 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201548 kb
Host smart-ad4d1bc5-57b8-43ee-815b-f2037d9691d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459291569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.1459291569
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.295124991
Short name T133
Test name
Test status
Simulation time 143496231 ps
CPU time 2.91 seconds
Started Aug 02 07:19:59 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 200704 kb
Host smart-0cd5302a-387a-4a7c-829b-e63ad457e05d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295124991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.clkmgr_tl_intg_err.295124991
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3876126453
Short name T973
Test name
Test status
Simulation time 110152390 ps
CPU time 1.96 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:03 PM PDT 24
Peak memory 200628 kb
Host smart-7e7c7958-b203-4433-aa3b-6bc31e87c951
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876126453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.3876126453
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.219184278
Short name T167
Test name
Test status
Simulation time 2036920595 ps
CPU time 9.3 seconds
Started Aug 02 07:19:58 PM PDT 24
Finished Aug 02 07:20:08 PM PDT 24
Peak memory 200616 kb
Host smart-9f9e68e9-cb89-49fb-b21d-4f2669068c51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219184278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_bit_bash.219184278
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.547942111
Short name T869
Test name
Test status
Simulation time 73880939 ps
CPU time 0.97 seconds
Started Aug 02 07:19:57 PM PDT 24
Finished Aug 02 07:19:59 PM PDT 24
Peak memory 200412 kb
Host smart-43656ce0-8307-41ab-a2fa-b53c7092b76d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547942111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_hw_reset.547942111
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2075037304
Short name T130
Test name
Test status
Simulation time 37716619 ps
CPU time 1.27 seconds
Started Aug 02 07:20:02 PM PDT 24
Finished Aug 02 07:20:03 PM PDT 24
Peak memory 200452 kb
Host smart-6c4c8006-a384-4dc4-ace4-960df35cfe2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075037304 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2075037304
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3456260353
Short name T970
Test name
Test status
Simulation time 60954620 ps
CPU time 0.98 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 200396 kb
Host smart-1389ebfa-4bd2-4550-ac5d-bba8040eea9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456260353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.3456260353
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1829169543
Short name T977
Test name
Test status
Simulation time 98263522 ps
CPU time 0.84 seconds
Started Aug 02 07:20:04 PM PDT 24
Finished Aug 02 07:20:05 PM PDT 24
Peak memory 198952 kb
Host smart-39ae1462-b63c-43c1-912b-49e93336d4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829169543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.1829169543
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1313506723
Short name T863
Test name
Test status
Simulation time 161597268 ps
CPU time 1.61 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 200604 kb
Host smart-1ebdba96-75a1-4915-9d6b-8a1d02903edf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313506723 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.1313506723
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3710089030
Short name T79
Test name
Test status
Simulation time 100345335 ps
CPU time 1.4 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 200704 kb
Host smart-e4b62283-b8de-44d0-90e3-60c763a5001c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710089030 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.3710089030
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3065423563
Short name T899
Test name
Test status
Simulation time 202147222 ps
CPU time 2.19 seconds
Started Aug 02 07:20:04 PM PDT 24
Finished Aug 02 07:20:07 PM PDT 24
Peak memory 200920 kb
Host smart-82617686-2808-452b-ad77-26b66732a0e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065423563 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3065423563
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4121779314
Short name T933
Test name
Test status
Simulation time 278995161 ps
CPU time 2.96 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:04 PM PDT 24
Peak memory 200648 kb
Host smart-cea27ecf-a53d-4d79-b9e0-058cd927af0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121779314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.4121779314
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.508370065
Short name T841
Test name
Test status
Simulation time 261345248 ps
CPU time 2.38 seconds
Started Aug 02 07:20:05 PM PDT 24
Finished Aug 02 07:20:07 PM PDT 24
Peak memory 200608 kb
Host smart-bdeb4d1b-2095-483e-8b9f-0f9839af5eb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508370065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_aliasing.508370065
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3513224742
Short name T916
Test name
Test status
Simulation time 729607093 ps
CPU time 8.17 seconds
Started Aug 02 07:19:57 PM PDT 24
Finished Aug 02 07:20:05 PM PDT 24
Peak memory 200616 kb
Host smart-39b43c0f-7df6-4370-a2ce-eda08f320f82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513224742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.3513224742
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.57687878
Short name T885
Test name
Test status
Simulation time 18624833 ps
CPU time 0.84 seconds
Started Aug 02 07:20:02 PM PDT 24
Finished Aug 02 07:20:03 PM PDT 24
Peak memory 200372 kb
Host smart-cf089079-3a4a-44bc-a74b-e18af4a9a745
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57687878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_csr_hw_reset.57687878
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1490395467
Short name T936
Test name
Test status
Simulation time 59771412 ps
CPU time 1.7 seconds
Started Aug 02 07:20:04 PM PDT 24
Finished Aug 02 07:20:06 PM PDT 24
Peak memory 216928 kb
Host smart-ef2f8440-d3b6-4789-a4a4-5d044985561d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490395467 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.1490395467
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3657446936
Short name T966
Test name
Test status
Simulation time 73980638 ps
CPU time 0.93 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:01 PM PDT 24
Peak memory 200524 kb
Host smart-5ea3374e-f3c8-4078-9776-7d16364aa33b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657446936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.3657446936
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2506654437
Short name T918
Test name
Test status
Simulation time 30434247 ps
CPU time 0.74 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 199076 kb
Host smart-b82c00cc-2666-463c-8c1c-f0151318d46e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506654437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.2506654437
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2155271368
Short name T975
Test name
Test status
Simulation time 41618667 ps
CPU time 0.98 seconds
Started Aug 02 07:20:05 PM PDT 24
Finished Aug 02 07:20:06 PM PDT 24
Peak memory 200356 kb
Host smart-354838a0-5f4b-4d8c-a5e2-aabec4c24c0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155271368 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.2155271368
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3026089947
Short name T939
Test name
Test status
Simulation time 120468026 ps
CPU time 2.03 seconds
Started Aug 02 07:19:57 PM PDT 24
Finished Aug 02 07:19:59 PM PDT 24
Peak memory 200896 kb
Host smart-4e7bdb37-fa09-4347-aa15-63eae1a752c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026089947 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.3026089947
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3433955302
Short name T892
Test name
Test status
Simulation time 141213124 ps
CPU time 1.73 seconds
Started Aug 02 07:19:58 PM PDT 24
Finished Aug 02 07:19:59 PM PDT 24
Peak memory 209056 kb
Host smart-8abab2c5-4e90-42ca-aadd-c69c166a750f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433955302 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.3433955302
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2598066190
Short name T859
Test name
Test status
Simulation time 368533150 ps
CPU time 3.41 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:05 PM PDT 24
Peak memory 200572 kb
Host smart-a6feab10-b500-4f9c-9c55-622feb974aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598066190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.2598066190
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.42436342
Short name T842
Test name
Test status
Simulation time 102327632 ps
CPU time 1.34 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200496 kb
Host smart-ba6e48f5-3d79-4e32-a6b4-29b233618387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42436342 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.42436342
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2779267031
Short name T926
Test name
Test status
Simulation time 25194054 ps
CPU time 0.78 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200344 kb
Host smart-d0010dbc-9bca-40f6-8d88-1537703393ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779267031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.2779267031
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.356991462
Short name T831
Test name
Test status
Simulation time 25141490 ps
CPU time 0.71 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 198960 kb
Host smart-1c5eb3fc-71e5-4330-9a5d-4c427a41f976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356991462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_intr_test.356991462
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1648174354
Short name T860
Test name
Test status
Simulation time 236353953 ps
CPU time 1.44 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200336 kb
Host smart-0c868523-7e70-49a3-87ad-63f835c64bef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648174354 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.1648174354
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.215915682
Short name T974
Test name
Test status
Simulation time 121948623 ps
CPU time 1.78 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200868 kb
Host smart-59b39f3b-9200-40ff-952c-6a16ad7b722f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215915682 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.215915682
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.420375292
Short name T852
Test name
Test status
Simulation time 105130617 ps
CPU time 2.63 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200512 kb
Host smart-ca888c4c-5a9b-479c-8de6-0fa7fe74e850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420375292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_tl_errors.420375292
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3979877805
Short name T962
Test name
Test status
Simulation time 29485272 ps
CPU time 1.03 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 200412 kb
Host smart-3f5d686f-f6de-4553-aaff-dbaef1896692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979877805 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.3979877805
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.742595661
Short name T906
Test name
Test status
Simulation time 15566921 ps
CPU time 0.83 seconds
Started Aug 02 07:20:51 PM PDT 24
Finished Aug 02 07:20:52 PM PDT 24
Peak memory 200376 kb
Host smart-1d301838-e5a1-444a-9019-f4374199913d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742595661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
clkmgr_csr_rw.742595661
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.18077929
Short name T825
Test name
Test status
Simulation time 15011666 ps
CPU time 0.66 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 199008 kb
Host smart-2c41efd5-c4f7-47c3-b662-f8224c02729a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18077929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkm
gr_intr_test.18077929
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3348183937
Short name T944
Test name
Test status
Simulation time 37387206 ps
CPU time 0.96 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200392 kb
Host smart-e267672e-22fd-4650-b31e-3f0914114e6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348183937 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.3348183937
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.4220804729
Short name T81
Test name
Test status
Simulation time 74886433 ps
CPU time 1.4 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200780 kb
Host smart-cbc73940-b4ec-40ba-9470-64490a92c0bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220804729 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.4220804729
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3473325128
Short name T943
Test name
Test status
Simulation time 217536066 ps
CPU time 2.02 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 209092 kb
Host smart-b59e81aa-a64e-43ff-a30a-fe90b3098bae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473325128 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3473325128
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.4021613794
Short name T917
Test name
Test status
Simulation time 67797923 ps
CPU time 2.27 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200572 kb
Host smart-ba3b334f-7003-408e-b478-75439cc4288c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021613794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.4021613794
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.437808976
Short name T835
Test name
Test status
Simulation time 122984631 ps
CPU time 1.51 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200476 kb
Host smart-fe4e9176-1ad0-4c15-8e5d-2f0e156abeac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437808976 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.437808976
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3659099560
Short name T879
Test name
Test status
Simulation time 24657598 ps
CPU time 0.83 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200412 kb
Host smart-91e6fcf3-b1e4-4fd3-b27f-abb15e732646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659099560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.3659099560
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3451701390
Short name T888
Test name
Test status
Simulation time 23666539 ps
CPU time 0.7 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 199084 kb
Host smart-8bf7071d-36d9-48f0-a097-c11217cff25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451701390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.3451701390
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2979634032
Short name T925
Test name
Test status
Simulation time 100510536 ps
CPU time 1.4 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200660 kb
Host smart-00f633a5-b4ea-4e11-97b3-a36cd371f1d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979634032 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.2979634032
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1161877425
Short name T924
Test name
Test status
Simulation time 545737234 ps
CPU time 3.91 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:21:00 PM PDT 24
Peak memory 217160 kb
Host smart-b4781fa3-3fa6-4076-bcf0-17e1663b8462
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161877425 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1161877425
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2621372226
Short name T877
Test name
Test status
Simulation time 67705105 ps
CPU time 1.86 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200696 kb
Host smart-95493f6c-6b3f-4771-80e3-938d691c1b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621372226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.2621372226
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2829007701
Short name T124
Test name
Test status
Simulation time 127448629 ps
CPU time 1.69 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200572 kb
Host smart-f489ed48-baca-418e-9579-4a86fb52aa2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829007701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.2829007701
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.483158854
Short name T868
Test name
Test status
Simulation time 36490033 ps
CPU time 1.71 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200624 kb
Host smart-65e76c30-a81d-4369-9ddc-ec3ecf14a98b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483158854 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.483158854
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.7874649
Short name T923
Test name
Test status
Simulation time 16238455 ps
CPU time 0.78 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200428 kb
Host smart-d5203cf5-c747-4af1-9655-9a397b0d052e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7874649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_csr_rw.7874649
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1689304391
Short name T824
Test name
Test status
Simulation time 16821634 ps
CPU time 0.65 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 198956 kb
Host smart-8823a084-644a-4414-a84c-ba957d526d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689304391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.1689304391
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3840600930
Short name T110
Test name
Test status
Simulation time 186441584 ps
CPU time 1.68 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200588 kb
Host smart-bd5fe909-bc4b-409f-bb4a-082f1a6b6a0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840600930 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.3840600930
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1120095867
Short name T976
Test name
Test status
Simulation time 166602579 ps
CPU time 1.96 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 216944 kb
Host smart-84cdd767-5514-4df2-b472-c5c478b8c40c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120095867 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.1120095867
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3510279686
Short name T920
Test name
Test status
Simulation time 287723710 ps
CPU time 2.43 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 209076 kb
Host smart-f7b0c8bd-4ea9-4b8e-bdba-77148b1b2c4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510279686 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.3510279686
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2385510709
Short name T907
Test name
Test status
Simulation time 179253723 ps
CPU time 3.02 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200624 kb
Host smart-b06ec4a5-3561-4feb-b018-d5a14288e0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385510709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.2385510709
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.678953712
Short name T137
Test name
Test status
Simulation time 351438261 ps
CPU time 3.13 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200624 kb
Host smart-6eafe04c-8e52-4c4d-8159-b2ebd9280348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678953712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.clkmgr_tl_intg_err.678953712
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2205891072
Short name T856
Test name
Test status
Simulation time 172705038 ps
CPU time 1.19 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 200468 kb
Host smart-dff45ce5-e86d-46ce-ac67-416b6104778d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205891072 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.2205891072
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2119245677
Short name T107
Test name
Test status
Simulation time 45376911 ps
CPU time 0.83 seconds
Started Aug 02 07:20:57 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200408 kb
Host smart-bf5c9c36-ab89-4654-9fe2-53c8859481e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119245677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.2119245677
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1471120603
Short name T898
Test name
Test status
Simulation time 39235366 ps
CPU time 0.74 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 199076 kb
Host smart-bce5b4f3-2711-4d03-8057-0d27d9c5cc1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471120603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.1471120603
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2338345818
Short name T861
Test name
Test status
Simulation time 55682752 ps
CPU time 1.42 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200600 kb
Host smart-890857c4-aa51-474a-890d-641f070e1335
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338345818 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.2338345818
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1545224753
Short name T909
Test name
Test status
Simulation time 153010490 ps
CPU time 1.5 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200788 kb
Host smart-d5214050-5e48-4f34-838d-5fd56ef38aa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545224753 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.1545224753
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1624830559
Short name T963
Test name
Test status
Simulation time 423828651 ps
CPU time 3.43 seconds
Started Aug 02 07:21:07 PM PDT 24
Finished Aug 02 07:21:11 PM PDT 24
Peak memory 209016 kb
Host smart-0a1f5063-0b81-4b23-bde6-dc20522f446d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624830559 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.1624830559
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2349009182
Short name T910
Test name
Test status
Simulation time 62465708 ps
CPU time 2.94 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 200576 kb
Host smart-ed44fc1a-b3d8-409b-b3fd-118ebb506200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349009182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.2349009182
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1860964085
Short name T956
Test name
Test status
Simulation time 116143922 ps
CPU time 1.73 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:02 PM PDT 24
Peak memory 200668 kb
Host smart-8815f4a6-d207-4410-b128-49e769736584
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860964085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.1860964085
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.981593425
Short name T948
Test name
Test status
Simulation time 73271706 ps
CPU time 1.3 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200524 kb
Host smart-4bed09d3-bbde-4b88-88f1-99e8ada251b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981593425 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.981593425
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4130942362
Short name T878
Test name
Test status
Simulation time 17699989 ps
CPU time 0.78 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 200444 kb
Host smart-1d8ea61b-912b-484b-bbae-59f8ffb71e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130942362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.4130942362
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2344261790
Short name T865
Test name
Test status
Simulation time 29733629 ps
CPU time 0.7 seconds
Started Aug 02 07:20:57 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 199012 kb
Host smart-bca837b2-16a7-4280-b46a-9c7dec84236a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344261790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2344261790
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.612650987
Short name T889
Test name
Test status
Simulation time 83609456 ps
CPU time 1.42 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:21:00 PM PDT 24
Peak memory 200636 kb
Host smart-d1280da4-2531-4f88-b7e1-2706d4746981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612650987 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 15.clkmgr_same_csr_outstanding.612650987
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1037237805
Short name T884
Test name
Test status
Simulation time 590039240 ps
CPU time 4.73 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:05 PM PDT 24
Peak memory 209148 kb
Host smart-26adcf1c-5df9-4443-ae9d-1db2973bc221
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037237805 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.1037237805
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.318117847
Short name T893
Test name
Test status
Simulation time 191449507 ps
CPU time 2.96 seconds
Started Aug 02 07:20:57 PM PDT 24
Finished Aug 02 07:21:00 PM PDT 24
Peak memory 200620 kb
Host smart-b28cd37f-c6a4-4948-9fb2-790db82d10dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318117847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk
mgr_tl_errors.318117847
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3915462563
Short name T900
Test name
Test status
Simulation time 342665419 ps
CPU time 3.03 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:21:00 PM PDT 24
Peak memory 200616 kb
Host smart-baccac4f-ce2e-4a47-8af9-6533013f9fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915462563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.3915462563
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1298833085
Short name T930
Test name
Test status
Simulation time 45046281 ps
CPU time 1.38 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 200472 kb
Host smart-76fe2b20-bfa7-4354-a90f-2f7f2a977b8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298833085 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.1298833085
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1635109876
Short name T903
Test name
Test status
Simulation time 43793179 ps
CPU time 0.84 seconds
Started Aug 02 07:21:04 PM PDT 24
Finished Aug 02 07:21:05 PM PDT 24
Peak memory 200260 kb
Host smart-3bd6aaf4-c541-4740-a7d9-e991f01a4c3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635109876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.1635109876
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3979401325
Short name T928
Test name
Test status
Simulation time 15224861 ps
CPU time 0.68 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 198996 kb
Host smart-0f4c1c33-3964-4f49-b5e8-002c826452fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979401325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.3979401325
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.792757682
Short name T927
Test name
Test status
Simulation time 91837100 ps
CPU time 1.15 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 200304 kb
Host smart-5522ae93-5e41-4c0a-b0cb-63709d40aa8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792757682 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 16.clkmgr_same_csr_outstanding.792757682
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1255774845
Short name T80
Test name
Test status
Simulation time 131973186 ps
CPU time 1.46 seconds
Started Aug 02 07:20:59 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 200680 kb
Host smart-9b06bbba-d64d-4a5d-a5cf-c8b12c5492dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255774845 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.1255774845
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.4252575964
Short name T147
Test name
Test status
Simulation time 156644864 ps
CPU time 2.13 seconds
Started Aug 02 07:20:57 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 209072 kb
Host smart-14542a06-631e-4c1d-b441-09182156ae71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252575964 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.4252575964
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1077177299
Short name T967
Test name
Test status
Simulation time 139378827 ps
CPU time 2.22 seconds
Started Aug 02 07:20:59 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 200632 kb
Host smart-11691526-1678-427a-85c2-207e9426facd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077177299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.1077177299
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1815417885
Short name T177
Test name
Test status
Simulation time 229431097 ps
CPU time 2.95 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:03 PM PDT 24
Peak memory 200508 kb
Host smart-22f22e16-de06-44c6-8375-4702447ae003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815417885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.1815417885
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3235133976
Short name T890
Test name
Test status
Simulation time 30184497 ps
CPU time 1.08 seconds
Started Aug 02 07:21:01 PM PDT 24
Finished Aug 02 07:21:03 PM PDT 24
Peak memory 200196 kb
Host smart-5906ba7c-5682-4bd5-bf39-b2e98f55ad7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235133976 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3235133976
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.4016174295
Short name T867
Test name
Test status
Simulation time 17668477 ps
CPU time 0.79 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 200396 kb
Host smart-d5cbba14-7e0d-40c8-a9cb-20337e496630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016174295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.4016174295
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.475611076
Short name T902
Test name
Test status
Simulation time 13762099 ps
CPU time 0.7 seconds
Started Aug 02 07:20:57 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 199144 kb
Host smart-dc0a4735-7e6f-417a-bc10-9ea444afdc46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475611076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk
mgr_intr_test.475611076
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2817816703
Short name T111
Test name
Test status
Simulation time 197907285 ps
CPU time 1.71 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200612 kb
Host smart-2bf7b3c4-8b75-40ce-94e6-22010a3cc291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817816703 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.2817816703
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3915657186
Short name T914
Test name
Test status
Simulation time 158710512 ps
CPU time 1.81 seconds
Started Aug 02 07:20:59 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 200844 kb
Host smart-cd312693-3aa9-451f-8dea-97a029f368dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915657186 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3915657186
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1469732374
Short name T83
Test name
Test status
Simulation time 109990148 ps
CPU time 2.57 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:21:00 PM PDT 24
Peak memory 201092 kb
Host smart-cf1a4233-ffe7-4f82-af9e-eb2161af2ff6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469732374 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.1469732374
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.1521543446
Short name T945
Test name
Test status
Simulation time 200525120 ps
CPU time 1.76 seconds
Started Aug 02 07:21:02 PM PDT 24
Finished Aug 02 07:21:04 PM PDT 24
Peak memory 200356 kb
Host smart-65fe3117-54b9-4c3f-8f44-2df18934b5cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521543446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.1521543446
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1066406764
Short name T138
Test name
Test status
Simulation time 100401704 ps
CPU time 2.51 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 200608 kb
Host smart-7793bdd2-2f1a-442f-a333-e87c24a426dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066406764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.1066406764
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3461560533
Short name T921
Test name
Test status
Simulation time 79645470 ps
CPU time 1.2 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 200488 kb
Host smart-5bc4f9a2-8b16-4efb-a830-dd147abdccc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461560533 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.3461560533
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2976527536
Short name T881
Test name
Test status
Simulation time 28500864 ps
CPU time 0.85 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200416 kb
Host smart-6c4f7abd-05b3-42cb-945f-1be32732404a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976527536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.2976527536
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3461507543
Short name T829
Test name
Test status
Simulation time 12627446 ps
CPU time 0.66 seconds
Started Aug 02 07:21:02 PM PDT 24
Finished Aug 02 07:21:02 PM PDT 24
Peak memory 198956 kb
Host smart-91f4b4fd-c545-4635-b70a-a35854d01266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461507543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.3461507543
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2668789080
Short name T76
Test name
Test status
Simulation time 150251693 ps
CPU time 2.55 seconds
Started Aug 02 07:21:02 PM PDT 24
Finished Aug 02 07:21:05 PM PDT 24
Peak memory 209008 kb
Host smart-a1c17688-5e35-4ff0-9620-7d67f6c1ebb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668789080 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.2668789080
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.974365940
Short name T937
Test name
Test status
Simulation time 55385619 ps
CPU time 1.73 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:02 PM PDT 24
Peak memory 200596 kb
Host smart-dfd14451-0efc-4a8d-863f-c716cdebe6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974365940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_tl_errors.974365940
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1856734633
Short name T134
Test name
Test status
Simulation time 113818208 ps
CPU time 2.37 seconds
Started Aug 02 07:21:01 PM PDT 24
Finished Aug 02 07:21:04 PM PDT 24
Peak memory 200352 kb
Host smart-1eebac2b-7e76-412e-8088-8f7b614297f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856734633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.1856734633
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3410686020
Short name T855
Test name
Test status
Simulation time 39939548 ps
CPU time 1.4 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 200492 kb
Host smart-5246c85f-0575-4bf2-a87f-e5d66d4e9b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410686020 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3410686020
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3798592717
Short name T922
Test name
Test status
Simulation time 52209979 ps
CPU time 0.82 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200372 kb
Host smart-338bb525-4bd5-4665-a296-7b3d7bcd4f31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798592717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.3798592717
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3333778468
Short name T932
Test name
Test status
Simulation time 31726549 ps
CPU time 0.69 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 199052 kb
Host smart-2410292d-57de-4695-af58-ccb0f4a7b06d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333778468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.3333778468
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3292937954
Short name T873
Test name
Test status
Simulation time 201091995 ps
CPU time 1.63 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200632 kb
Host smart-3f4e68f5-6eff-4cc9-b70a-7df9b960db0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292937954 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.3292937954
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2304573917
Short name T152
Test name
Test status
Simulation time 101641060 ps
CPU time 1.26 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200732 kb
Host smart-bacb4b50-3866-4667-8203-d694db1a4bae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304573917 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.2304573917
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2422362021
Short name T154
Test name
Test status
Simulation time 98660712 ps
CPU time 2.55 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 201056 kb
Host smart-3b2bdb51-7aa9-41af-a508-e0c945e81a3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422362021 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2422362021
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1496190328
Short name T958
Test name
Test status
Simulation time 64832210 ps
CPU time 2.18 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200540 kb
Host smart-09e24e2e-4a39-4387-9ae4-19fb5003e7af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496190328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.1496190328
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.205277694
Short name T954
Test name
Test status
Simulation time 63755036 ps
CPU time 1.61 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200564 kb
Host smart-fc5b447a-2f12-4312-9f32-a0d7f5925be4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205277694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_tl_intg_err.205277694
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.823484563
Short name T849
Test name
Test status
Simulation time 22610201 ps
CPU time 1.15 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 200436 kb
Host smart-1b96a9fd-f5cb-4cb7-98b0-d086891e8b58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823484563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_aliasing.823484563
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1033150202
Short name T838
Test name
Test status
Simulation time 6597125533 ps
CPU time 21.89 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:23 PM PDT 24
Peak memory 200684 kb
Host smart-acafae51-46e6-4bb7-b664-0d8afffe800d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033150202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.1033150202
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.4282476489
Short name T875
Test name
Test status
Simulation time 44330441 ps
CPU time 0.81 seconds
Started Aug 02 07:19:56 PM PDT 24
Finished Aug 02 07:19:57 PM PDT 24
Peak memory 200384 kb
Host smart-654ae415-db09-4557-ab7b-ce5baa9cd20b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282476489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.4282476489
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1123533707
Short name T844
Test name
Test status
Simulation time 21677992 ps
CPU time 1.29 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 200544 kb
Host smart-75e67220-dbf2-4afd-bbf7-4000619b9521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123533707 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.1123533707
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.801839945
Short name T870
Test name
Test status
Simulation time 142322380 ps
CPU time 1.06 seconds
Started Aug 02 07:19:59 PM PDT 24
Finished Aug 02 07:20:00 PM PDT 24
Peak memory 200412 kb
Host smart-73b5fb63-7336-46f7-a49f-d6294cc1dadf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801839945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.c
lkmgr_csr_rw.801839945
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.744983245
Short name T866
Test name
Test status
Simulation time 14293066 ps
CPU time 0.69 seconds
Started Aug 02 07:19:58 PM PDT 24
Finished Aug 02 07:19:59 PM PDT 24
Peak memory 199016 kb
Host smart-4e253081-3191-49db-b170-3674fd83a6f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744983245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_intr_test.744983245
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1049050333
Short name T109
Test name
Test status
Simulation time 49620576 ps
CPU time 1.3 seconds
Started Aug 02 07:19:58 PM PDT 24
Finished Aug 02 07:20:00 PM PDT 24
Peak memory 200432 kb
Host smart-78aaec70-1327-4107-b379-8b942e6638f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049050333 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.1049050333
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2364752278
Short name T151
Test name
Test status
Simulation time 305684193 ps
CPU time 2.37 seconds
Started Aug 02 07:20:03 PM PDT 24
Finished Aug 02 07:20:05 PM PDT 24
Peak memory 200976 kb
Host smart-db6245fc-d87f-45bc-9b8c-263b44561b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364752278 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.2364752278
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3111639662
Short name T950
Test name
Test status
Simulation time 99808695 ps
CPU time 1.99 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 209084 kb
Host smart-5a21f32e-598f-4f90-9376-74e92fab4759
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111639662 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.3111639662
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.574397440
Short name T823
Test name
Test status
Simulation time 239864549 ps
CPU time 2.42 seconds
Started Aug 02 07:20:04 PM PDT 24
Finished Aug 02 07:20:07 PM PDT 24
Peak memory 200568 kb
Host smart-70cbc8e9-3430-4764-9807-dca3f653aca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574397440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_tl_errors.574397440
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.2136483779
Short name T178
Test name
Test status
Simulation time 71763025 ps
CPU time 1.88 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:03 PM PDT 24
Peak memory 200672 kb
Host smart-e863e789-6d0c-45a5-a7c9-20f55cb66d47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136483779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.2136483779
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1634856835
Short name T965
Test name
Test status
Simulation time 16602914 ps
CPU time 0.67 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 199052 kb
Host smart-3df28dae-05a0-48e7-b433-e9727fdb0283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634856835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.1634856835
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3196106903
Short name T971
Test name
Test status
Simulation time 11757035 ps
CPU time 0.66 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 199056 kb
Host smart-9dd1adbf-8b6d-4570-8669-c6b901de0115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196106903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.3196106903
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.183059131
Short name T827
Test name
Test status
Simulation time 16586814 ps
CPU time 0.67 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 199160 kb
Host smart-7940ceb9-18d6-495e-a375-0b6844d1b8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183059131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clk
mgr_intr_test.183059131
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3804457462
Short name T854
Test name
Test status
Simulation time 39163068 ps
CPU time 0.74 seconds
Started Aug 02 07:20:57 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 199100 kb
Host smart-7835ec9c-8f6e-49fc-8aa8-4719b2020665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804457462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.3804457462
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1186568663
Short name T874
Test name
Test status
Simulation time 19846114 ps
CPU time 0.68 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 199088 kb
Host smart-4f29ff13-db70-4cfc-865d-49d29807feda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186568663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.1186568663
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.222694895
Short name T951
Test name
Test status
Simulation time 17209720 ps
CPU time 0.71 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 199044 kb
Host smart-c531276c-8c69-40ec-a4e9-c58b3b0efa51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222694895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk
mgr_intr_test.222694895
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2688883952
Short name T961
Test name
Test status
Simulation time 12376931 ps
CPU time 0.66 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 199032 kb
Host smart-b67bb722-fa41-4f8e-8587-6cc5e73d1568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688883952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.2688883952
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1995040832
Short name T857
Test name
Test status
Simulation time 24831883 ps
CPU time 0.67 seconds
Started Aug 02 07:21:00 PM PDT 24
Finished Aug 02 07:21:01 PM PDT 24
Peak memory 199056 kb
Host smart-361bda81-c501-4ab4-a424-2b57384b9bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995040832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.1995040832
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.463475890
Short name T883
Test name
Test status
Simulation time 27554355 ps
CPU time 0.68 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 199032 kb
Host smart-e1b49957-b89d-465f-b82b-74a690ceacc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463475890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk
mgr_intr_test.463475890
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2828741072
Short name T912
Test name
Test status
Simulation time 30244794 ps
CPU time 0.73 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 199016 kb
Host smart-424ad52d-0641-4c07-a632-f700086bb70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828741072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.2828741072
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3744419168
Short name T929
Test name
Test status
Simulation time 22253641 ps
CPU time 1.13 seconds
Started Aug 02 07:19:59 PM PDT 24
Finished Aug 02 07:20:00 PM PDT 24
Peak memory 200440 kb
Host smart-38bcd4f3-6503-4851-b218-e26c59d9fcad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744419168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.3744419168
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1462436887
Short name T872
Test name
Test status
Simulation time 220594639 ps
CPU time 4.52 seconds
Started Aug 02 07:19:59 PM PDT 24
Finished Aug 02 07:20:03 PM PDT 24
Peak memory 200544 kb
Host smart-1907e73d-e977-465e-a81c-0860126e7327
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462436887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.1462436887
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.509347830
Short name T166
Test name
Test status
Simulation time 61860554 ps
CPU time 0.85 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:01 PM PDT 24
Peak memory 200368 kb
Host smart-20a1d5b6-99e2-420d-bd96-932ba8e47333
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509347830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_hw_reset.509347830
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.533764804
Short name T129
Test name
Test status
Simulation time 68302632 ps
CPU time 1.31 seconds
Started Aug 02 07:20:05 PM PDT 24
Finished Aug 02 07:20:06 PM PDT 24
Peak memory 200568 kb
Host smart-889b6de9-1f91-44f7-bc57-21dc3f23aa40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533764804 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.533764804
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.585558476
Short name T955
Test name
Test status
Simulation time 39950279 ps
CPU time 0.9 seconds
Started Aug 02 07:19:57 PM PDT 24
Finished Aug 02 07:19:58 PM PDT 24
Peak memory 200472 kb
Host smart-4faa9328-4b0b-4820-80a2-fa17c9cc8d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585558476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.c
lkmgr_csr_rw.585558476
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.882296244
Short name T833
Test name
Test status
Simulation time 74868343 ps
CPU time 0.81 seconds
Started Aug 02 07:19:59 PM PDT 24
Finished Aug 02 07:20:00 PM PDT 24
Peak memory 199008 kb
Host smart-e35fd108-26b7-4361-b40b-6c31db5aea01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882296244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm
gr_intr_test.882296244
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2133356938
Short name T840
Test name
Test status
Simulation time 55403258 ps
CPU time 1.35 seconds
Started Aug 02 07:20:04 PM PDT 24
Finished Aug 02 07:20:06 PM PDT 24
Peak memory 200656 kb
Host smart-b3c98a12-b79a-4cfa-ab00-089b031e3f1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133356938 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.2133356938
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1691761752
Short name T972
Test name
Test status
Simulation time 172798460 ps
CPU time 1.99 seconds
Started Aug 02 07:19:59 PM PDT 24
Finished Aug 02 07:20:01 PM PDT 24
Peak memory 217236 kb
Host smart-1504bdbd-f507-41dc-a284-36edcbee70b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691761752 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.1691761752
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1151394970
Short name T77
Test name
Test status
Simulation time 67174968 ps
CPU time 1.68 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 209100 kb
Host smart-a2d6d64e-91b0-41de-a9ab-d676d2d097c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151394970 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.1151394970
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1880637695
Short name T941
Test name
Test status
Simulation time 153512569 ps
CPU time 2.98 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:03 PM PDT 24
Peak memory 200584 kb
Host smart-33f14b93-eda9-4bc7-8709-e07ce6542c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880637695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.1880637695
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2543496074
Short name T127
Test name
Test status
Simulation time 56149116 ps
CPU time 1.5 seconds
Started Aug 02 07:19:58 PM PDT 24
Finished Aug 02 07:20:00 PM PDT 24
Peak memory 200624 kb
Host smart-6b357223-9155-43a2-8eb8-1bdb249ab8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543496074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.2543496074
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2397303840
Short name T882
Test name
Test status
Simulation time 80471843 ps
CPU time 0.8 seconds
Started Aug 02 07:20:58 PM PDT 24
Finished Aug 02 07:20:59 PM PDT 24
Peak memory 199088 kb
Host smart-ddd465e4-2ffd-4c74-b2f3-b7c0c6f1d2a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397303840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.2397303840
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1921734980
Short name T919
Test name
Test status
Simulation time 41004980 ps
CPU time 0.71 seconds
Started Aug 02 07:20:57 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 199004 kb
Host smart-340c4c09-edee-40ec-86c9-1b23a3f78a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921734980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.1921734980
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2949532381
Short name T953
Test name
Test status
Simulation time 13796710 ps
CPU time 0.67 seconds
Started Aug 02 07:20:57 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 199076 kb
Host smart-35f21b95-912b-40f1-8525-27ed8e9f89c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949532381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.2949532381
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.256145696
Short name T915
Test name
Test status
Simulation time 28472327 ps
CPU time 0.68 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 199040 kb
Host smart-722a1a66-d563-40a8-8242-2b9725be2186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256145696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clk
mgr_intr_test.256145696
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.3158727634
Short name T862
Test name
Test status
Simulation time 16608506 ps
CPU time 0.65 seconds
Started Aug 02 07:21:04 PM PDT 24
Finished Aug 02 07:21:05 PM PDT 24
Peak memory 198968 kb
Host smart-0eca9327-4fe2-4877-8431-c09a9e6b393f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158727634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.3158727634
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3172015920
Short name T904
Test name
Test status
Simulation time 11836730 ps
CPU time 0.65 seconds
Started Aug 02 07:21:12 PM PDT 24
Finished Aug 02 07:21:13 PM PDT 24
Peak memory 198952 kb
Host smart-fe6522b7-c3ee-4dac-82d7-4d529f518a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172015920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.3172015920
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1278008284
Short name T836
Test name
Test status
Simulation time 11503180 ps
CPU time 0.66 seconds
Started Aug 02 07:21:03 PM PDT 24
Finished Aug 02 07:21:03 PM PDT 24
Peak memory 198976 kb
Host smart-bcb36f11-630a-4921-93a9-c6d8190930ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278008284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.1278008284
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.496301899
Short name T959
Test name
Test status
Simulation time 26880855 ps
CPU time 0.71 seconds
Started Aug 02 07:21:11 PM PDT 24
Finished Aug 02 07:21:12 PM PDT 24
Peak memory 199092 kb
Host smart-24ddae4c-abd8-4ef0-ad4c-81eeb263c5d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496301899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clk
mgr_intr_test.496301899
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.83346663
Short name T913
Test name
Test status
Simulation time 12685333 ps
CPU time 0.66 seconds
Started Aug 02 07:21:08 PM PDT 24
Finished Aug 02 07:21:09 PM PDT 24
Peak memory 199000 kb
Host smart-a7f69df0-debc-4c79-8c33-f2dc34484f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83346663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkm
gr_intr_test.83346663
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1470916781
Short name T895
Test name
Test status
Simulation time 25298681 ps
CPU time 0.69 seconds
Started Aug 02 07:21:12 PM PDT 24
Finished Aug 02 07:21:13 PM PDT 24
Peak memory 199024 kb
Host smart-6cce2cbc-d42e-42d7-8082-b5d1f84868b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470916781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.1470916781
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.4167332786
Short name T876
Test name
Test status
Simulation time 19897449 ps
CPU time 1.1 seconds
Started Aug 02 07:20:05 PM PDT 24
Finished Aug 02 07:20:06 PM PDT 24
Peak memory 200404 kb
Host smart-513b03f1-3bf0-4ccb-9781-b0ab0af6c156
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167332786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.4167332786
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3838220916
Short name T837
Test name
Test status
Simulation time 287590135 ps
CPU time 4.65 seconds
Started Aug 02 07:20:05 PM PDT 24
Finished Aug 02 07:20:09 PM PDT 24
Peak memory 200676 kb
Host smart-2669eaee-55c0-4b3f-9722-597e6898d4e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838220916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.3838220916
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1043927500
Short name T896
Test name
Test status
Simulation time 21702009 ps
CPU time 0.84 seconds
Started Aug 02 07:19:57 PM PDT 24
Finished Aug 02 07:19:58 PM PDT 24
Peak memory 200400 kb
Host smart-37b5cfa5-bed2-4ece-b41e-6c03dc77feb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043927500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.1043927500
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1233573308
Short name T964
Test name
Test status
Simulation time 28127561 ps
CPU time 1.02 seconds
Started Aug 02 07:20:13 PM PDT 24
Finished Aug 02 07:20:14 PM PDT 24
Peak memory 200408 kb
Host smart-e06980f6-b63b-4878-a248-32ca2d073cb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233573308 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.1233573308
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3664288429
Short name T106
Test name
Test status
Simulation time 116426186 ps
CPU time 1.06 seconds
Started Aug 02 07:20:05 PM PDT 24
Finished Aug 02 07:20:06 PM PDT 24
Peak memory 200340 kb
Host smart-eedeeefc-754d-49c0-a6df-d1ad87a18658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664288429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3664288429
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2950128795
Short name T911
Test name
Test status
Simulation time 33047750 ps
CPU time 0.69 seconds
Started Aug 02 07:19:59 PM PDT 24
Finished Aug 02 07:20:00 PM PDT 24
Peak memory 199100 kb
Host smart-58e2400c-3a3e-4b78-8030-0ff0b5dfe6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950128795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.2950128795
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2039048367
Short name T851
Test name
Test status
Simulation time 49543016 ps
CPU time 1.42 seconds
Started Aug 02 07:20:10 PM PDT 24
Finished Aug 02 07:20:11 PM PDT 24
Peak memory 200548 kb
Host smart-9b982505-9aad-4b1f-8350-7046045367a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039048367 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.2039048367
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.4027310157
Short name T931
Test name
Test status
Simulation time 117672719 ps
CPU time 2.05 seconds
Started Aug 02 07:20:01 PM PDT 24
Finished Aug 02 07:20:03 PM PDT 24
Peak memory 209044 kb
Host smart-8006153b-e024-4bfd-bc4e-0f9cfc180fb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027310157 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.4027310157
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.4102348108
Short name T143
Test name
Test status
Simulation time 152670183 ps
CPU time 2.85 seconds
Started Aug 02 07:20:04 PM PDT 24
Finished Aug 02 07:20:07 PM PDT 24
Peak memory 201236 kb
Host smart-34f0e881-9bd8-4fe7-8c43-77d6941f419f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102348108 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.4102348108
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1452722768
Short name T826
Test name
Test status
Simulation time 143482441 ps
CPU time 2.43 seconds
Started Aug 02 07:20:00 PM PDT 24
Finished Aug 02 07:20:03 PM PDT 24
Peak memory 200576 kb
Host smart-cddd0ea6-d3a7-4f5c-86e0-902d50921db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452722768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.1452722768
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1184741248
Short name T131
Test name
Test status
Simulation time 93873547 ps
CPU time 2.4 seconds
Started Aug 02 07:19:59 PM PDT 24
Finished Aug 02 07:20:02 PM PDT 24
Peak memory 200636 kb
Host smart-970ce670-c8f3-4930-abd1-8a523c00dbb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184741248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1184741248
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.667051664
Short name T834
Test name
Test status
Simulation time 22856898 ps
CPU time 0.77 seconds
Started Aug 02 07:21:02 PM PDT 24
Finished Aug 02 07:21:03 PM PDT 24
Peak memory 199016 kb
Host smart-c6de0810-6ab1-493a-8370-88bd82068f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667051664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clk
mgr_intr_test.667051664
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2864400557
Short name T864
Test name
Test status
Simulation time 21216006 ps
CPU time 0.68 seconds
Started Aug 02 07:21:10 PM PDT 24
Finished Aug 02 07:21:11 PM PDT 24
Peak memory 199080 kb
Host smart-143fe8ce-67d3-4409-93d9-668d834f58f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864400557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2864400557
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3048757361
Short name T934
Test name
Test status
Simulation time 13269477 ps
CPU time 0.67 seconds
Started Aug 02 07:21:10 PM PDT 24
Finished Aug 02 07:21:11 PM PDT 24
Peak memory 199152 kb
Host smart-1f7212f7-a25b-4d1b-b18e-127ec779d266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048757361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.3048757361
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3580783207
Short name T871
Test name
Test status
Simulation time 51101461 ps
CPU time 0.74 seconds
Started Aug 02 07:21:15 PM PDT 24
Finished Aug 02 07:21:16 PM PDT 24
Peak memory 199080 kb
Host smart-04ca2446-d840-4e74-b19e-51b4b1ccdc0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580783207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.3580783207
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.636015163
Short name T952
Test name
Test status
Simulation time 17314155 ps
CPU time 0.65 seconds
Started Aug 02 07:21:07 PM PDT 24
Finished Aug 02 07:21:08 PM PDT 24
Peak memory 199032 kb
Host smart-4cdf4519-91df-42dc-a2f9-d966a102e41f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636015163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clk
mgr_intr_test.636015163
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3092251293
Short name T946
Test name
Test status
Simulation time 32289412 ps
CPU time 0.7 seconds
Started Aug 02 07:21:05 PM PDT 24
Finished Aug 02 07:21:05 PM PDT 24
Peak memory 199076 kb
Host smart-79a4333e-40fd-4e83-a52e-7e64c7eb0f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092251293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.3092251293
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3548112761
Short name T853
Test name
Test status
Simulation time 22509170 ps
CPU time 0.7 seconds
Started Aug 02 07:21:10 PM PDT 24
Finished Aug 02 07:21:11 PM PDT 24
Peak memory 199080 kb
Host smart-e4b9987a-b2ac-4626-af92-072b3f515494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548112761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.3548112761
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.1115019385
Short name T839
Test name
Test status
Simulation time 30654705 ps
CPU time 0.74 seconds
Started Aug 02 07:21:03 PM PDT 24
Finished Aug 02 07:21:04 PM PDT 24
Peak memory 199016 kb
Host smart-25f44aec-ecb3-4d89-8c70-c6efbcd68f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115019385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.1115019385
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.340334445
Short name T832
Test name
Test status
Simulation time 97762931 ps
CPU time 0.89 seconds
Started Aug 02 07:21:11 PM PDT 24
Finished Aug 02 07:21:12 PM PDT 24
Peak memory 199164 kb
Host smart-32665468-3762-4271-9827-a9eb4f7cf1f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340334445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clk
mgr_intr_test.340334445
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1460112893
Short name T938
Test name
Test status
Simulation time 11943741 ps
CPU time 0.67 seconds
Started Aug 02 07:21:07 PM PDT 24
Finished Aug 02 07:21:08 PM PDT 24
Peak memory 199076 kb
Host smart-492eb740-1e3d-40ba-b28c-0045993e0183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460112893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.1460112893
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2962631868
Short name T880
Test name
Test status
Simulation time 127727312 ps
CPU time 1.41 seconds
Started Aug 02 07:20:38 PM PDT 24
Finished Aug 02 07:20:39 PM PDT 24
Peak memory 200424 kb
Host smart-96138777-fee4-4c53-ac97-6579bcb91bb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962631868 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.2962631868
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.4039767750
Short name T886
Test name
Test status
Simulation time 50197677 ps
CPU time 0.86 seconds
Started Aug 02 07:20:40 PM PDT 24
Finished Aug 02 07:20:41 PM PDT 24
Peak memory 200304 kb
Host smart-49709477-b557-469d-87f6-8215b0c02ec7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039767750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.4039767750
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.658080219
Short name T848
Test name
Test status
Simulation time 26375197 ps
CPU time 0.69 seconds
Started Aug 02 07:20:22 PM PDT 24
Finished Aug 02 07:20:23 PM PDT 24
Peak memory 199008 kb
Host smart-dba36897-b421-4a57-9001-6864a1570f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658080219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm
gr_intr_test.658080219
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2838688074
Short name T960
Test name
Test status
Simulation time 34769277 ps
CPU time 1.34 seconds
Started Aug 02 07:20:40 PM PDT 24
Finished Aug 02 07:20:42 PM PDT 24
Peak memory 200576 kb
Host smart-fbcba543-3eaf-4ac3-8115-c9ed5489fb87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838688074 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.2838688074
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1707953779
Short name T146
Test name
Test status
Simulation time 260444883 ps
CPU time 1.9 seconds
Started Aug 02 07:20:12 PM PDT 24
Finished Aug 02 07:20:14 PM PDT 24
Peak memory 200668 kb
Host smart-d9095170-49e5-4e50-af85-4ada55842019
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707953779 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1707953779
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2359299810
Short name T901
Test name
Test status
Simulation time 57746805 ps
CPU time 1.6 seconds
Started Aug 02 07:20:12 PM PDT 24
Finished Aug 02 07:20:14 PM PDT 24
Peak memory 201088 kb
Host smart-6864c44e-db36-4ef9-bb57-e694c110f8d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359299810 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.2359299810
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.712200582
Short name T830
Test name
Test status
Simulation time 131098038 ps
CPU time 3.3 seconds
Started Aug 02 07:20:22 PM PDT 24
Finished Aug 02 07:20:26 PM PDT 24
Peak memory 200592 kb
Host smart-61a493b2-0465-4449-acaa-3dac756fee49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712200582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm
gr_tl_errors.712200582
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3472445867
Short name T843
Test name
Test status
Simulation time 25190734 ps
CPU time 0.93 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 200476 kb
Host smart-e29e42fc-3bc2-4311-8cf9-5b5473ca9610
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472445867 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.3472445867
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.427975428
Short name T845
Test name
Test status
Simulation time 31464775 ps
CPU time 0.9 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200364 kb
Host smart-dc532154-21f5-4d64-815a-44283aa6d994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427975428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.c
lkmgr_csr_rw.427975428
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2690216794
Short name T887
Test name
Test status
Simulation time 21921699 ps
CPU time 0.68 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:52 PM PDT 24
Peak memory 199020 kb
Host smart-16953e3c-98e8-433b-947a-1eba5ffb09b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690216794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.2690216794
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3298473526
Short name T112
Test name
Test status
Simulation time 195602927 ps
CPU time 1.74 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200616 kb
Host smart-7a8a0184-bbfa-4e99-bc71-1cfe934b892f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298473526 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.3298473526
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.675950910
Short name T148
Test name
Test status
Simulation time 241199524 ps
CPU time 2.03 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 217040 kb
Host smart-4cd82bef-cd52-4e03-8369-22713b55f14c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675950910 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.clkmgr_shadow_reg_errors.675950910
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.767317197
Short name T968
Test name
Test status
Simulation time 376362658 ps
CPU time 3.17 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 209052 kb
Host smart-06551a0f-7ce7-4992-a670-a350427e1d2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767317197 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.767317197
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3358118833
Short name T947
Test name
Test status
Simulation time 36708005 ps
CPU time 1.98 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200580 kb
Host smart-1a24e9a7-6ff2-4b29-8a54-c8d51c1d33c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358118833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.3358118833
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3601415322
Short name T949
Test name
Test status
Simulation time 538214421 ps
CPU time 3.54 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200632 kb
Host smart-05b676c7-1be1-4839-917e-9703d8fd4de1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601415322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.3601415322
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1030541080
Short name T935
Test name
Test status
Simulation time 25688618 ps
CPU time 0.92 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 200468 kb
Host smart-fab5affe-9e49-4e5b-87ac-0581d4896769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030541080 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1030541080
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.2783047955
Short name T113
Test name
Test status
Simulation time 23919605 ps
CPU time 0.84 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200360 kb
Host smart-b59b4bac-15fb-46c6-ac0c-b199f1a68458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783047955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.2783047955
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2415502548
Short name T942
Test name
Test status
Simulation time 21035690 ps
CPU time 0.68 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 198400 kb
Host smart-182d39c5-41be-4c72-ab73-c5b07a868436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415502548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.2415502548
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.947876230
Short name T940
Test name
Test status
Simulation time 57073176 ps
CPU time 1.52 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 200516 kb
Host smart-52cd1f8c-6fce-4b7d-8217-fb0e37083a31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947876230 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.clkmgr_same_csr_outstanding.947876230
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.4234950268
Short name T908
Test name
Test status
Simulation time 133983493 ps
CPU time 1.98 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200864 kb
Host smart-60388650-2a7b-4782-8ff8-d6780ef4a664
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234950268 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.4234950268
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3981766885
Short name T82
Test name
Test status
Simulation time 263799591 ps
CPU time 2.3 seconds
Started Aug 02 07:20:50 PM PDT 24
Finished Aug 02 07:20:52 PM PDT 24
Peak memory 209012 kb
Host smart-d8660ee7-214b-4fb0-985a-6ae39e169b5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981766885 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3981766885
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2096973058
Short name T969
Test name
Test status
Simulation time 60129076 ps
CPU time 1.86 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200560 kb
Host smart-a0b77bd3-0556-4a64-a7be-2d0e7040e509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096973058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.2096973058
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1802227
Short name T957
Test name
Test status
Simulation time 410215201 ps
CPU time 2.52 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200620 kb
Host smart-86b2de88-1489-4de4-aef4-09453dc6de34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 7.clkmgr_tl_intg_err.1802227
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2830261428
Short name T828
Test name
Test status
Simulation time 49920651 ps
CPU time 1.05 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200496 kb
Host smart-e7230ee0-1116-4c55-80fd-1abc8f7268d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830261428 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.2830261428
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1668733044
Short name T905
Test name
Test status
Simulation time 94120111 ps
CPU time 0.87 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 200320 kb
Host smart-6e78a3a4-d088-4c17-a356-d01b588a230d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668733044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.1668733044
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1776726954
Short name T891
Test name
Test status
Simulation time 39463569 ps
CPU time 0.75 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 199036 kb
Host smart-19e1815f-c283-4d4c-a802-eb2124c0bff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776726954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.1776726954
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1539846297
Short name T894
Test name
Test status
Simulation time 61345644 ps
CPU time 1.51 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200548 kb
Host smart-44c8b299-5890-4afe-a4ef-36b198c56f5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539846297 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.1539846297
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1960194064
Short name T150
Test name
Test status
Simulation time 269819291 ps
CPU time 2.36 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 209032 kb
Host smart-2285e078-c24d-4968-8a75-a285ebd73085
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960194064 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.1960194064
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3702388492
Short name T144
Test name
Test status
Simulation time 108314493 ps
CPU time 2.58 seconds
Started Aug 02 07:20:54 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 217344 kb
Host smart-59ff677b-6d2e-4704-bb03-e1f897f5eea6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702388492 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3702388492
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.4232610172
Short name T858
Test name
Test status
Simulation time 732501106 ps
CPU time 4.74 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200572 kb
Host smart-4e5bd3aa-3be1-4a64-94fa-d1428710119f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232610172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.4232610172
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1680573835
Short name T132
Test name
Test status
Simulation time 490312720 ps
CPU time 3.47 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200576 kb
Host smart-f1c34066-5984-4e44-9140-79f6c7db4e9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680573835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.1680573835
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3570829107
Short name T850
Test name
Test status
Simulation time 32843460 ps
CPU time 1.06 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200552 kb
Host smart-1b3b6b5c-b310-40ff-9c93-ecbc2e0583fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570829107 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.3570829107
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.1391708124
Short name T897
Test name
Test status
Simulation time 17356387 ps
CPU time 0.79 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:54 PM PDT 24
Peak memory 200396 kb
Host smart-a7b8f48f-4ffe-4a40-b488-79a3947ce635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391708124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.1391708124
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3045248380
Short name T847
Test name
Test status
Simulation time 28495089 ps
CPU time 0.67 seconds
Started Aug 02 07:20:52 PM PDT 24
Finished Aug 02 07:20:53 PM PDT 24
Peak memory 198956 kb
Host smart-76be4d34-c949-4f3e-af33-253fa201d837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045248380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.3045248380
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.4038156381
Short name T108
Test name
Test status
Simulation time 152775364 ps
CPU time 1.63 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200604 kb
Host smart-fb4448dd-9b63-494c-ad15-e435161952f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038156381 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.4038156381
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.58948868
Short name T75
Test name
Test status
Simulation time 121473744 ps
CPU time 1.43 seconds
Started Aug 02 07:20:55 PM PDT 24
Finished Aug 02 07:20:56 PM PDT 24
Peak memory 200688 kb
Host smart-e8f57968-6fb8-49af-ab9c-411ec31791e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58948868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.clkmgr_shadow_reg_errors.58948868
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2858866272
Short name T149
Test name
Test status
Simulation time 270204729 ps
CPU time 2.13 seconds
Started Aug 02 07:20:56 PM PDT 24
Finished Aug 02 07:20:58 PM PDT 24
Peak memory 200916 kb
Host smart-c61c57cb-62df-4aec-9258-1b9ca1cbeb8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858866272 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.2858866272
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3046504861
Short name T846
Test name
Test status
Simulation time 512177515 ps
CPU time 4.54 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:57 PM PDT 24
Peak memory 200568 kb
Host smart-8d6290db-d471-4487-91aa-bf1f0e7cc2d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046504861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.3046504861
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1804420831
Short name T135
Test name
Test status
Simulation time 114532845 ps
CPU time 1.64 seconds
Started Aug 02 07:20:53 PM PDT 24
Finished Aug 02 07:20:55 PM PDT 24
Peak memory 200544 kb
Host smart-e74d58bb-95d1-491b-b3bb-98e17766e628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804420831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.1804420831
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.29559652
Short name T722
Test name
Test status
Simulation time 103788174 ps
CPU time 1.04 seconds
Started Aug 02 07:22:02 PM PDT 24
Finished Aug 02 07:22:04 PM PDT 24
Peak memory 201072 kb
Host smart-8195ced8-dd33-4397-b4fc-eabe293e5bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29559652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr
_alert_test.29559652
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.135717614
Short name T274
Test name
Test status
Simulation time 15531435 ps
CPU time 0.76 seconds
Started Aug 02 07:22:01 PM PDT 24
Finished Aug 02 07:22:02 PM PDT 24
Peak memory 201060 kb
Host smart-50a394d8-5f16-4505-a138-5927fb9f5861
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135717614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.135717614
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.1233687744
Short name T502
Test name
Test status
Simulation time 30309923 ps
CPU time 0.78 seconds
Started Aug 02 07:21:56 PM PDT 24
Finished Aug 02 07:21:57 PM PDT 24
Peak memory 200296 kb
Host smart-8ec6229f-6f5f-471c-b1ab-127c56106175
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233687744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1233687744
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.1178780311
Short name T749
Test name
Test status
Simulation time 71269866 ps
CPU time 1.01 seconds
Started Aug 02 07:22:04 PM PDT 24
Finished Aug 02 07:22:05 PM PDT 24
Peak memory 201132 kb
Host smart-8b5bcbdb-31d0-4323-a8c7-f15907cb4264
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178780311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.1178780311
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.1064951323
Short name T716
Test name
Test status
Simulation time 44844636 ps
CPU time 0.91 seconds
Started Aug 02 07:21:58 PM PDT 24
Finished Aug 02 07:21:59 PM PDT 24
Peak memory 201124 kb
Host smart-ac0ed036-4412-47b8-bf01-711e15f5e1a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064951323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.1064951323
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.532818764
Short name T505
Test name
Test status
Simulation time 444735474 ps
CPU time 3.13 seconds
Started Aug 02 07:21:58 PM PDT 24
Finished Aug 02 07:22:01 PM PDT 24
Peak memory 201216 kb
Host smart-86192445-58c6-4abd-9887-1348ce8997bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532818764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.532818764
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.2444535449
Short name T561
Test name
Test status
Simulation time 2064347204 ps
CPU time 10.03 seconds
Started Aug 02 07:22:01 PM PDT 24
Finished Aug 02 07:22:11 PM PDT 24
Peak memory 201268 kb
Host smart-a9fa0323-6cf8-41ea-8fa7-db7ad999aeea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444535449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.2444535449
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.591751808
Short name T601
Test name
Test status
Simulation time 82320299 ps
CPU time 0.99 seconds
Started Aug 02 07:22:00 PM PDT 24
Finished Aug 02 07:22:01 PM PDT 24
Peak memory 201128 kb
Host smart-7295ca80-62e6-4c49-87eb-145b007c29f5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591751808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_idle_intersig_mubi.591751808
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2828572110
Short name T597
Test name
Test status
Simulation time 32613273 ps
CPU time 0.83 seconds
Started Aug 02 07:21:59 PM PDT 24
Finished Aug 02 07:22:00 PM PDT 24
Peak memory 201136 kb
Host smart-c10540fe-2eae-4977-865f-fc275c5b2806
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828572110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.2828572110
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.459644268
Short name T485
Test name
Test status
Simulation time 16921873 ps
CPU time 0.78 seconds
Started Aug 02 07:21:59 PM PDT 24
Finished Aug 02 07:22:00 PM PDT 24
Peak memory 201052 kb
Host smart-18374a24-5d0e-47aa-8f37-622470463d1c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459644268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.459644268
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.1179278075
Short name T771
Test name
Test status
Simulation time 44522530 ps
CPU time 0.83 seconds
Started Aug 02 07:21:58 PM PDT 24
Finished Aug 02 07:21:59 PM PDT 24
Peak memory 201092 kb
Host smart-1701604c-ec6c-486d-ad58-67d7bf93cfa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179278075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.1179278075
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.2974502830
Short name T577
Test name
Test status
Simulation time 170891323 ps
CPU time 1.27 seconds
Started Aug 02 07:22:04 PM PDT 24
Finished Aug 02 07:22:06 PM PDT 24
Peak memory 201128 kb
Host smart-9392b76f-32be-4e3d-90ac-a968740fbf66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974502830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.2974502830
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.336350008
Short name T598
Test name
Test status
Simulation time 40513425 ps
CPU time 0.93 seconds
Started Aug 02 07:22:00 PM PDT 24
Finished Aug 02 07:22:02 PM PDT 24
Peak memory 201072 kb
Host smart-8a73b789-1d71-4ddb-a7f6-946b1d806079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336350008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.336350008
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.3048576234
Short name T348
Test name
Test status
Simulation time 5626644993 ps
CPU time 30.91 seconds
Started Aug 02 07:22:04 PM PDT 24
Finished Aug 02 07:22:35 PM PDT 24
Peak memory 201540 kb
Host smart-14306c07-5fba-4f57-9817-c40b31ae624f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048576234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.3048576234
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.2941934047
Short name T236
Test name
Test status
Simulation time 23293823 ps
CPU time 0.87 seconds
Started Aug 02 07:21:59 PM PDT 24
Finished Aug 02 07:22:00 PM PDT 24
Peak memory 200996 kb
Host smart-fba4906a-28f1-44a5-9cee-95fd101c7d08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941934047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2941934047
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.3059020599
Short name T293
Test name
Test status
Simulation time 37373172 ps
CPU time 0.79 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:13 PM PDT 24
Peak memory 201160 kb
Host smart-20dd070c-3d5c-4a11-8d51-d3de4273ff3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059020599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.3059020599
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3904407211
Short name T558
Test name
Test status
Simulation time 235083552 ps
CPU time 1.52 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:12 PM PDT 24
Peak memory 201160 kb
Host smart-9092e3fb-78e6-4a92-be06-57e77f3d81b5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904407211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.3904407211
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.385436964
Short name T644
Test name
Test status
Simulation time 157830134 ps
CPU time 1.04 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:12 PM PDT 24
Peak memory 200328 kb
Host smart-b424f40a-09b3-47b8-967e-bc35e05db407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385436964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.385436964
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.896911342
Short name T504
Test name
Test status
Simulation time 37743539 ps
CPU time 0.91 seconds
Started Aug 02 07:22:04 PM PDT 24
Finished Aug 02 07:22:05 PM PDT 24
Peak memory 201180 kb
Host smart-e94e66e4-2fdc-4681-a9f7-cc834a1dbf5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896911342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.896911342
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.448744087
Short name T357
Test name
Test status
Simulation time 1776989587 ps
CPU time 8.22 seconds
Started Aug 02 07:22:02 PM PDT 24
Finished Aug 02 07:22:10 PM PDT 24
Peak memory 201132 kb
Host smart-10cc0925-266b-4fec-bf60-d050ad78f7e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448744087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.448744087
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.37539481
Short name T682
Test name
Test status
Simulation time 860859576 ps
CPU time 6.48 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:18 PM PDT 24
Peak memory 201228 kb
Host smart-51dc7941-ed13-40b4-93af-b16371f1b0d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37539481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_time
out.37539481
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.350187828
Short name T536
Test name
Test status
Simulation time 36739461 ps
CPU time 0.89 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:12 PM PDT 24
Peak memory 201136 kb
Host smart-f21f0e0e-8dd7-4510-a75c-dd8874e205ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350187828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.clkmgr_idle_intersig_mubi.350187828
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2180360312
Short name T398
Test name
Test status
Simulation time 27589908 ps
CPU time 0.75 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201124 kb
Host smart-4836d631-7451-45a2-876f-52f0cb87c9dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180360312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.2180360312
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.1534461954
Short name T71
Test name
Test status
Simulation time 50611524 ps
CPU time 0.86 seconds
Started Aug 02 07:22:12 PM PDT 24
Finished Aug 02 07:22:13 PM PDT 24
Peak memory 201136 kb
Host smart-ed8e3f56-cc7b-4e4a-a5cb-3b1e4f0814ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534461954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.1534461954
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.2086227711
Short name T291
Test name
Test status
Simulation time 40383650 ps
CPU time 0.81 seconds
Started Aug 02 07:22:10 PM PDT 24
Finished Aug 02 07:22:11 PM PDT 24
Peak memory 201128 kb
Host smart-127245d7-0804-46af-a0b8-fd1f1fc777bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086227711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2086227711
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.3881654666
Short name T162
Test name
Test status
Simulation time 175533308 ps
CPU time 1.66 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:12 PM PDT 24
Peak memory 201136 kb
Host smart-df13c8e0-032d-42bd-bb33-3186732c5a84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881654666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3881654666
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.3432617179
Short name T743
Test name
Test status
Simulation time 284954688 ps
CPU time 1.61 seconds
Started Aug 02 07:22:04 PM PDT 24
Finished Aug 02 07:22:06 PM PDT 24
Peak memory 201132 kb
Host smart-f339056b-be28-4368-bf0c-3ed294855a35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432617179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.3432617179
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.3709608930
Short name T580
Test name
Test status
Simulation time 5916887529 ps
CPU time 42.22 seconds
Started Aug 02 07:22:10 PM PDT 24
Finished Aug 02 07:22:52 PM PDT 24
Peak memory 201544 kb
Host smart-fd86f955-1fb5-4bfc-995d-c0329a21aad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709608930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.3709608930
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.2972092003
Short name T472
Test name
Test status
Simulation time 24193135 ps
CPU time 0.84 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201040 kb
Host smart-a2f7649f-5ff0-4216-8890-2a928514746e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972092003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2972092003
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.4024858846
Short name T754
Test name
Test status
Simulation time 12145370 ps
CPU time 0.74 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201212 kb
Host smart-1ce3aebb-56af-4cc7-9c4f-1c933849300d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024858846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.4024858846
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2007658857
Short name T585
Test name
Test status
Simulation time 17221266 ps
CPU time 0.79 seconds
Started Aug 02 07:23:04 PM PDT 24
Finished Aug 02 07:23:05 PM PDT 24
Peak memory 201108 kb
Host smart-c8bb1f42-18f6-4f9a-b194-64370131bb6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007658857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.2007658857
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.917022132
Short name T592
Test name
Test status
Simulation time 18448110 ps
CPU time 0.75 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 200336 kb
Host smart-37a6d9bb-0f33-4e43-858c-fd64e16a75a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917022132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.917022132
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.3470146770
Short name T522
Test name
Test status
Simulation time 27220242 ps
CPU time 0.84 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:01 PM PDT 24
Peak memory 201140 kb
Host smart-ce358270-6a03-4e23-8d24-d079cd5b3878
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470146770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.3470146770
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.1393629585
Short name T579
Test name
Test status
Simulation time 23523509 ps
CPU time 0.74 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:00 PM PDT 24
Peak memory 201076 kb
Host smart-d94eb197-059c-47ba-adb7-d8b0881ae305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393629585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1393629585
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.1541482036
Short name T441
Test name
Test status
Simulation time 222850716 ps
CPU time 1.7 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201180 kb
Host smart-9c2356c9-249a-47aa-a8c2-ba5815bb96ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541482036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1541482036
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.1230478849
Short name T523
Test name
Test status
Simulation time 2058262583 ps
CPU time 14.58 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:14 PM PDT 24
Peak memory 201448 kb
Host smart-e3a86f45-6ee5-44bc-8af3-21ad1e6acab0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230478849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.1230478849
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.2350172160
Short name T452
Test name
Test status
Simulation time 61326279 ps
CPU time 0.99 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:00 PM PDT 24
Peak memory 201068 kb
Host smart-5f7e822a-761a-458a-afc9-c526bcb9bd84
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350172160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.2350172160
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.3316047128
Short name T225
Test name
Test status
Simulation time 25618522 ps
CPU time 0.77 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:01 PM PDT 24
Peak memory 201156 kb
Host smart-d62ad163-5a7f-4d18-8b4f-43be43d0aa98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316047128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.3316047128
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.7732081
Short name T593
Test name
Test status
Simulation time 18892736 ps
CPU time 0.83 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201124 kb
Host smart-c4689545-921c-4115-8828-19eab132e600
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7732081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_lc_ctrl_intersig_mubi.7732081
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.4137970629
Short name T25
Test name
Test status
Simulation time 58275909 ps
CPU time 0.93 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201096 kb
Host smart-3945e3a7-333d-4e2a-b60a-2f2080e29dba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137970629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.4137970629
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.2273663637
Short name T228
Test name
Test status
Simulation time 1348301548 ps
CPU time 7.11 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:09 PM PDT 24
Peak memory 201296 kb
Host smart-07b3b14e-6dc9-4ae9-99bc-47c95b8b9db3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273663637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2273663637
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.163880724
Short name T630
Test name
Test status
Simulation time 38977381 ps
CPU time 0.92 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201120 kb
Host smart-a96de726-470e-4ddc-8ed1-acfb0ea5bcc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163880724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.163880724
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.1965168270
Short name T320
Test name
Test status
Simulation time 510794050 ps
CPU time 4.29 seconds
Started Aug 02 07:22:54 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201304 kb
Host smart-4d8f317a-5c3d-49f5-b5c3-aa69f4152a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965168270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.1965168270
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.861780831
Short name T733
Test name
Test status
Simulation time 27366497 ps
CPU time 0.94 seconds
Started Aug 02 07:22:57 PM PDT 24
Finished Aug 02 07:22:58 PM PDT 24
Peak memory 201060 kb
Host smart-e884fa41-7eac-4398-9e6a-f30903f32bed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861780831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.861780831
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.1481801838
Short name T254
Test name
Test status
Simulation time 211814512 ps
CPU time 1.43 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201120 kb
Host smart-f6fbf9fd-f4d0-4783-8f6a-534cdc0f20cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481801838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.1481801838
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1751391388
Short name T400
Test name
Test status
Simulation time 70401324 ps
CPU time 1.04 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201196 kb
Host smart-e6f0440a-c176-4168-b68e-2a81e70003e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751391388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.1751391388
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.444375051
Short name T33
Test name
Test status
Simulation time 24968035 ps
CPU time 0.77 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201140 kb
Host smart-4a12ab20-4ec0-41b3-a0e3-8a4b9e631b12
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444375051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.clkmgr_div_intersig_mubi.444375051
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.2819984904
Short name T382
Test name
Test status
Simulation time 19427486 ps
CPU time 0.79 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:00 PM PDT 24
Peak memory 201016 kb
Host smart-dd9d28b7-91be-435a-a81c-43009b2aaa2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819984904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2819984904
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.4000404239
Short name T19
Test name
Test status
Simulation time 683882566 ps
CPU time 4.47 seconds
Started Aug 02 07:22:57 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201132 kb
Host smart-90893f4d-5c83-4fb3-94d5-98335d4ce7dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000404239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.4000404239
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.1500736728
Short name T667
Test name
Test status
Simulation time 1652704327 ps
CPU time 6.72 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:07 PM PDT 24
Peak memory 201228 kb
Host smart-9c7d2f17-dd21-4221-b938-49796e2da059
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500736728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.1500736728
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2574266617
Short name T564
Test name
Test status
Simulation time 59218459 ps
CPU time 1.07 seconds
Started Aug 02 07:23:04 PM PDT 24
Finished Aug 02 07:23:05 PM PDT 24
Peak memory 201144 kb
Host smart-b52f870b-48fe-4027-b654-15c00a2dc20e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574266617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.2574266617
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.603077648
Short name T627
Test name
Test status
Simulation time 101881567 ps
CPU time 1.06 seconds
Started Aug 02 07:23:04 PM PDT 24
Finished Aug 02 07:23:05 PM PDT 24
Peak memory 201128 kb
Host smart-de09c4da-6ef7-4cfb-861c-bc284fc3c46c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603077648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.clkmgr_lc_clk_byp_req_intersig_mubi.603077648
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1315636367
Short name T776
Test name
Test status
Simulation time 44689788 ps
CPU time 0.86 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201092 kb
Host smart-9f7099d6-f0a4-4e85-879a-209150ebed58
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315636367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.1315636367
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.4198637660
Short name T290
Test name
Test status
Simulation time 19123956 ps
CPU time 0.73 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:01 PM PDT 24
Peak memory 201072 kb
Host smart-74ff2ee8-f023-43a9-9897-0c469eecef56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198637660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.4198637660
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.2673562984
Short name T500
Test name
Test status
Simulation time 885832467 ps
CPU time 5.17 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:07 PM PDT 24
Peak memory 201360 kb
Host smart-de9ffa46-a36c-4cbb-93c9-c2eb7e4771fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673562984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.2673562984
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.1572964586
Short name T363
Test name
Test status
Simulation time 71106596 ps
CPU time 0.99 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201068 kb
Host smart-a75091fc-ed2b-456b-9a35-ce2088c111a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572964586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.1572964586
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.1094728263
Short name T569
Test name
Test status
Simulation time 7951510908 ps
CPU time 29.43 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:32 PM PDT 24
Peak memory 201544 kb
Host smart-a52d7923-71eb-426e-a055-b1db2c2d18f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094728263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.1094728263
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.2785732064
Short name T639
Test name
Test status
Simulation time 42247513 ps
CPU time 0.91 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:01 PM PDT 24
Peak memory 201136 kb
Host smart-f9dd41e8-d6b8-4bbd-8081-2f8cd4f3a387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785732064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.2785732064
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.3946833786
Short name T280
Test name
Test status
Simulation time 69065368 ps
CPU time 0.98 seconds
Started Aug 02 07:23:04 PM PDT 24
Finished Aug 02 07:23:05 PM PDT 24
Peak memory 201100 kb
Host smart-414ced1b-142b-42b5-a874-d2e6d336afb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946833786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.3946833786
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3960232602
Short name T477
Test name
Test status
Simulation time 47668505 ps
CPU time 0.84 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201144 kb
Host smart-ac906711-df17-4a07-8ec4-884634a2ee4a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960232602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3960232602
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.1055087474
Short name T711
Test name
Test status
Simulation time 15094771 ps
CPU time 0.73 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 200324 kb
Host smart-a0e21f54-4e6c-49d8-8485-621c21141ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055087474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.1055087474
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.2384383037
Short name T679
Test name
Test status
Simulation time 123896165 ps
CPU time 1.21 seconds
Started Aug 02 07:23:04 PM PDT 24
Finished Aug 02 07:23:06 PM PDT 24
Peak memory 201108 kb
Host smart-a9ccb8ad-6b68-4a6e-8518-9cbd9c94eff3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384383037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.2384383037
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.2191768320
Short name T70
Test name
Test status
Simulation time 62559491 ps
CPU time 0.87 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201072 kb
Host smart-97f179d6-c74d-4778-a125-764a53c87f55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191768320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.2191768320
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.2307520819
Short name T34
Test name
Test status
Simulation time 861561156 ps
CPU time 4.17 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:07 PM PDT 24
Peak memory 201200 kb
Host smart-c2c144f0-c638-4266-a7ca-fb48d9531636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307520819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.2307520819
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.2566511245
Short name T371
Test name
Test status
Simulation time 260552551 ps
CPU time 2.64 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:05 PM PDT 24
Peak memory 201260 kb
Host smart-643a21a6-50f1-470b-8c02-2c16e7a0a88a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566511245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.2566511245
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.1818756879
Short name T631
Test name
Test status
Simulation time 16096792 ps
CPU time 0.73 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201100 kb
Host smart-eb76b288-7586-45fb-8990-5e5d11e93c2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818756879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.1818756879
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1798484888
Short name T675
Test name
Test status
Simulation time 46127896 ps
CPU time 0.94 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201112 kb
Host smart-df8b04b6-f43f-4484-a31a-5cc8647dd2d6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798484888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.1798484888
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2193676874
Short name T497
Test name
Test status
Simulation time 28584084 ps
CPU time 0.98 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201132 kb
Host smart-2dde4c9e-42bf-4319-b852-2cb4af8f1cb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193676874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.2193676874
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.4046858765
Short name T328
Test name
Test status
Simulation time 14943670 ps
CPU time 0.83 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201104 kb
Host smart-64d94aab-a1c5-41ec-a8fe-7c03941faa3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046858765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.4046858765
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.3884719989
Short name T267
Test name
Test status
Simulation time 423211999 ps
CPU time 1.97 seconds
Started Aug 02 07:22:56 PM PDT 24
Finished Aug 02 07:22:58 PM PDT 24
Peak memory 201100 kb
Host smart-ed973015-389d-432c-9e91-ae5e5128c051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884719989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3884719989
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.3612644321
Short name T26
Test name
Test status
Simulation time 104860791 ps
CPU time 1.17 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:00 PM PDT 24
Peak memory 201048 kb
Host smart-672e391d-ed04-48ba-966b-5f695fe4584e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612644321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.3612644321
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.863988433
Short name T406
Test name
Test status
Simulation time 4035747646 ps
CPU time 25.25 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:25 PM PDT 24
Peak memory 201400 kb
Host smart-0eef1d83-b27a-4f7d-8978-dc4031a252e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863988433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.863988433
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.3770826649
Short name T238
Test name
Test status
Simulation time 81544206 ps
CPU time 0.99 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201096 kb
Host smart-d77062ee-3fa0-404a-92b3-b5c7574a8eb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770826649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.3770826649
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.2233913812
Short name T774
Test name
Test status
Simulation time 50541218 ps
CPU time 0.9 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201148 kb
Host smart-1415196d-2e3f-4035-bf9a-265e431db3e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233913812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.2233913812
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.3617928190
Short name T755
Test name
Test status
Simulation time 18280490 ps
CPU time 0.81 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201116 kb
Host smart-0023043d-2954-41e3-9918-6c6c9ec442ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617928190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.3617928190
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.4037409224
Short name T338
Test name
Test status
Simulation time 37085608 ps
CPU time 0.76 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201044 kb
Host smart-1d0c0f58-319f-45e8-9694-190f418a2139
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037409224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.4037409224
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.2977844154
Short name T299
Test name
Test status
Simulation time 116884311 ps
CPU time 0.99 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:01 PM PDT 24
Peak memory 201072 kb
Host smart-f3782f83-b3d2-4b4c-832c-46bd1427776e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977844154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.2977844154
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.3784921723
Short name T652
Test name
Test status
Simulation time 78467614 ps
CPU time 1.02 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201104 kb
Host smart-edb8469d-6748-425a-80f9-64b38e65cb6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784921723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.3784921723
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.3880925785
Short name T3
Test name
Test status
Simulation time 1608855474 ps
CPU time 6.35 seconds
Started Aug 02 07:23:04 PM PDT 24
Finished Aug 02 07:23:11 PM PDT 24
Peak memory 201184 kb
Host smart-13791685-d270-4293-bd97-abcae54f9448
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880925785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3880925785
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.3739404686
Short name T534
Test name
Test status
Simulation time 381792675 ps
CPU time 3.35 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201308 kb
Host smart-fab89ef8-0a49-4dcc-82e9-6ba432c018ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739404686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.3739404686
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.1656521581
Short name T803
Test name
Test status
Simulation time 15026306 ps
CPU time 0.75 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201084 kb
Host smart-57e25185-c54d-496f-aa1e-9d5485857e41
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656521581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.1656521581
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.3160023575
Short name T305
Test name
Test status
Simulation time 19705453 ps
CPU time 0.81 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201080 kb
Host smart-c6366e84-cf26-447b-8734-159cbf4e9104
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160023575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.3160023575
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.2480016577
Short name T775
Test name
Test status
Simulation time 21086021 ps
CPU time 0.87 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:01 PM PDT 24
Peak memory 201088 kb
Host smart-15f58055-e88d-441a-84e8-5667bfc9ed99
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480016577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.2480016577
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.2369969085
Short name T671
Test name
Test status
Simulation time 19476008 ps
CPU time 0.76 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201044 kb
Host smart-358f607a-79d3-41f3-8500-9f155fbaab50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369969085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.2369969085
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.1671561539
Short name T198
Test name
Test status
Simulation time 1150240024 ps
CPU time 6.74 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:10 PM PDT 24
Peak memory 201400 kb
Host smart-c7b050d6-5ddb-47b1-a0d4-876683fa9ad9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671561539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1671561539
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.3628362435
Short name T427
Test name
Test status
Simulation time 38599440 ps
CPU time 0.86 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:00 PM PDT 24
Peak memory 201096 kb
Host smart-f15af56e-d84e-4c7c-8ef9-4704ad3f842d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628362435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.3628362435
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.497449810
Short name T533
Test name
Test status
Simulation time 9868322334 ps
CPU time 40.6 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:41 PM PDT 24
Peak memory 201460 kb
Host smart-6535923a-0a51-4007-bb29-b2bea0e18b66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497449810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.497449810
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.2296673196
Short name T468
Test name
Test status
Simulation time 30065893 ps
CPU time 0.94 seconds
Started Aug 02 07:22:55 PM PDT 24
Finished Aug 02 07:22:56 PM PDT 24
Peak memory 201092 kb
Host smart-40be1391-4881-4188-9c9f-1cc5d139c444
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296673196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2296673196
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.3169466881
Short name T319
Test name
Test status
Simulation time 43263008 ps
CPU time 0.9 seconds
Started Aug 02 07:23:17 PM PDT 24
Finished Aug 02 07:23:18 PM PDT 24
Peak memory 201160 kb
Host smart-bfc9b729-b1d4-4bee-a55f-255c3369fda2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169466881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.3169466881
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2353026168
Short name T389
Test name
Test status
Simulation time 40536781 ps
CPU time 0.85 seconds
Started Aug 02 07:23:16 PM PDT 24
Finished Aug 02 07:23:17 PM PDT 24
Peak memory 201160 kb
Host smart-a55e1981-0dba-4264-8313-8a668bb08e38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353026168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.2353026168
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.4050967469
Short name T171
Test name
Test status
Simulation time 13261516 ps
CPU time 0.7 seconds
Started Aug 02 07:23:07 PM PDT 24
Finished Aug 02 07:23:09 PM PDT 24
Peak memory 200296 kb
Host smart-475b8a60-d463-4750-a2f1-4f46ae09bafb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050967469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.4050967469
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.3898982092
Short name T813
Test name
Test status
Simulation time 59994149 ps
CPU time 0.97 seconds
Started Aug 02 07:23:14 PM PDT 24
Finished Aug 02 07:23:15 PM PDT 24
Peak memory 201128 kb
Host smart-2d2f9840-c7e5-4d76-99cb-91113dfd2ed2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898982092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.3898982092
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.2130482859
Short name T483
Test name
Test status
Simulation time 24055479 ps
CPU time 0.87 seconds
Started Aug 02 07:23:12 PM PDT 24
Finished Aug 02 07:23:13 PM PDT 24
Peak memory 201060 kb
Host smart-6cdeeedf-ced3-4540-90b1-ebb77cf09b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130482859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.2130482859
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.1328175963
Short name T746
Test name
Test status
Simulation time 798281251 ps
CPU time 6.31 seconds
Started Aug 02 07:23:13 PM PDT 24
Finished Aug 02 07:23:20 PM PDT 24
Peak memory 201188 kb
Host smart-47d3b35c-1671-4e7f-8fa2-ecb92c83a240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328175963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.1328175963
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.195216215
Short name T511
Test name
Test status
Simulation time 3050300701 ps
CPU time 9.92 seconds
Started Aug 02 07:23:12 PM PDT 24
Finished Aug 02 07:23:22 PM PDT 24
Peak memory 201444 kb
Host smart-05c99d24-b8d1-4d80-9a88-de68559fa9aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195216215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_ti
meout.195216215
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.1629903188
Short name T278
Test name
Test status
Simulation time 37558407 ps
CPU time 1 seconds
Started Aug 02 07:23:12 PM PDT 24
Finished Aug 02 07:23:13 PM PDT 24
Peak memory 201032 kb
Host smart-0840937f-2209-466e-83bd-98f48b62538c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629903188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.1629903188
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.95829676
Short name T352
Test name
Test status
Simulation time 22044174 ps
CPU time 0.85 seconds
Started Aug 02 07:23:13 PM PDT 24
Finished Aug 02 07:23:14 PM PDT 24
Peak memory 201092 kb
Host smart-5c7ed3e1-e030-4fd0-b1af-db46ad75305d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95829676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_lc_clk_byp_req_intersig_mubi.95829676
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.1605979980
Short name T647
Test name
Test status
Simulation time 58870050 ps
CPU time 0.96 seconds
Started Aug 02 07:23:07 PM PDT 24
Finished Aug 02 07:23:08 PM PDT 24
Peak memory 201100 kb
Host smart-05b91578-b96c-455a-9ac5-a6d63fc8854b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605979980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.1605979980
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.108797284
Short name T256
Test name
Test status
Simulation time 29814233 ps
CPU time 0.77 seconds
Started Aug 02 07:23:14 PM PDT 24
Finished Aug 02 07:23:15 PM PDT 24
Peak memory 201096 kb
Host smart-6822c0f1-685b-452e-bca4-0f8d0c9660c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108797284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.108797284
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.3205646363
Short name T40
Test name
Test status
Simulation time 311925228 ps
CPU time 2.3 seconds
Started Aug 02 07:23:13 PM PDT 24
Finished Aug 02 07:23:16 PM PDT 24
Peak memory 201156 kb
Host smart-fa251822-b607-43f0-9c90-38850546ba8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205646363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3205646363
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.629720159
Short name T141
Test name
Test status
Simulation time 45727337 ps
CPU time 0.91 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201092 kb
Host smart-3d59793a-27b3-498a-81b5-da461ec3c6e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629720159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.629720159
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.2819250692
Short name T797
Test name
Test status
Simulation time 8053432286 ps
CPU time 33.66 seconds
Started Aug 02 07:23:13 PM PDT 24
Finished Aug 02 07:23:47 PM PDT 24
Peak memory 201516 kb
Host smart-bad6e6be-1dc0-4ea3-bb9b-e1eae94a4070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819250692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.2819250692
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.1877143121
Short name T276
Test name
Test status
Simulation time 24703814 ps
CPU time 0.93 seconds
Started Aug 02 07:23:14 PM PDT 24
Finished Aug 02 07:23:16 PM PDT 24
Peak memory 201112 kb
Host smart-0f7037c3-b77d-4dc1-997a-8fd17ff6b87e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877143121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.1877143121
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.2821623417
Short name T730
Test name
Test status
Simulation time 19133292 ps
CPU time 0.82 seconds
Started Aug 02 07:23:09 PM PDT 24
Finished Aug 02 07:23:10 PM PDT 24
Peak memory 201116 kb
Host smart-b7c67493-8f15-4e48-955b-a4d75bf7fdf6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821623417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.2821623417
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.3961345445
Short name T715
Test name
Test status
Simulation time 18174846 ps
CPU time 0.73 seconds
Started Aug 02 07:23:16 PM PDT 24
Finished Aug 02 07:23:17 PM PDT 24
Peak memory 200332 kb
Host smart-6686aa58-eb2a-4874-8300-3691985a56d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961345445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3961345445
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.140565821
Short name T587
Test name
Test status
Simulation time 14030322 ps
CPU time 0.84 seconds
Started Aug 02 07:23:14 PM PDT 24
Finished Aug 02 07:23:15 PM PDT 24
Peak memory 201132 kb
Host smart-c2f4b4e8-d315-4e98-8ef3-c34c3757f8ce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140565821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_div_intersig_mubi.140565821
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.2760639531
Short name T94
Test name
Test status
Simulation time 17272943 ps
CPU time 0.74 seconds
Started Aug 02 07:23:07 PM PDT 24
Finished Aug 02 07:23:08 PM PDT 24
Peak memory 201116 kb
Host smart-d7bc1580-962f-4174-abcc-5c017d147e5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760639531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.2760639531
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.1767026980
Short name T345
Test name
Test status
Simulation time 1997844254 ps
CPU time 8.52 seconds
Started Aug 02 07:23:13 PM PDT 24
Finished Aug 02 07:23:22 PM PDT 24
Peak memory 201396 kb
Host smart-386aa17a-bbad-4638-a77d-5ff23405a25c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767026980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1767026980
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.2467113994
Short name T244
Test name
Test status
Simulation time 2293180114 ps
CPU time 17.14 seconds
Started Aug 02 07:23:07 PM PDT 24
Finished Aug 02 07:23:25 PM PDT 24
Peak memory 201540 kb
Host smart-84027e30-8894-47a2-a0b0-a3ce80aa6b12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467113994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.2467113994
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1506047044
Short name T678
Test name
Test status
Simulation time 134256632 ps
CPU time 1.29 seconds
Started Aug 02 07:23:07 PM PDT 24
Finished Aug 02 07:23:08 PM PDT 24
Peak memory 201076 kb
Host smart-78d382ba-3d7d-41b0-93e6-46b8981d3fc5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506047044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.1506047044
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2940484678
Short name T283
Test name
Test status
Simulation time 16152274 ps
CPU time 0.74 seconds
Started Aug 02 07:23:13 PM PDT 24
Finished Aug 02 07:23:14 PM PDT 24
Peak memory 201068 kb
Host smart-dfa18415-e3e8-43d5-b745-7ec865fecc34
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940484678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.2940484678
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1770301679
Short name T314
Test name
Test status
Simulation time 95705402 ps
CPU time 1.12 seconds
Started Aug 02 07:23:10 PM PDT 24
Finished Aug 02 07:23:12 PM PDT 24
Peak memory 201196 kb
Host smart-032fd135-f9d3-4041-bec3-3435a4fdd7e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770301679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1770301679
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.66616166
Short name T673
Test name
Test status
Simulation time 49905721 ps
CPU time 0.84 seconds
Started Aug 02 07:23:06 PM PDT 24
Finished Aug 02 07:23:07 PM PDT 24
Peak memory 201096 kb
Host smart-8a709570-a6f4-4aaa-b85b-4348ed1c8283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66616166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.66616166
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.3904595969
Short name T161
Test name
Test status
Simulation time 1142702532 ps
CPU time 4.7 seconds
Started Aug 02 07:23:13 PM PDT 24
Finished Aug 02 07:23:18 PM PDT 24
Peak memory 201356 kb
Host smart-4e4879ca-7640-40b4-a256-464302ea8832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904595969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3904595969
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.4208808846
Short name T93
Test name
Test status
Simulation time 23832671 ps
CPU time 0.87 seconds
Started Aug 02 07:23:14 PM PDT 24
Finished Aug 02 07:23:15 PM PDT 24
Peak memory 201048 kb
Host smart-ad32e752-5042-417e-a96e-52beedebf599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208808846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.4208808846
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.1475777154
Short name T85
Test name
Test status
Simulation time 50675750214 ps
CPU time 703.12 seconds
Started Aug 02 07:23:16 PM PDT 24
Finished Aug 02 07:34:59 PM PDT 24
Peak memory 209876 kb
Host smart-d119c97d-ddc0-4bbe-b5b7-071a6c0e9e2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1475777154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.1475777154
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.clkmgr_trans.4284304878
Short name T659
Test name
Test status
Simulation time 77211466 ps
CPU time 1.1 seconds
Started Aug 02 07:23:09 PM PDT 24
Finished Aug 02 07:23:10 PM PDT 24
Peak memory 201236 kb
Host smart-65335fb6-a504-4271-ab97-836026cf6f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284304878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.4284304878
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.7564292
Short name T416
Test name
Test status
Simulation time 12477793 ps
CPU time 0.68 seconds
Started Aug 02 07:23:29 PM PDT 24
Finished Aug 02 07:23:30 PM PDT 24
Peak memory 201056 kb
Host smart-27967e84-9b3d-4239-8635-31845340a7da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7564292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr
_alert_test.7564292
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.4075860673
Short name T196
Test name
Test status
Simulation time 70931355 ps
CPU time 0.95 seconds
Started Aug 02 07:23:18 PM PDT 24
Finished Aug 02 07:23:19 PM PDT 24
Peak memory 201124 kb
Host smart-bbd2c6fd-92ba-488c-ae7c-ac44b85dba89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075860673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.4075860673
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.2516561019
Short name T705
Test name
Test status
Simulation time 101304522 ps
CPU time 0.91 seconds
Started Aug 02 07:23:29 PM PDT 24
Finished Aug 02 07:23:30 PM PDT 24
Peak memory 201016 kb
Host smart-6bbdd043-202f-4b3e-a38c-a39aa8697358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516561019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2516561019
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.874096931
Short name T811
Test name
Test status
Simulation time 84163164 ps
CPU time 1.04 seconds
Started Aug 02 07:23:17 PM PDT 24
Finished Aug 02 07:23:18 PM PDT 24
Peak memory 201184 kb
Host smart-7c5be419-d14e-4b97-8c8e-2b95af405136
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874096931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.clkmgr_div_intersig_mubi.874096931
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.495671241
Short name T301
Test name
Test status
Simulation time 90326394 ps
CPU time 1.02 seconds
Started Aug 02 07:23:08 PM PDT 24
Finished Aug 02 07:23:10 PM PDT 24
Peak memory 201156 kb
Host smart-fd3b1e72-3877-4fec-b447-a2f141e745a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495671241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.495671241
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.1589363765
Short name T407
Test name
Test status
Simulation time 2134002507 ps
CPU time 9.51 seconds
Started Aug 02 07:23:16 PM PDT 24
Finished Aug 02 07:23:26 PM PDT 24
Peak memory 201416 kb
Host smart-f951da6f-c770-4a96-a3ae-2d28deed32cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589363765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1589363765
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.777871504
Short name T820
Test name
Test status
Simulation time 1951689153 ps
CPU time 8.49 seconds
Started Aug 02 07:23:07 PM PDT 24
Finished Aug 02 07:23:16 PM PDT 24
Peak memory 201188 kb
Host smart-6eb0bf9d-63c9-4335-b4d9-f269c3eb40c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777871504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_ti
meout.777871504
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2071117472
Short name T669
Test name
Test status
Simulation time 14456798 ps
CPU time 0.74 seconds
Started Aug 02 07:23:29 PM PDT 24
Finished Aug 02 07:23:30 PM PDT 24
Peak memory 201080 kb
Host smart-05e7a938-8292-444d-a8af-d660c6934d8d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071117472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2071117472
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.542077832
Short name T425
Test name
Test status
Simulation time 50262722 ps
CPU time 0.88 seconds
Started Aug 02 07:23:19 PM PDT 24
Finished Aug 02 07:23:20 PM PDT 24
Peak memory 201132 kb
Host smart-88772a6f-508c-4710-8df2-2aac9bca004f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542077832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.clkmgr_lc_clk_byp_req_intersig_mubi.542077832
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3744216625
Short name T591
Test name
Test status
Simulation time 23074460 ps
CPU time 0.77 seconds
Started Aug 02 07:23:20 PM PDT 24
Finished Aug 02 07:23:21 PM PDT 24
Peak memory 201176 kb
Host smart-06a02640-0205-400d-90d6-9a16a3b1cd87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744216625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.3744216625
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.4211888457
Short name T687
Test name
Test status
Simulation time 16134146 ps
CPU time 0.76 seconds
Started Aug 02 07:23:19 PM PDT 24
Finished Aug 02 07:23:20 PM PDT 24
Peak memory 201072 kb
Host smart-91b8637a-200f-4f60-a105-d05beca4d3ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211888457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.4211888457
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.3644984571
Short name T512
Test name
Test status
Simulation time 449117573 ps
CPU time 3.01 seconds
Started Aug 02 07:23:19 PM PDT 24
Finished Aug 02 07:23:22 PM PDT 24
Peak memory 201200 kb
Host smart-c6c974a5-9c38-4abd-b9de-dfe2714865d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644984571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3644984571
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.2717742518
Short name T27
Test name
Test status
Simulation time 21554003 ps
CPU time 0.83 seconds
Started Aug 02 07:23:09 PM PDT 24
Finished Aug 02 07:23:10 PM PDT 24
Peak memory 201116 kb
Host smart-b52d07b9-8740-4ba2-a637-a1facc6992c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717742518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2717742518
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.535466720
Short name T805
Test name
Test status
Simulation time 3585236734 ps
CPU time 15.13 seconds
Started Aug 02 07:23:28 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201464 kb
Host smart-0d82a813-dad6-4246-b7c1-fd15b14255c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535466720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.535466720
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.2773929655
Short name T740
Test name
Test status
Simulation time 26855401 ps
CPU time 0.91 seconds
Started Aug 02 07:23:16 PM PDT 24
Finished Aug 02 07:23:17 PM PDT 24
Peak memory 201084 kb
Host smart-b82d7130-888e-4094-aeec-d1ee58940709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773929655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.2773929655
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.1687269664
Short name T185
Test name
Test status
Simulation time 53272376 ps
CPU time 0.91 seconds
Started Aug 02 07:23:26 PM PDT 24
Finished Aug 02 07:23:27 PM PDT 24
Peak memory 201104 kb
Host smart-da5f696e-d2c6-4658-a109-ce2ac6a3f573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687269664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.1687269664
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1665734698
Short name T784
Test name
Test status
Simulation time 35265609 ps
CPU time 0.87 seconds
Started Aug 02 07:23:27 PM PDT 24
Finished Aug 02 07:23:28 PM PDT 24
Peak memory 201136 kb
Host smart-9a5ca7d7-551a-4772-82d9-24b0c6f8deeb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665734698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.1665734698
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.3293832943
Short name T702
Test name
Test status
Simulation time 13832596 ps
CPU time 0.69 seconds
Started Aug 02 07:23:29 PM PDT 24
Finished Aug 02 07:23:30 PM PDT 24
Peak memory 200292 kb
Host smart-f5439f4f-addd-42ca-838e-2353887a9f3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293832943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.3293832943
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.162225898
Short name T693
Test name
Test status
Simulation time 28977559 ps
CPU time 0.92 seconds
Started Aug 02 07:23:27 PM PDT 24
Finished Aug 02 07:23:28 PM PDT 24
Peak memory 201132 kb
Host smart-f14edbb7-77f5-48a0-aa3e-51347c9cde71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162225898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.clkmgr_div_intersig_mubi.162225898
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.3208845417
Short name T370
Test name
Test status
Simulation time 22399910 ps
CPU time 0.81 seconds
Started Aug 02 07:23:20 PM PDT 24
Finished Aug 02 07:23:20 PM PDT 24
Peak memory 201076 kb
Host smart-61b1786f-e46b-4f14-8d70-6f1bb7d5b372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208845417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3208845417
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.2292480109
Short name T551
Test name
Test status
Simulation time 1037183935 ps
CPU time 8.36 seconds
Started Aug 02 07:23:19 PM PDT 24
Finished Aug 02 07:23:28 PM PDT 24
Peak memory 201160 kb
Host smart-69e755b7-8a17-40fe-9f38-dcb441fa81d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292480109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.2292480109
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.2303123795
Short name T419
Test name
Test status
Simulation time 1943365525 ps
CPU time 10.24 seconds
Started Aug 02 07:23:28 PM PDT 24
Finished Aug 02 07:23:39 PM PDT 24
Peak memory 201164 kb
Host smart-6db68957-9c25-4a9e-be30-a4c7776c0346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303123795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.2303123795
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2785136412
Short name T786
Test name
Test status
Simulation time 18214957 ps
CPU time 0.78 seconds
Started Aug 02 07:23:17 PM PDT 24
Finished Aug 02 07:23:18 PM PDT 24
Peak memory 201096 kb
Host smart-1745a96c-5c53-4a70-915b-b37d8849d9fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785136412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2785136412
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2817509882
Short name T99
Test name
Test status
Simulation time 39015501 ps
CPU time 0.88 seconds
Started Aug 02 07:23:16 PM PDT 24
Finished Aug 02 07:23:17 PM PDT 24
Peak memory 201060 kb
Host smart-8a366ea4-0680-40aa-b499-e37273b9204a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817509882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.2817509882
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.217897830
Short name T355
Test name
Test status
Simulation time 155086341 ps
CPU time 1.13 seconds
Started Aug 02 07:23:14 PM PDT 24
Finished Aug 02 07:23:16 PM PDT 24
Peak memory 201100 kb
Host smart-bb9f0268-da1c-4906-a45c-825444c3058e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217897830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_ctrl_intersig_mubi.217897830
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.1881371788
Short name T367
Test name
Test status
Simulation time 18118967 ps
CPU time 0.74 seconds
Started Aug 02 07:23:16 PM PDT 24
Finished Aug 02 07:23:17 PM PDT 24
Peak memory 201076 kb
Host smart-0a6a3999-7750-4fb0-a860-be9ec6c163ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881371788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1881371788
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.4065641129
Short name T230
Test name
Test status
Simulation time 1277841324 ps
CPU time 4.97 seconds
Started Aug 02 07:23:26 PM PDT 24
Finished Aug 02 07:23:31 PM PDT 24
Peak memory 201288 kb
Host smart-d86bd57f-5a35-408e-871b-e94bab9224a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065641129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.4065641129
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.1791105236
Short name T184
Test name
Test status
Simulation time 50325493 ps
CPU time 0.89 seconds
Started Aug 02 07:23:36 PM PDT 24
Finished Aug 02 07:23:37 PM PDT 24
Peak memory 201084 kb
Host smart-8dd3a14e-5522-4632-ab87-290a4bf16277
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791105236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1791105236
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.1330529908
Short name T737
Test name
Test status
Simulation time 5186268742 ps
CPU time 32.31 seconds
Started Aug 02 07:23:31 PM PDT 24
Finished Aug 02 07:24:03 PM PDT 24
Peak memory 201448 kb
Host smart-3f9aba45-4cb6-42cd-841e-44716f60fd02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330529908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.1330529908
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.3636370861
Short name T199
Test name
Test status
Simulation time 177170654 ps
CPU time 1.29 seconds
Started Aug 02 07:23:20 PM PDT 24
Finished Aug 02 07:23:21 PM PDT 24
Peak memory 201116 kb
Host smart-1ef06f59-ad5f-45c9-954b-ba7d0c1750a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636370861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.3636370861
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.3403391076
Short name T187
Test name
Test status
Simulation time 52485782 ps
CPU time 0.81 seconds
Started Aug 02 07:23:44 PM PDT 24
Finished Aug 02 07:23:45 PM PDT 24
Peak memory 201084 kb
Host smart-7859a148-f113-4c32-8567-d112b194a3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403391076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.3403391076
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1984648028
Short name T802
Test name
Test status
Simulation time 100473591 ps
CPU time 1.14 seconds
Started Aug 02 07:23:28 PM PDT 24
Finished Aug 02 07:23:29 PM PDT 24
Peak memory 201064 kb
Host smart-21ea710e-d83a-4d72-9ec3-84a0baaf08ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984648028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.1984648028
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.3772668247
Short name T635
Test name
Test status
Simulation time 22593897 ps
CPU time 0.69 seconds
Started Aug 02 07:23:26 PM PDT 24
Finished Aug 02 07:23:27 PM PDT 24
Peak memory 200312 kb
Host smart-1c3b2e25-512c-4c0b-b3fd-4e5f228a844a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772668247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3772668247
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.3463043622
Short name T250
Test name
Test status
Simulation time 33650120 ps
CPU time 0.88 seconds
Started Aug 02 07:23:27 PM PDT 24
Finished Aug 02 07:23:28 PM PDT 24
Peak memory 201128 kb
Host smart-34c7497c-d221-40e2-bbe4-d7abf553d40a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463043622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.3463043622
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.4089493244
Short name T347
Test name
Test status
Simulation time 28219122 ps
CPU time 0.82 seconds
Started Aug 02 07:23:28 PM PDT 24
Finished Aug 02 07:23:29 PM PDT 24
Peak memory 201128 kb
Host smart-f721982e-71d0-4a48-9fbb-b1721027b20c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089493244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.4089493244
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.255765615
Short name T767
Test name
Test status
Simulation time 196004966 ps
CPU time 2.02 seconds
Started Aug 02 07:23:30 PM PDT 24
Finished Aug 02 07:23:32 PM PDT 24
Peak memory 201112 kb
Host smart-a1ad84d8-fe9e-4376-be2f-957a0794bc5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255765615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.255765615
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.3407799841
Short name T409
Test name
Test status
Simulation time 623034611 ps
CPU time 3.58 seconds
Started Aug 02 07:23:27 PM PDT 24
Finished Aug 02 07:23:31 PM PDT 24
Peak memory 201188 kb
Host smart-73d0ee84-326e-4107-b643-7e0bc9669201
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407799841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.3407799841
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.3862729416
Short name T604
Test name
Test status
Simulation time 25535677 ps
CPU time 0.95 seconds
Started Aug 02 07:23:36 PM PDT 24
Finished Aug 02 07:23:37 PM PDT 24
Peak memory 201084 kb
Host smart-f650feca-fead-4ea0-ad07-0d235df85316
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862729416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.3862729416
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.1982319256
Short name T446
Test name
Test status
Simulation time 20773842 ps
CPU time 0.86 seconds
Started Aug 02 07:23:28 PM PDT 24
Finished Aug 02 07:23:29 PM PDT 24
Peak memory 201100 kb
Host smart-5afa2c11-069e-4d88-94ab-ebbd8acd6882
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982319256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.1982319256
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3877301543
Short name T637
Test name
Test status
Simulation time 163440649 ps
CPU time 1.36 seconds
Started Aug 02 07:23:27 PM PDT 24
Finished Aug 02 07:23:29 PM PDT 24
Peak memory 201156 kb
Host smart-1e8d8feb-644b-4c54-90f0-c2b5c5e049a8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877301543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.3877301543
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.656155428
Short name T603
Test name
Test status
Simulation time 44172687 ps
CPU time 0.85 seconds
Started Aug 02 07:23:27 PM PDT 24
Finished Aug 02 07:23:28 PM PDT 24
Peak memory 201236 kb
Host smart-29e15cfe-75d8-4fab-9d70-1b7c48f1ce76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656155428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.656155428
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.705550883
Short name T727
Test name
Test status
Simulation time 990219222 ps
CPU time 5.73 seconds
Started Aug 02 07:23:36 PM PDT 24
Finished Aug 02 07:23:42 PM PDT 24
Peak memory 201288 kb
Host smart-70680e11-9a4b-4cf7-b9bb-d8a805293960
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705550883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.705550883
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.2169787378
Short name T515
Test name
Test status
Simulation time 323509068 ps
CPU time 1.65 seconds
Started Aug 02 07:23:31 PM PDT 24
Finished Aug 02 07:23:32 PM PDT 24
Peak memory 201068 kb
Host smart-696c6353-5461-4c63-9fd3-3e99b232449a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169787378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2169787378
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.1805485569
Short name T277
Test name
Test status
Simulation time 3922115000 ps
CPU time 21.87 seconds
Started Aug 02 07:23:41 PM PDT 24
Finished Aug 02 07:24:03 PM PDT 24
Peak memory 201504 kb
Host smart-add29f7a-08e9-4190-a774-0844e64273e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805485569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.1805485569
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3324143881
Short name T796
Test name
Test status
Simulation time 717587202382 ps
CPU time 2730.26 seconds
Started Aug 02 07:23:42 PM PDT 24
Finished Aug 02 08:09:13 PM PDT 24
Peak memory 217184 kb
Host smart-89b8c10c-96a8-4ffc-a944-fb99c3af25b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3324143881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.3324143881
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.clkmgr_trans.2211556406
Short name T581
Test name
Test status
Simulation time 78138246 ps
CPU time 1.05 seconds
Started Aug 02 07:23:36 PM PDT 24
Finished Aug 02 07:23:37 PM PDT 24
Peak memory 201080 kb
Host smart-582f42a3-e7fa-49ec-85ec-5bfe9dce75e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211556406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.2211556406
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.3060986820
Short name T189
Test name
Test status
Simulation time 46233685 ps
CPU time 0.84 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201180 kb
Host smart-acd0191c-eb81-47b4-b74e-5b5e8deaca4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060986820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.3060986820
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.3320690291
Short name T532
Test name
Test status
Simulation time 26050801 ps
CPU time 0.8 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201168 kb
Host smart-dd73dba3-685d-48f6-adf8-4758dd69c8d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320690291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.3320690291
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.1580265838
Short name T742
Test name
Test status
Simulation time 27324311 ps
CPU time 0.75 seconds
Started Aug 02 07:23:44 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 200300 kb
Host smart-53bea4e7-157d-4387-92d5-0803daac09ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580265838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1580265838
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.3153208423
Short name T405
Test name
Test status
Simulation time 14824361 ps
CPU time 0.79 seconds
Started Aug 02 07:23:45 PM PDT 24
Finished Aug 02 07:23:46 PM PDT 24
Peak memory 201188 kb
Host smart-db7aa632-fe7f-4712-a8aa-f8ec7480a559
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153208423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.3153208423
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.2713049518
Short name T268
Test name
Test status
Simulation time 1760546604 ps
CPU time 13.49 seconds
Started Aug 02 07:23:38 PM PDT 24
Finished Aug 02 07:23:52 PM PDT 24
Peak memory 201432 kb
Host smart-4e98639f-0c14-42a2-ad45-926ec13b2fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713049518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.2713049518
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.2727761491
Short name T260
Test name
Test status
Simulation time 301962848 ps
CPU time 1.64 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201252 kb
Host smart-32362f54-3685-49e1-8bde-a505c54e31ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727761491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.2727761491
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.939682578
Short name T496
Test name
Test status
Simulation time 39542839 ps
CPU time 0.89 seconds
Started Aug 02 07:23:44 PM PDT 24
Finished Aug 02 07:23:45 PM PDT 24
Peak memory 201068 kb
Host smart-107a3571-c3cd-4d88-99f3-26f67cdede9b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939682578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.clkmgr_idle_intersig_mubi.939682578
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.937795179
Short name T562
Test name
Test status
Simulation time 80478663 ps
CPU time 1 seconds
Started Aug 02 07:23:40 PM PDT 24
Finished Aug 02 07:23:41 PM PDT 24
Peak memory 201008 kb
Host smart-ec3f5cca-b9d7-4673-91b2-0aaec1383b13
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937795179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.clkmgr_lc_clk_byp_req_intersig_mubi.937795179
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1739960588
Short name T249
Test name
Test status
Simulation time 244256943 ps
CPU time 1.61 seconds
Started Aug 02 07:23:41 PM PDT 24
Finished Aug 02 07:23:43 PM PDT 24
Peak memory 201100 kb
Host smart-d9dc54c6-3beb-44e5-b859-94e27a35272c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739960588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.1739960588
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.140101583
Short name T602
Test name
Test status
Simulation time 16699427 ps
CPU time 0.75 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201020 kb
Host smart-ec2c1807-4d87-4751-8228-274007d5c9d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140101583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.140101583
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.2044141428
Short name T377
Test name
Test status
Simulation time 350034141 ps
CPU time 2.58 seconds
Started Aug 02 07:23:45 PM PDT 24
Finished Aug 02 07:23:48 PM PDT 24
Peak memory 201180 kb
Host smart-f95ba545-6b3b-45b2-a1a6-0727cf238c39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044141428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2044141428
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.776953906
Short name T214
Test name
Test status
Simulation time 20926262 ps
CPU time 0.85 seconds
Started Aug 02 07:23:40 PM PDT 24
Finished Aug 02 07:23:41 PM PDT 24
Peak memory 201032 kb
Host smart-f6849c72-4108-49e6-a5fc-61490374080a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776953906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.776953906
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.1115395871
Short name T386
Test name
Test status
Simulation time 22321439 ps
CPU time 0.8 seconds
Started Aug 02 07:23:42 PM PDT 24
Finished Aug 02 07:23:43 PM PDT 24
Peak memory 201080 kb
Host smart-c1b31d96-eaed-4fba-9572-8ab1be24abc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115395871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.1115395871
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.2508071433
Short name T100
Test name
Test status
Simulation time 63380535 ps
CPU time 1.1 seconds
Started Aug 02 07:23:42 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201060 kb
Host smart-25586586-2fb6-4273-bdd0-af778398803c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508071433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2508071433
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.2991120020
Short name T607
Test name
Test status
Simulation time 37682726 ps
CPU time 0.86 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201160 kb
Host smart-09edce5a-0da8-4687-97f5-d7d92037d32b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991120020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.2991120020
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.59256361
Short name T173
Test name
Test status
Simulation time 14506124 ps
CPU time 0.75 seconds
Started Aug 02 07:22:19 PM PDT 24
Finished Aug 02 07:22:19 PM PDT 24
Peak memory 200276 kb
Host smart-fa42fbb6-9065-478a-a255-b7fe00e66334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59256361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.59256361
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.760145701
Short name T689
Test name
Test status
Simulation time 41338853 ps
CPU time 0.84 seconds
Started Aug 02 07:22:19 PM PDT 24
Finished Aug 02 07:22:20 PM PDT 24
Peak memory 201076 kb
Host smart-5c43efa1-6950-4a51-acb5-6507775b1044
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760145701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_div_intersig_mubi.760145701
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.1768495025
Short name T394
Test name
Test status
Simulation time 98471775 ps
CPU time 1.06 seconds
Started Aug 02 07:22:12 PM PDT 24
Finished Aug 02 07:22:13 PM PDT 24
Peak memory 201088 kb
Host smart-bd787fe2-422f-4f8d-9385-5d7f1830085a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768495025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1768495025
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.3435741735
Short name T1
Test name
Test status
Simulation time 2118298259 ps
CPU time 16.25 seconds
Started Aug 02 07:22:14 PM PDT 24
Finished Aug 02 07:22:30 PM PDT 24
Peak memory 201424 kb
Host smart-222b00b8-c824-4767-9440-6ba68cf997c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435741735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.3435741735
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.1448342295
Short name T364
Test name
Test status
Simulation time 1575443974 ps
CPU time 11.93 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:23 PM PDT 24
Peak memory 201272 kb
Host smart-4135e38f-22a9-44c4-964e-f89569f2d0e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448342295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.1448342295
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.2782162476
Short name T509
Test name
Test status
Simulation time 101550032 ps
CPU time 1.14 seconds
Started Aug 02 07:22:12 PM PDT 24
Finished Aug 02 07:22:13 PM PDT 24
Peak memory 201168 kb
Host smart-788730d3-4025-4428-b34c-9a7ec7aa6758
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782162476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.2782162476
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.3306025486
Short name T311
Test name
Test status
Simulation time 16452765 ps
CPU time 0.77 seconds
Started Aug 02 07:22:15 PM PDT 24
Finished Aug 02 07:22:16 PM PDT 24
Peak memory 201172 kb
Host smart-27349e97-03b0-427e-927a-772125072a57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306025486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.3306025486
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3720866954
Short name T251
Test name
Test status
Simulation time 72063117 ps
CPU time 0.96 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201160 kb
Host smart-34c18b70-22be-4352-be52-507c42ab703f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720866954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.3720866954
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.1701582294
Short name T622
Test name
Test status
Simulation time 42419511 ps
CPU time 0.82 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201148 kb
Host smart-6c6d6b93-1212-44bc-8072-b3b2e2192b6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701582294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1701582294
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.1626421395
Short name T73
Test name
Test status
Simulation time 904767833 ps
CPU time 5.3 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:16 PM PDT 24
Peak memory 201336 kb
Host smart-e7486d6a-7be6-4829-9476-d340441e6064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626421395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1626421395
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.2840935515
Short name T52
Test name
Test status
Simulation time 158373826 ps
CPU time 2.06 seconds
Started Aug 02 07:22:12 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 216516 kb
Host smart-af87c749-197f-4d2d-acd6-8e3678757b5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840935515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.2840935515
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.6163154
Short name T690
Test name
Test status
Simulation time 25232620 ps
CPU time 0.89 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:15 PM PDT 24
Peak memory 200920 kb
Host smart-d96f0572-9bfc-4f3c-a536-9e147996a92d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6163154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.6163154
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.2152390746
Short name T588
Test name
Test status
Simulation time 7404175665 ps
CPU time 53.71 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:23:07 PM PDT 24
Peak memory 201512 kb
Host smart-88073d6c-17fc-43d4-8536-4ef67601bb82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152390746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.2152390746
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.3082614676
Short name T521
Test name
Test status
Simulation time 26925028 ps
CPU time 0.79 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:12 PM PDT 24
Peak memory 201148 kb
Host smart-460bf5d9-8434-4490-9587-66cffdbd6ded
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082614676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.3082614676
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.1983956590
Short name T245
Test name
Test status
Simulation time 14212063 ps
CPU time 0.72 seconds
Started Aug 02 07:23:40 PM PDT 24
Finished Aug 02 07:23:41 PM PDT 24
Peak memory 201088 kb
Host smart-879660e1-8950-488a-be4a-b3c569ec96ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983956590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.1983956590
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.2537264491
Short name T616
Test name
Test status
Simulation time 29307645 ps
CPU time 0.8 seconds
Started Aug 02 07:23:44 PM PDT 24
Finished Aug 02 07:23:45 PM PDT 24
Peak memory 201144 kb
Host smart-9b2f5207-4f07-49d8-8f60-b64708b764b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537264491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.2537264491
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.2032656397
Short name T795
Test name
Test status
Simulation time 113729420 ps
CPU time 0.96 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:45 PM PDT 24
Peak memory 200352 kb
Host smart-99954107-7c27-48db-925d-277d27335865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032656397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.2032656397
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.3079024274
Short name T665
Test name
Test status
Simulation time 16630379 ps
CPU time 0.8 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201056 kb
Host smart-4743d0b3-bc5c-46b4-9410-2bbf6fb6c0df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079024274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.3079024274
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.341667365
Short name T453
Test name
Test status
Simulation time 49583983 ps
CPU time 0.85 seconds
Started Aug 02 07:23:44 PM PDT 24
Finished Aug 02 07:23:45 PM PDT 24
Peak memory 201020 kb
Host smart-7f4b3417-d8fa-4197-bb64-bd317476426b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341667365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.341667365
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1747593314
Short name T423
Test name
Test status
Simulation time 313757262 ps
CPU time 2.89 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:46 PM PDT 24
Peak memory 201172 kb
Host smart-2e8a0488-6485-489f-aee9-1ae729f2a0ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747593314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1747593314
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.3991869004
Short name T758
Test name
Test status
Simulation time 785904953 ps
CPU time 3.28 seconds
Started Aug 02 07:23:42 PM PDT 24
Finished Aug 02 07:23:46 PM PDT 24
Peak memory 201200 kb
Host smart-c38e3ad4-9789-4694-a91e-26e4cc7b2625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991869004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.3991869004
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1135345629
Short name T387
Test name
Test status
Simulation time 41108705 ps
CPU time 0.83 seconds
Started Aug 02 07:23:44 PM PDT 24
Finished Aug 02 07:23:45 PM PDT 24
Peak memory 201140 kb
Host smart-30a1034a-a489-46d8-9532-359d74eaf877
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135345629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.1135345629
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2146207690
Short name T232
Test name
Test status
Simulation time 110537764 ps
CPU time 1.15 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:45 PM PDT 24
Peak memory 201108 kb
Host smart-280ef985-beeb-45d3-bd32-1bdc613a3e2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146207690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2146207690
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3545227071
Short name T96
Test name
Test status
Simulation time 149594486 ps
CPU time 1.15 seconds
Started Aug 02 07:23:42 PM PDT 24
Finished Aug 02 07:23:43 PM PDT 24
Peak memory 201076 kb
Host smart-cfececd5-930c-4f6b-aad6-32f9407d1dfe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545227071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.3545227071
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.3363473565
Short name T360
Test name
Test status
Simulation time 14883056 ps
CPU time 0.74 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201128 kb
Host smart-981213cf-5f79-491b-b898-f1a9ebcfed55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363473565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.3363473565
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.1304065083
Short name T672
Test name
Test status
Simulation time 371467644 ps
CPU time 2.58 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:45 PM PDT 24
Peak memory 201116 kb
Host smart-12bf9ba2-91d9-430c-8677-980ce3f71999
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304065083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1304065083
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.941319447
Short name T738
Test name
Test status
Simulation time 37867947 ps
CPU time 0.88 seconds
Started Aug 02 07:23:43 PM PDT 24
Finished Aug 02 07:23:44 PM PDT 24
Peak memory 201120 kb
Host smart-4fdeb9c6-7747-4a23-9c9d-9a1b62bfca2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941319447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.941319447
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.3362017850
Short name T415
Test name
Test status
Simulation time 1024055335 ps
CPU time 8.48 seconds
Started Aug 02 07:23:42 PM PDT 24
Finished Aug 02 07:23:51 PM PDT 24
Peak memory 201396 kb
Host smart-8e0590fd-6f39-4f64-bc04-f4c6ae178535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362017850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.3362017850
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.3817844015
Short name T542
Test name
Test status
Simulation time 16094952 ps
CPU time 0.83 seconds
Started Aug 02 07:23:40 PM PDT 24
Finished Aug 02 07:23:41 PM PDT 24
Peak memory 201140 kb
Host smart-55b414d0-4e0d-4b84-9801-12a315eb176d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817844015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.3817844015
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.4179700980
Short name T55
Test name
Test status
Simulation time 17884213 ps
CPU time 0.75 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:23:54 PM PDT 24
Peak memory 201100 kb
Host smart-18c0715f-d938-4b30-b3fb-703c5f76db6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179700980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.4179700980
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.1180944673
Short name T571
Test name
Test status
Simulation time 25745719 ps
CPU time 0.91 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:23:55 PM PDT 24
Peak memory 201104 kb
Host smart-49fe91f9-b595-46ec-9a09-fede9bcd2aba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180944673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.1180944673
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.578998927
Short name T340
Test name
Test status
Simulation time 131515056 ps
CPU time 0.99 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 200312 kb
Host smart-e193375b-06cf-4fff-8d5e-62e9fc83e467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578998927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.578998927
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.57564689
Short name T548
Test name
Test status
Simulation time 49713540 ps
CPU time 0.84 seconds
Started Aug 02 07:23:53 PM PDT 24
Finished Aug 02 07:23:54 PM PDT 24
Peak memory 201044 kb
Host smart-2c6638b0-a4ba-4896-b460-4d23db86b631
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57564689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.clkmgr_div_intersig_mubi.57564689
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.1880955204
Short name T429
Test name
Test status
Simulation time 45109227 ps
CPU time 0.82 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:56 PM PDT 24
Peak memory 201076 kb
Host smart-2f3ae291-1359-4937-9be4-79ce8bea8c44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880955204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1880955204
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.2483606257
Short name T255
Test name
Test status
Simulation time 1881308745 ps
CPU time 14.59 seconds
Started Aug 02 07:23:53 PM PDT 24
Finished Aug 02 07:24:08 PM PDT 24
Peak memory 201476 kb
Host smart-eb544256-91a3-4314-9f48-6374a50b050b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483606257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2483606257
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.2065064502
Short name T514
Test name
Test status
Simulation time 2632660544 ps
CPU time 8.9 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201488 kb
Host smart-573f95fa-9284-4852-8055-f774ccc39813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065064502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.2065064502
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.3236280988
Short name T799
Test name
Test status
Simulation time 61794656 ps
CPU time 0.95 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201188 kb
Host smart-8d32e455-da25-40a0-abb6-ea45d0dcabe7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236280988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.3236280988
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3303772717
Short name T362
Test name
Test status
Simulation time 22707923 ps
CPU time 0.8 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:56 PM PDT 24
Peak memory 201008 kb
Host smart-7872dcca-9337-4078-8ef8-52b5eb08172d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303772717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.3303772717
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.3495727425
Short name T224
Test name
Test status
Simulation time 21825230 ps
CPU time 0.78 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:56 PM PDT 24
Peak memory 201148 kb
Host smart-f55abf02-a606-4b5b-85cd-59f6ff80541f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495727425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3495727425
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.442768890
Short name T104
Test name
Test status
Simulation time 556117705 ps
CPU time 2.98 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:03 PM PDT 24
Peak memory 201368 kb
Host smart-4c2de9b3-1ec8-438c-bf7a-6f802f303ca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442768890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.442768890
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.175731695
Short name T488
Test name
Test status
Simulation time 28848360 ps
CPU time 0.85 seconds
Started Aug 02 07:23:42 PM PDT 24
Finished Aug 02 07:23:43 PM PDT 24
Peak memory 201100 kb
Host smart-d9f1da82-931e-4110-9f13-c510bec0b4fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175731695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.175731695
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.1713692587
Short name T20
Test name
Test status
Simulation time 9561147066 ps
CPU time 39.82 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:24:37 PM PDT 24
Peak memory 201420 kb
Host smart-0ac1b97f-218c-4e90-8102-dd275b5069c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713692587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.1713692587
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.4096944236
Short name T315
Test name
Test status
Simulation time 29846697 ps
CPU time 0.98 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:56 PM PDT 24
Peak memory 201096 kb
Host smart-c5bc2f81-5df2-4396-9d17-56e9c9f522d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096944236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.4096944236
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.571273572
Short name T584
Test name
Test status
Simulation time 48485595 ps
CPU time 0.85 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201184 kb
Host smart-db960809-d579-49ec-8873-a6f8f07049d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571273572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkm
gr_alert_test.571273572
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.3797585098
Short name T691
Test name
Test status
Simulation time 92414987 ps
CPU time 1.1 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:56 PM PDT 24
Peak memory 201084 kb
Host smart-64cd07cd-44d5-4ad5-8e5e-1ccfe229484b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797585098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.3797585098
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.3513087301
Short name T492
Test name
Test status
Simulation time 13580520 ps
CPU time 0.72 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:23:55 PM PDT 24
Peak memory 200272 kb
Host smart-f9d34e54-9541-409c-a5de-3f158470ac82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513087301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3513087301
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.814013224
Short name T140
Test name
Test status
Simulation time 152149106 ps
CPU time 1.22 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201096 kb
Host smart-a2651cd8-b013-4ca2-bb41-e620fdd645d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814013224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_div_intersig_mubi.814013224
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.4246324337
Short name T392
Test name
Test status
Simulation time 32219915 ps
CPU time 0.82 seconds
Started Aug 02 07:23:58 PM PDT 24
Finished Aug 02 07:23:59 PM PDT 24
Peak memory 201116 kb
Host smart-fca91a25-832e-4beb-9ff3-6cc8ef3c77a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246324337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.4246324337
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.1120696268
Short name T649
Test name
Test status
Simulation time 2236934130 ps
CPU time 17.63 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:24:14 PM PDT 24
Peak memory 201416 kb
Host smart-efc5a49e-283f-4416-a67f-e4692790a0b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120696268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.1120696268
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.3231001993
Short name T777
Test name
Test status
Simulation time 1459301518 ps
CPU time 10.89 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:24:07 PM PDT 24
Peak memory 201216 kb
Host smart-d3d2598b-73fa-44a5-967e-2dc662e721fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231001993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.3231001993
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.3468872283
Short name T466
Test name
Test status
Simulation time 16965726 ps
CPU time 0.84 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 200600 kb
Host smart-b0bf7661-b21b-4674-911f-e9294df386ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468872283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.3468872283
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2775059942
Short name T378
Test name
Test status
Simulation time 62118676 ps
CPU time 0.95 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201076 kb
Host smart-6c6e3375-6bbb-4a00-a506-224c8e941fb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775059942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2775059942
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.3854515548
Short name T91
Test name
Test status
Simulation time 57400508 ps
CPU time 0.99 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:56 PM PDT 24
Peak memory 201080 kb
Host smart-9413a58f-b407-4fd8-9d2f-5c08334b2c04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854515548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.3854515548
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.3138039103
Short name T574
Test name
Test status
Simulation time 14514050 ps
CPU time 0.77 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:01 PM PDT 24
Peak memory 201172 kb
Host smart-cf60ea31-c696-4ded-a571-bbe420f1e351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138039103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3138039103
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.1356447585
Short name T431
Test name
Test status
Simulation time 513012653 ps
CPU time 2.73 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201296 kb
Host smart-c2e5cfef-9caf-4723-a4d1-d63600545c33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356447585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.1356447585
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.2139362388
Short name T336
Test name
Test status
Simulation time 26626595 ps
CPU time 0.81 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:23:54 PM PDT 24
Peak memory 201072 kb
Host smart-36c7fb76-4f56-48f9-bf8a-a4e1db3d31b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139362388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.2139362388
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.3627631936
Short name T612
Test name
Test status
Simulation time 5932918925 ps
CPU time 25.25 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:25 PM PDT 24
Peak memory 201476 kb
Host smart-02b8a825-666c-4946-89ce-335b8117d7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627631936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.3627631936
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.3762732347
Short name T23
Test name
Test status
Simulation time 31440571 ps
CPU time 1.01 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 200664 kb
Host smart-7a2266d1-f423-48c4-a36a-194e9f040b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762732347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3762732347
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.2734160945
Short name T44
Test name
Test status
Simulation time 21054622 ps
CPU time 0.71 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201052 kb
Host smart-9be655a2-4427-4584-85e6-e7e872a816dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734160945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.2734160945
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2627099385
Short name T116
Test name
Test status
Simulation time 72018504 ps
CPU time 1.05 seconds
Started Aug 02 07:23:58 PM PDT 24
Finished Aug 02 07:23:59 PM PDT 24
Peak memory 201060 kb
Host smart-0b472c37-4dc2-4ce0-b247-60f4507edf26
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627099385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.2627099385
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.2541491111
Short name T613
Test name
Test status
Simulation time 24067377 ps
CPU time 0.73 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:23:58 PM PDT 24
Peak memory 201036 kb
Host smart-8e7b83eb-0915-4958-b76c-a648315c0fa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541491111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.2541491111
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.1056183700
Short name T567
Test name
Test status
Simulation time 88374979 ps
CPU time 1.2 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201020 kb
Host smart-169ca125-ef08-4b65-8222-7597f893304c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056183700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.1056183700
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.2006145929
Short name T292
Test name
Test status
Simulation time 70213081 ps
CPU time 1.02 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201112 kb
Host smart-31cc6610-4672-4c6b-bec9-139f2172133e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006145929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.2006145929
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.3748378208
Short name T401
Test name
Test status
Simulation time 1281177396 ps
CPU time 10.41 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:24:04 PM PDT 24
Peak memory 201200 kb
Host smart-edb77726-c5f8-4685-933b-e7531fb3add3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748378208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3748378208
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.608540264
Short name T794
Test name
Test status
Simulation time 144795478 ps
CPU time 1.34 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:01 PM PDT 24
Peak memory 201260 kb
Host smart-935e194d-715c-4ae6-8838-0beef7e78cde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608540264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_ti
meout.608540264
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.3489098219
Short name T642
Test name
Test status
Simulation time 45152956 ps
CPU time 0.91 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:01 PM PDT 24
Peak memory 201124 kb
Host smart-dbf1bc58-b902-4bf5-ae2f-6dc78010b76d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489098219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.3489098219
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.2434671393
Short name T385
Test name
Test status
Simulation time 19599184 ps
CPU time 0.81 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 201104 kb
Host smart-f481b3c8-47ef-496d-9a2c-4160cd9c5485
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434671393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.2434671393
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.1427073995
Short name T265
Test name
Test status
Simulation time 74075310 ps
CPU time 0.96 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 201120 kb
Host smart-698d75bd-3345-42a1-bb81-587e9c63878e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427073995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.1427073995
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.3659593295
Short name T614
Test name
Test status
Simulation time 35344717 ps
CPU time 0.78 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201196 kb
Host smart-0b16976a-1f49-45fa-b5e2-fe2aaa956e22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659593295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3659593295
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.471331431
Short name T159
Test name
Test status
Simulation time 618716264 ps
CPU time 2.49 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:58 PM PDT 24
Peak memory 201088 kb
Host smart-ccbef5d2-e49e-40b1-a835-541c4410b9f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471331431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.471331431
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.751340751
Short name T470
Test name
Test status
Simulation time 18721026 ps
CPU time 0.82 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:23:56 PM PDT 24
Peak memory 201144 kb
Host smart-17d61abe-7723-454a-a6b3-1a80d89e4a80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751340751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.751340751
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.117922089
Short name T707
Test name
Test status
Simulation time 11504854017 ps
CPU time 47.18 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:24:41 PM PDT 24
Peak memory 201452 kb
Host smart-f0bf95a8-62bb-43dc-ba15-70525456369c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117922089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.117922089
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.1876143809
Short name T719
Test name
Test status
Simulation time 61680960256 ps
CPU time 440.35 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:31:21 PM PDT 24
Peak memory 217956 kb
Host smart-90fb46fc-88ed-4295-aefc-36011d9aaa56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1876143809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.1876143809
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_trans.1066956390
Short name T650
Test name
Test status
Simulation time 37159201 ps
CPU time 0.8 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:23:55 PM PDT 24
Peak memory 201084 kb
Host smart-7168c3f6-bc5b-45cf-ba02-1fc4096ac1c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066956390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.1066956390
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.1027112422
Short name T188
Test name
Test status
Simulation time 22157872 ps
CPU time 0.79 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201100 kb
Host smart-c7377180-94c2-485c-9cf2-cc50b1d29b89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027112422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.1027112422
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.1088911925
Short name T610
Test name
Test status
Simulation time 16248784 ps
CPU time 0.78 seconds
Started Aug 02 07:24:01 PM PDT 24
Finished Aug 02 07:24:02 PM PDT 24
Peak memory 201100 kb
Host smart-232f8a86-c1cf-4d98-af16-f1af91a2e6a8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088911925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.1088911925
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.3602031908
Short name T507
Test name
Test status
Simulation time 29324543 ps
CPU time 0.73 seconds
Started Aug 02 07:23:54 PM PDT 24
Finished Aug 02 07:23:55 PM PDT 24
Peak memory 200272 kb
Host smart-9b5fc5d6-bb4b-4058-82ad-fff2016f6303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602031908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3602031908
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1689852738
Short name T139
Test name
Test status
Simulation time 36556619 ps
CPU time 0.81 seconds
Started Aug 02 07:23:58 PM PDT 24
Finished Aug 02 07:23:59 PM PDT 24
Peak memory 201112 kb
Host smart-29a76091-7be4-4f76-ad39-8d245052a549
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689852738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.1689852738
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.359354650
Short name T231
Test name
Test status
Simulation time 33816605 ps
CPU time 0.89 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201132 kb
Host smart-7de97cb7-ca72-4d57-b844-829861dd6b49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359354650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.359354650
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.585841639
Short name T38
Test name
Test status
Simulation time 449608898 ps
CPU time 2.93 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:59 PM PDT 24
Peak memory 201188 kb
Host smart-32a04686-1951-4f4e-a4de-84f00735fb3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585841639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.585841639
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.2957573976
Short name T552
Test name
Test status
Simulation time 2337214716 ps
CPU time 9.73 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:24:07 PM PDT 24
Peak memory 201408 kb
Host smart-da8e2d06-3b24-4c3d-af62-1a13a2da1e8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957573976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.2957573976
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3065418835
Short name T804
Test name
Test status
Simulation time 13668757 ps
CPU time 0.74 seconds
Started Aug 02 07:24:03 PM PDT 24
Finished Aug 02 07:24:04 PM PDT 24
Peak memory 201080 kb
Host smart-9f39f5e7-66c1-4de7-bf38-8f52e2b301b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065418835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3065418835
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.3058246016
Short name T576
Test name
Test status
Simulation time 87031113 ps
CPU time 1.06 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:01 PM PDT 24
Peak memory 201100 kb
Host smart-8f66b39c-8244-4645-929c-57284d7fcc79
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058246016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.3058246016
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.372713310
Short name T435
Test name
Test status
Simulation time 26818899 ps
CPU time 0.93 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:01 PM PDT 24
Peak memory 201108 kb
Host smart-349b11a7-acd4-4848-aeaf-7c266522772f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372713310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.clkmgr_lc_ctrl_intersig_mubi.372713310
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.3112585847
Short name T474
Test name
Test status
Simulation time 38368699 ps
CPU time 0.81 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 201084 kb
Host smart-1a4d05a7-eec2-49ef-82df-b3a7e0b649bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112585847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3112585847
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.2715640206
Short name T623
Test name
Test status
Simulation time 1484976524 ps
CPU time 5.54 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 201248 kb
Host smart-60a32cd6-1515-480a-b9ba-d6b3200e56fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715640206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.2715640206
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.1454828163
Short name T57
Test name
Test status
Simulation time 25230280 ps
CPU time 0.88 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:23:58 PM PDT 24
Peak memory 201060 kb
Host smart-ba4a59f4-348c-4fde-86c4-63e562a81233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454828163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.1454828163
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.2862839358
Short name T164
Test name
Test status
Simulation time 1991795296 ps
CPU time 9.02 seconds
Started Aug 02 07:23:58 PM PDT 24
Finished Aug 02 07:24:07 PM PDT 24
Peak memory 201408 kb
Host smart-b2363e24-f413-45bb-b788-dcdb3f66e0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862839358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.2862839358
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.78008298
Short name T390
Test name
Test status
Simulation time 39450255 ps
CPU time 1.06 seconds
Started Aug 02 07:23:56 PM PDT 24
Finished Aug 02 07:23:57 PM PDT 24
Peak memory 201032 kb
Host smart-9bb74536-51b9-459d-900f-9840318c41e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78008298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.78008298
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.2737520455
Short name T375
Test name
Test status
Simulation time 37033540 ps
CPU time 0.82 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201124 kb
Host smart-2f9df81c-c312-46f2-aea4-bc677e90edc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737520455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.2737520455
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1799558881
Short name T323
Test name
Test status
Simulation time 21409115 ps
CPU time 0.76 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:01 PM PDT 24
Peak memory 201088 kb
Host smart-e7fba780-34f7-4b38-8705-68f94cd74d2b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799558881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.1799558881
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.498369177
Short name T732
Test name
Test status
Simulation time 11540404 ps
CPU time 0.68 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:23:58 PM PDT 24
Peak memory 201016 kb
Host smart-c17fac8f-1228-4ddf-afb4-734ed0e97693
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498369177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.498369177
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.1924690140
Short name T704
Test name
Test status
Simulation time 20611430 ps
CPU time 0.85 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201084 kb
Host smart-f17115ef-43a2-437e-813b-0f805f373593
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924690140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.1924690140
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3812298064
Short name T241
Test name
Test status
Simulation time 18715743 ps
CPU time 0.89 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:01 PM PDT 24
Peak memory 201136 kb
Host smart-4ebc70fd-c7f1-4803-b842-dfe66ed13b71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812298064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3812298064
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.2065361338
Short name T287
Test name
Test status
Simulation time 984764867 ps
CPU time 4.63 seconds
Started Aug 02 07:23:55 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 201216 kb
Host smart-7e909a36-7ffe-40f1-b8b4-0cb09a28f854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065361338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.2065361338
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.107905449
Short name T463
Test name
Test status
Simulation time 518247004 ps
CPU time 2.73 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:02 PM PDT 24
Peak memory 201244 kb
Host smart-a59afe37-f3bf-413e-a357-c7d40bee16f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107905449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_ti
meout.107905449
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3009866472
Short name T434
Test name
Test status
Simulation time 24977771 ps
CPU time 0.93 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 201144 kb
Host smart-b3eaab58-e767-4960-968c-0664c25e912e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009866472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3009866472
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.2022511110
Short name T469
Test name
Test status
Simulation time 17603512 ps
CPU time 0.77 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:23:58 PM PDT 24
Peak memory 201100 kb
Host smart-f3e4f582-0149-45e6-8037-7b275d3c3567
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022511110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.2022511110
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2933523399
Short name T457
Test name
Test status
Simulation time 22889659 ps
CPU time 0.87 seconds
Started Aug 02 07:24:01 PM PDT 24
Finished Aug 02 07:24:02 PM PDT 24
Peak memory 201096 kb
Host smart-368ab681-588f-42d3-9ee5-2d08572bea47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933523399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.2933523399
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.3506092992
Short name T816
Test name
Test status
Simulation time 24726630 ps
CPU time 0.8 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:02 PM PDT 24
Peak memory 201104 kb
Host smart-55e6c84d-8a70-4b21-9899-9bce6d75428b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506092992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.3506092992
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.3416770588
Short name T545
Test name
Test status
Simulation time 1442521954 ps
CPU time 5.04 seconds
Started Aug 02 07:24:00 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201324 kb
Host smart-44235ba8-2ab2-473d-805b-6d88ac211b52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416770588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3416770588
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2948144339
Short name T757
Test name
Test status
Simulation time 23823073 ps
CPU time 0.87 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:23:58 PM PDT 24
Peak memory 200984 kb
Host smart-2c223eab-3371-412c-94c6-56ebbe5b31d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948144339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2948144339
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.1271345575
Short name T482
Test name
Test status
Simulation time 4361534586 ps
CPU time 21.25 seconds
Started Aug 02 07:24:01 PM PDT 24
Finished Aug 02 07:24:22 PM PDT 24
Peak memory 201524 kb
Host smart-81d0346d-81d4-4d70-b1fa-16be9160d24c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271345575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.1271345575
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.938059321
Short name T89
Test name
Test status
Simulation time 43349492426 ps
CPU time 646.49 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:34:44 PM PDT 24
Peak memory 217968 kb
Host smart-5eaf0f4b-f26a-438e-841c-8acc0f6ba9f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=938059321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.938059321
Directory /workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.clkmgr_trans.1089062490
Short name T731
Test name
Test status
Simulation time 25893479 ps
CPU time 0.96 seconds
Started Aug 02 07:24:01 PM PDT 24
Finished Aug 02 07:24:02 PM PDT 24
Peak memory 201128 kb
Host smart-8f0b5f40-6f7b-4a4d-8055-46cc40933f83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089062490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1089062490
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.2135998279
Short name T349
Test name
Test status
Simulation time 14696303 ps
CPU time 0.78 seconds
Started Aug 02 07:24:03 PM PDT 24
Finished Aug 02 07:24:04 PM PDT 24
Peak memory 201124 kb
Host smart-0123b6ad-0a1f-4dbd-ac8e-e989d96ee901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135998279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.2135998279
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3038749350
Short name T801
Test name
Test status
Simulation time 46987353 ps
CPU time 0.99 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201108 kb
Host smart-9b68ecf5-19c2-473b-815b-4ccf6d5e2c60
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038749350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.3038749350
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.374785465
Short name T234
Test name
Test status
Simulation time 31845412 ps
CPU time 0.74 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 200344 kb
Host smart-f6266b97-68ca-45ab-9687-83b16935ea34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374785465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.374785465
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.296686440
Short name T300
Test name
Test status
Simulation time 19301982 ps
CPU time 0.81 seconds
Started Aug 02 07:24:02 PM PDT 24
Finished Aug 02 07:24:03 PM PDT 24
Peak memory 201148 kb
Host smart-f9ca97a4-e634-4736-ae79-2f76a0302f0c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296686440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_div_intersig_mubi.296686440
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.3615259842
Short name T220
Test name
Test status
Simulation time 17496386 ps
CPU time 0.77 seconds
Started Aug 02 07:24:01 PM PDT 24
Finished Aug 02 07:24:01 PM PDT 24
Peak memory 201116 kb
Host smart-61bf6a38-089c-4e44-85e1-8a0ca586122d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615259842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.3615259842
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.3963972948
Short name T442
Test name
Test status
Simulation time 2354095532 ps
CPU time 18.23 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:22 PM PDT 24
Peak memory 201444 kb
Host smart-6a163406-58d9-4919-8d05-ea9d27532d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963972948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3963972948
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.479686620
Short name T753
Test name
Test status
Simulation time 854128727 ps
CPU time 6.91 seconds
Started Aug 02 07:24:02 PM PDT 24
Finished Aug 02 07:24:09 PM PDT 24
Peak memory 201248 kb
Host smart-9ade6979-0f64-4705-842b-9cef44f52deb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479686620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_ti
meout.479686620
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.368307227
Short name T183
Test name
Test status
Simulation time 37105272 ps
CPU time 1.11 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201096 kb
Host smart-0a8d164b-23d2-4260-a3a2-21bd3db75f65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368307227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_idle_intersig_mubi.368307227
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.2827335125
Short name T566
Test name
Test status
Simulation time 128713528 ps
CPU time 1.2 seconds
Started Aug 02 07:24:03 PM PDT 24
Finished Aug 02 07:24:04 PM PDT 24
Peak memory 201096 kb
Host smart-59b18ff7-b33d-4fe6-b4df-c2fc78cfdea9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827335125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.2827335125
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2796188529
Short name T710
Test name
Test status
Simulation time 15027113 ps
CPU time 0.79 seconds
Started Aug 02 07:24:01 PM PDT 24
Finished Aug 02 07:24:02 PM PDT 24
Peak memory 201108 kb
Host smart-d03ac7ce-bbad-41be-ba14-87e6236853b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796188529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.2796188529
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.3801606725
Short name T720
Test name
Test status
Simulation time 16478032 ps
CPU time 0.74 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:23:58 PM PDT 24
Peak memory 201152 kb
Host smart-04db87c5-cb00-42a3-a25d-af9aa181f879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801606725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.3801606725
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.4046427694
Short name T448
Test name
Test status
Simulation time 1271191598 ps
CPU time 4.6 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:08 PM PDT 24
Peak memory 201240 kb
Host smart-c8bfa1cf-842d-4f82-83ab-f465542726bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046427694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.4046427694
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.694714255
Short name T209
Test name
Test status
Simulation time 22737387 ps
CPU time 0.84 seconds
Started Aug 02 07:23:57 PM PDT 24
Finished Aug 02 07:23:58 PM PDT 24
Peak memory 201096 kb
Host smart-9b2acc4a-2d97-41c2-8000-8a7c4bf2be1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694714255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.694714255
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.3695405180
Short name T41
Test name
Test status
Simulation time 4512944567 ps
CPU time 27.44 seconds
Started Aug 02 07:24:02 PM PDT 24
Finished Aug 02 07:24:29 PM PDT 24
Peak memory 201524 kb
Host smart-8de77416-42ba-40e0-bc80-ecddd6282cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695405180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.3695405180
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.2278357796
Short name T88
Test name
Test status
Simulation time 51870892915 ps
CPU time 334.72 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:29:39 PM PDT 24
Peak memory 209796 kb
Host smart-7c1b07eb-69de-4f70-8558-c4f95f23e733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2278357796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.2278357796
Directory /workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.clkmgr_trans.1506317825
Short name T640
Test name
Test status
Simulation time 20463350 ps
CPU time 0.82 seconds
Started Aug 02 07:24:01 PM PDT 24
Finished Aug 02 07:24:02 PM PDT 24
Peak memory 201132 kb
Host smart-1f2de5cc-bd7c-4ce4-84b2-eae2fe0aa73e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506317825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1506317825
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.3257604596
Short name T807
Test name
Test status
Simulation time 16593380 ps
CPU time 0.76 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:04 PM PDT 24
Peak memory 201172 kb
Host smart-a56cb533-cb63-4051-a9be-a40a1fbb2e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257604596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.3257604596
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3151430834
Short name T29
Test name
Test status
Simulation time 30284429 ps
CPU time 0.95 seconds
Started Aug 02 07:24:06 PM PDT 24
Finished Aug 02 07:24:07 PM PDT 24
Peak memory 201108 kb
Host smart-778ad2f9-6288-4ab4-b334-b8a3eb3ff006
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151430834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.3151430834
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.1217564438
Short name T772
Test name
Test status
Simulation time 19102247 ps
CPU time 0.76 seconds
Started Aug 02 07:24:03 PM PDT 24
Finished Aug 02 07:24:04 PM PDT 24
Peak memory 201052 kb
Host smart-b389bd48-9a51-495f-8c3c-ae62a9c24adf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217564438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1217564438
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.1787103171
Short name T97
Test name
Test status
Simulation time 16255005 ps
CPU time 0.73 seconds
Started Aug 02 07:24:08 PM PDT 24
Finished Aug 02 07:24:08 PM PDT 24
Peak memory 201096 kb
Host smart-4e2482ea-9905-4443-a73a-241836b10331
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787103171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.1787103171
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.209055957
Short name T499
Test name
Test status
Simulation time 90459276 ps
CPU time 0.99 seconds
Started Aug 02 07:24:03 PM PDT 24
Finished Aug 02 07:24:04 PM PDT 24
Peak memory 201140 kb
Host smart-bcc0f9e3-58cf-4b12-b30a-7a1c86a66168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209055957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.209055957
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.998047213
Short name T15
Test name
Test status
Simulation time 681130924 ps
CPU time 5.91 seconds
Started Aug 02 07:24:02 PM PDT 24
Finished Aug 02 07:24:08 PM PDT 24
Peak memory 201196 kb
Host smart-ffcda736-79cd-49b6-999e-f2f70f4cb210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998047213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.998047213
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.3246518815
Short name T61
Test name
Test status
Simulation time 1460137951 ps
CPU time 10.55 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:10 PM PDT 24
Peak memory 201192 kb
Host smart-3ce3980a-7bd6-4eee-aba8-8458096f8320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246518815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.3246518815
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.3126918560
Short name T242
Test name
Test status
Simulation time 83875462 ps
CPU time 1.09 seconds
Started Aug 02 07:24:03 PM PDT 24
Finished Aug 02 07:24:04 PM PDT 24
Peak memory 201144 kb
Host smart-0ab62821-7750-4a8c-ac05-acd9a9d32a32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126918560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.3126918560
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.956211401
Short name T201
Test name
Test status
Simulation time 23231077 ps
CPU time 0.9 seconds
Started Aug 02 07:23:59 PM PDT 24
Finished Aug 02 07:24:00 PM PDT 24
Peak memory 201104 kb
Host smart-d353d9b0-dd69-4712-85ce-e61114151cd4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956211401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_clk_byp_req_intersig_mubi.956211401
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.2037764960
Short name T369
Test name
Test status
Simulation time 50984168 ps
CPU time 0.85 seconds
Started Aug 02 07:24:02 PM PDT 24
Finished Aug 02 07:24:03 PM PDT 24
Peak memory 201140 kb
Host smart-213328e7-2a88-4562-b735-e40ad56cf914
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037764960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.2037764960
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.3408827140
Short name T262
Test name
Test status
Simulation time 39572693 ps
CPU time 0.77 seconds
Started Aug 02 07:24:02 PM PDT 24
Finished Aug 02 07:24:03 PM PDT 24
Peak memory 201116 kb
Host smart-d0b3bbb3-ac1e-490f-9999-d824e8fb124f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408827140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.3408827140
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.597724533
Short name T697
Test name
Test status
Simulation time 67982061 ps
CPU time 1.02 seconds
Started Aug 02 07:24:12 PM PDT 24
Finished Aug 02 07:24:13 PM PDT 24
Peak memory 201184 kb
Host smart-89531fa8-7eb1-4747-8a58-826e441ee7ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597724533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.597724533
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.135706512
Short name T713
Test name
Test status
Simulation time 46727374 ps
CPU time 0.89 seconds
Started Aug 02 07:24:01 PM PDT 24
Finished Aug 02 07:24:02 PM PDT 24
Peak memory 201096 kb
Host smart-dae5993a-1709-4f49-b836-e3e8c3b0fad1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135706512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.135706512
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.997311873
Short name T410
Test name
Test status
Simulation time 200647049 ps
CPU time 1.69 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:24:13 PM PDT 24
Peak memory 201144 kb
Host smart-9b03268e-0fa9-4dec-9c2c-530d2746f87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997311873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.997311873
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.277415073
Short name T84
Test name
Test status
Simulation time 130651782379 ps
CPU time 789.08 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:37:21 PM PDT 24
Peak memory 217988 kb
Host smart-df6f4683-0a21-436c-a18f-50a2a8e82c3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=277415073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.277415073
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.1430508228
Short name T186
Test name
Test status
Simulation time 80230655 ps
CPU time 1.07 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201084 kb
Host smart-d9228fd5-3bd1-43c0-b8fd-20a2e9c1a30f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430508228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1430508228
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.3586894116
Short name T384
Test name
Test status
Simulation time 50327346 ps
CPU time 0.82 seconds
Started Aug 02 07:24:12 PM PDT 24
Finished Aug 02 07:24:13 PM PDT 24
Peak memory 201096 kb
Host smart-c9c9b51c-4c67-4853-9dfe-2ad769ea1bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586894116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.3586894116
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.1827951762
Short name T724
Test name
Test status
Simulation time 21242743 ps
CPU time 0.85 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201100 kb
Host smart-3bcf0e42-1d24-4f15-b3f0-b26ac3a27ab0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827951762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.1827951762
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.3122288011
Short name T47
Test name
Test status
Simulation time 76781589 ps
CPU time 0.87 seconds
Started Aug 02 07:24:16 PM PDT 24
Finished Aug 02 07:24:18 PM PDT 24
Peak memory 201048 kb
Host smart-271d4da2-ef32-4b25-9c92-ddf9082a0e0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122288011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3122288011
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.4122119577
Short name T688
Test name
Test status
Simulation time 57728021 ps
CPU time 0.93 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 201056 kb
Host smart-a713eb3d-5e8c-482d-85f2-9678da8c5b48
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122119577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.4122119577
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.1716345752
Short name T313
Test name
Test status
Simulation time 25381486 ps
CPU time 0.91 seconds
Started Aug 02 07:24:06 PM PDT 24
Finished Aug 02 07:24:07 PM PDT 24
Peak memory 201152 kb
Host smart-3ce41be9-cd96-4595-8f2e-75179647e109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716345752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1716345752
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.114532669
Short name T17
Test name
Test status
Simulation time 1885955223 ps
CPU time 10.87 seconds
Started Aug 02 07:24:12 PM PDT 24
Finished Aug 02 07:24:23 PM PDT 24
Peak memory 201324 kb
Host smart-37ed0b93-c2c9-4305-aace-85d17a2f92d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114532669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.114532669
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.3206510429
Short name T764
Test name
Test status
Simulation time 1576388407 ps
CPU time 11.56 seconds
Started Aug 02 07:24:07 PM PDT 24
Finished Aug 02 07:24:19 PM PDT 24
Peak memory 201140 kb
Host smart-1a9b6f80-5a7b-4515-a3fe-be2ff4f5c11b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206510429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.3206510429
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.3314691224
Short name T806
Test name
Test status
Simulation time 42824598 ps
CPU time 1.1 seconds
Started Aug 02 07:24:13 PM PDT 24
Finished Aug 02 07:24:14 PM PDT 24
Peak memory 201132 kb
Host smart-df6b4c15-2b86-4c49-8b3c-883aeabac11a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314691224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.3314691224
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2925729851
Short name T326
Test name
Test status
Simulation time 16812172 ps
CPU time 0.75 seconds
Started Aug 02 07:24:04 PM PDT 24
Finished Aug 02 07:24:05 PM PDT 24
Peak memory 200996 kb
Host smart-e3c3b30b-1241-4c42-9f4a-2a6adf61d11b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925729851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.2925729851
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1354842334
Short name T68
Test name
Test status
Simulation time 37118951 ps
CPU time 0.94 seconds
Started Aug 02 07:24:07 PM PDT 24
Finished Aug 02 07:24:08 PM PDT 24
Peak memory 201152 kb
Host smart-11ca6625-d663-4f5e-9ef2-df82ef411cae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354842334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.1354842334
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.2970777421
Short name T449
Test name
Test status
Simulation time 40132719 ps
CPU time 0.79 seconds
Started Aug 02 07:24:06 PM PDT 24
Finished Aug 02 07:24:07 PM PDT 24
Peak memory 201200 kb
Host smart-683e33c9-2477-4f2e-9e84-97f6c983555e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970777421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2970777421
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.1909788966
Short name T350
Test name
Test status
Simulation time 729982766 ps
CPU time 4.64 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:24:16 PM PDT 24
Peak memory 201368 kb
Host smart-6f286d95-fb9f-4ea6-ac6c-a61c5d3b412c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909788966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1909788966
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.2521651198
Short name T636
Test name
Test status
Simulation time 17272242 ps
CPU time 0.82 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:24:12 PM PDT 24
Peak memory 201132 kb
Host smart-a7cbdf24-18cc-4d5e-a7d2-fc9a9800ad85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521651198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.2521651198
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.1207212840
Short name T572
Test name
Test status
Simulation time 6640567407 ps
CPU time 22.91 seconds
Started Aug 02 07:24:07 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201448 kb
Host smart-67f71da7-c8ef-4824-b45a-f8f2cb91a029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207212840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.1207212840
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.1996791273
Short name T668
Test name
Test status
Simulation time 52016018100 ps
CPU time 370.23 seconds
Started Aug 02 07:24:12 PM PDT 24
Finished Aug 02 07:30:22 PM PDT 24
Peak memory 218048 kb
Host smart-78fe2318-4319-4492-8775-8b7808f6208b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1996791273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.1996791273
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_trans.1805416017
Short name T780
Test name
Test status
Simulation time 34543977 ps
CPU time 0.95 seconds
Started Aug 02 07:24:06 PM PDT 24
Finished Aug 02 07:24:08 PM PDT 24
Peak memory 201148 kb
Host smart-94e12ab9-19e8-4425-a710-9c1c4b21c9cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805416017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.1805416017
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.3303747576
Short name T43
Test name
Test status
Simulation time 16336253 ps
CPU time 0.76 seconds
Started Aug 02 07:24:26 PM PDT 24
Finished Aug 02 07:24:27 PM PDT 24
Peak memory 201108 kb
Host smart-df634745-2156-464c-9606-827b9247da6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303747576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.3303747576
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3686507942
Short name T430
Test name
Test status
Simulation time 59634443 ps
CPU time 0.95 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:24:12 PM PDT 24
Peak memory 201112 kb
Host smart-7f1c9099-857b-467d-9882-66e10f7d993b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686507942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.3686507942
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.146860907
Short name T49
Test name
Test status
Simulation time 41308746 ps
CPU time 0.77 seconds
Started Aug 02 07:24:12 PM PDT 24
Finished Aug 02 07:24:13 PM PDT 24
Peak memory 200376 kb
Host smart-12b8b57a-cef9-4f25-bb30-9f4dad07ebe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146860907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.146860907
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.80080935
Short name T725
Test name
Test status
Simulation time 109670139 ps
CPU time 1.27 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:24:13 PM PDT 24
Peak memory 201084 kb
Host smart-4a68e538-c3c4-4e5e-9890-8adbc59a0acd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80080935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.clkmgr_div_intersig_mubi.80080935
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.1632544583
Short name T621
Test name
Test status
Simulation time 27078363 ps
CPU time 0.87 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:24:12 PM PDT 24
Peak memory 201120 kb
Host smart-2af3bfe1-6bfe-4da5-a0fd-9db0028f9163
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632544583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1632544583
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.2727419051
Short name T339
Test name
Test status
Simulation time 2494346916 ps
CPU time 10.21 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:24:21 PM PDT 24
Peak memory 201504 kb
Host smart-3b3bda4f-8025-48dc-91ea-6c42fa5a3943
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727419051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2727419051
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.1221122250
Short name T530
Test name
Test status
Simulation time 2162769037 ps
CPU time 8.44 seconds
Started Aug 02 07:24:06 PM PDT 24
Finished Aug 02 07:24:14 PM PDT 24
Peak memory 201460 kb
Host smart-57f56dac-299d-4549-91ef-ebc2ddf2772d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221122250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.1221122250
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.1260581567
Short name T476
Test name
Test status
Simulation time 20906894 ps
CPU time 0.83 seconds
Started Aug 02 07:24:10 PM PDT 24
Finished Aug 02 07:24:11 PM PDT 24
Peak memory 201168 kb
Host smart-6b9c78bf-4d88-47e3-a7f3-26fee6025608
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260581567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.1260581567
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2607235826
Short name T175
Test name
Test status
Simulation time 44603883 ps
CPU time 0.82 seconds
Started Aug 02 07:24:11 PM PDT 24
Finished Aug 02 07:24:11 PM PDT 24
Peak memory 201180 kb
Host smart-0618ce9d-641c-46b3-a287-6360569f20a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607235826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2607235826
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.696286764
Short name T554
Test name
Test status
Simulation time 75646354 ps
CPU time 1 seconds
Started Aug 02 07:24:16 PM PDT 24
Finished Aug 02 07:24:17 PM PDT 24
Peak memory 201132 kb
Host smart-27e2bddf-1788-47d8-90f9-a68527dcbfcc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696286764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.clkmgr_lc_ctrl_intersig_mubi.696286764
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.3138424839
Short name T212
Test name
Test status
Simulation time 55844046 ps
CPU time 0.86 seconds
Started Aug 02 07:24:10 PM PDT 24
Finished Aug 02 07:24:11 PM PDT 24
Peak memory 201088 kb
Host smart-4ef1b566-2787-4886-8931-d6ef131f40c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138424839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.3138424839
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.1059359064
Short name T703
Test name
Test status
Simulation time 105716179 ps
CPU time 1.06 seconds
Started Aug 02 07:24:12 PM PDT 24
Finished Aug 02 07:24:14 PM PDT 24
Peak memory 201132 kb
Host smart-be5d3ae8-14a4-442f-bb80-95d9f49a96c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059359064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1059359064
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.3538724386
Short name T541
Test name
Test status
Simulation time 8322541258 ps
CPU time 39.61 seconds
Started Aug 02 07:24:13 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201484 kb
Host smart-78f35a4a-fc05-48d0-bfd7-6e1bb44ac5be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538724386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.3538724386
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.4196553536
Short name T321
Test name
Test status
Simulation time 78992778 ps
CPU time 1.04 seconds
Started Aug 02 07:24:16 PM PDT 24
Finished Aug 02 07:24:18 PM PDT 24
Peak memory 201132 kb
Host smart-b166e6da-c363-4972-bb68-7e7379cae24c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196553536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.4196553536
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.1256570375
Short name T259
Test name
Test status
Simulation time 19028369 ps
CPU time 0.78 seconds
Started Aug 02 07:22:14 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201100 kb
Host smart-a071f757-db8f-4241-b997-2aa28eb17edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256570375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.1256570375
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.3383535735
Short name T306
Test name
Test status
Simulation time 31200082 ps
CPU time 0.78 seconds
Started Aug 02 07:22:05 PM PDT 24
Finished Aug 02 07:22:06 PM PDT 24
Peak memory 201124 kb
Host smart-40721f72-8a17-4b02-86dd-f4d3af0be6ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383535735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.3383535735
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.3120814578
Short name T519
Test name
Test status
Simulation time 13155747 ps
CPU time 0.69 seconds
Started Aug 02 07:22:15 PM PDT 24
Finished Aug 02 07:22:15 PM PDT 24
Peak memory 200412 kb
Host smart-e818ced2-9abe-4e44-977d-c193471d4b39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120814578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.3120814578
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.572957541
Short name T180
Test name
Test status
Simulation time 85593709 ps
CPU time 1.08 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201084 kb
Host smart-d8193feb-58d7-4af9-a93e-f3fa5d95b859
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572957541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.clkmgr_div_intersig_mubi.572957541
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.4099504198
Short name T282
Test name
Test status
Simulation time 22269789 ps
CPU time 0.84 seconds
Started Aug 02 07:22:12 PM PDT 24
Finished Aug 02 07:22:13 PM PDT 24
Peak memory 201136 kb
Host smart-422da28b-4315-4b85-b9b4-1ee06c17ffee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099504198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.4099504198
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.1570866261
Short name T589
Test name
Test status
Simulation time 561064849 ps
CPU time 4.83 seconds
Started Aug 02 07:22:15 PM PDT 24
Finished Aug 02 07:22:20 PM PDT 24
Peak memory 201264 kb
Host smart-d34408d7-1a44-4f18-9411-6a540d2fe2c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570866261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.1570866261
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.3113529625
Short name T289
Test name
Test status
Simulation time 138099118 ps
CPU time 1.36 seconds
Started Aug 02 07:22:12 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201172 kb
Host smart-2bfa5df0-1d4c-4466-89ec-fc89d70bf134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113529625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.3113529625
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3981225025
Short name T763
Test name
Test status
Simulation time 95451207 ps
CPU time 1.21 seconds
Started Aug 02 07:22:09 PM PDT 24
Finished Aug 02 07:22:10 PM PDT 24
Peak memory 201080 kb
Host smart-d3dda3de-4e39-4df7-94cb-5fd53335e24c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981225025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.3981225025
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.4218378156
Short name T257
Test name
Test status
Simulation time 23014246 ps
CPU time 0.86 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:14 PM PDT 24
Peak memory 201120 kb
Host smart-655cf79c-3eb6-4686-aab7-1a1d61ac5a37
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218378156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.4218378156
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.339239829
Short name T307
Test name
Test status
Simulation time 20258267 ps
CPU time 0.84 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:12 PM PDT 24
Peak memory 201156 kb
Host smart-cb837132-756c-48bd-b92e-44aea4c74312
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339239829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_ctrl_intersig_mubi.339239829
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.2419496963
Short name T263
Test name
Test status
Simulation time 14437764 ps
CPU time 0.7 seconds
Started Aug 02 07:22:18 PM PDT 24
Finished Aug 02 07:22:19 PM PDT 24
Peak memory 201072 kb
Host smart-3b6d1e4e-4999-46bc-a3c8-69e95ff63609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419496963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.2419496963
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.2555698116
Short name T64
Test name
Test status
Simulation time 781370208 ps
CPU time 4.07 seconds
Started Aug 02 07:22:09 PM PDT 24
Finished Aug 02 07:22:13 PM PDT 24
Peak memory 217956 kb
Host smart-0c7288d4-e29e-4191-8edd-83a1f8d42365
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555698116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.2555698116
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.1230958045
Short name T157
Test name
Test status
Simulation time 31640540 ps
CPU time 0.9 seconds
Started Aug 02 07:22:15 PM PDT 24
Finished Aug 02 07:22:16 PM PDT 24
Peak memory 201204 kb
Host smart-2036c165-3975-4d9f-8bfd-3f5a1f2d726e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230958045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.1230958045
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.3550325520
Short name T216
Test name
Test status
Simulation time 6394199734 ps
CPU time 23.31 seconds
Started Aug 02 07:22:13 PM PDT 24
Finished Aug 02 07:22:36 PM PDT 24
Peak memory 201504 kb
Host smart-e86654b3-7644-4127-a334-1b37209764d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550325520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.3550325520
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.3775694541
Short name T273
Test name
Test status
Simulation time 134920157 ps
CPU time 1.23 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:12 PM PDT 24
Peak memory 201144 kb
Host smart-825c2b59-4368-4b9f-b477-17e313409b47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775694541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3775694541
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1305241893
Short name T698
Test name
Test status
Simulation time 35186501 ps
CPU time 0.78 seconds
Started Aug 02 07:24:18 PM PDT 24
Finished Aug 02 07:24:19 PM PDT 24
Peak memory 201084 kb
Host smart-e4bb9843-3146-4575-801c-d3df83bfbf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305241893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1305241893
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.2852144587
Short name T122
Test name
Test status
Simulation time 52096555 ps
CPU time 1 seconds
Started Aug 02 07:24:25 PM PDT 24
Finished Aug 02 07:24:26 PM PDT 24
Peak memory 201116 kb
Host smart-1309a9e8-01de-4ac2-afbc-af1ef60a8a9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852144587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.2852144587
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.2572961092
Short name T172
Test name
Test status
Simulation time 97579193 ps
CPU time 0.96 seconds
Started Aug 02 07:24:19 PM PDT 24
Finished Aug 02 07:24:20 PM PDT 24
Peak memory 201020 kb
Host smart-899f4175-c091-4309-ae6f-aa802626decc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572961092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2572961092
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.4012286866
Short name T420
Test name
Test status
Simulation time 43786345 ps
CPU time 0.96 seconds
Started Aug 02 07:24:19 PM PDT 24
Finished Aug 02 07:24:20 PM PDT 24
Peak memory 201096 kb
Host smart-958d8815-f770-40b8-b9b9-a66e119e73ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012286866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.4012286866
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.1073279563
Short name T709
Test name
Test status
Simulation time 18271832 ps
CPU time 0.79 seconds
Started Aug 02 07:24:20 PM PDT 24
Finished Aug 02 07:24:21 PM PDT 24
Peak memory 201120 kb
Host smart-980ea4e8-0a81-49ec-8033-6e2902a1aa87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073279563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1073279563
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.2545454001
Short name T372
Test name
Test status
Simulation time 1161030907 ps
CPU time 9.82 seconds
Started Aug 02 07:24:21 PM PDT 24
Finished Aug 02 07:24:31 PM PDT 24
Peak memory 201180 kb
Host smart-eecf1e9f-819d-404d-ac82-85cac1d49684
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545454001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2545454001
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.4122561978
Short name T373
Test name
Test status
Simulation time 258267761 ps
CPU time 2.39 seconds
Started Aug 02 07:24:19 PM PDT 24
Finished Aug 02 07:24:22 PM PDT 24
Peak memory 201204 kb
Host smart-c2e2ae9b-4df7-4655-8c10-ba9e9a75222b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122561978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.4122561978
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.3663061278
Short name T207
Test name
Test status
Simulation time 31129057 ps
CPU time 1.01 seconds
Started Aug 02 07:24:19 PM PDT 24
Finished Aug 02 07:24:20 PM PDT 24
Peak memory 201064 kb
Host smart-63709b88-1e0a-40f1-b009-c0a8357f7881
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663061278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.3663061278
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1464284180
Short name T341
Test name
Test status
Simulation time 106553346 ps
CPU time 1.06 seconds
Started Aug 02 07:24:18 PM PDT 24
Finished Aug 02 07:24:19 PM PDT 24
Peak memory 200996 kb
Host smart-e7b2d4ff-fb3a-447d-9b72-fa488540eb46
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464284180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.1464284180
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3600630693
Short name T778
Test name
Test status
Simulation time 46464588 ps
CPU time 0.95 seconds
Started Aug 02 07:24:14 PM PDT 24
Finished Aug 02 07:24:15 PM PDT 24
Peak memory 201076 kb
Host smart-51a4b309-d011-43ac-b828-0f10398446bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600630693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.3600630693
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.146601776
Short name T101
Test name
Test status
Simulation time 12561599 ps
CPU time 0.73 seconds
Started Aug 02 07:24:17 PM PDT 24
Finished Aug 02 07:24:18 PM PDT 24
Peak memory 201044 kb
Host smart-7cbc8800-f1eb-45ba-88f8-5c9c0e27347b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146601776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.146601776
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.977379181
Short name T489
Test name
Test status
Simulation time 913494901 ps
CPU time 3.71 seconds
Started Aug 02 07:24:21 PM PDT 24
Finished Aug 02 07:24:25 PM PDT 24
Peak memory 201332 kb
Host smart-dbb77f76-28b3-4cce-b7c5-e464cd0edf5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977379181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.977379181
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.3089628882
Short name T422
Test name
Test status
Simulation time 24499026 ps
CPU time 0.85 seconds
Started Aug 02 07:24:21 PM PDT 24
Finished Aug 02 07:24:22 PM PDT 24
Peak memory 201120 kb
Host smart-4f0c5473-d3a2-483a-8ddc-13b87538ea87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089628882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3089628882
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.1713166239
Short name T658
Test name
Test status
Simulation time 922126712 ps
CPU time 5.48 seconds
Started Aug 02 07:24:21 PM PDT 24
Finished Aug 02 07:24:27 PM PDT 24
Peak memory 201208 kb
Host smart-08b8659e-7bc3-46c1-8e47-cb3b93a2d642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713166239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.1713166239
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.1871697546
Short name T353
Test name
Test status
Simulation time 136421812 ps
CPU time 1.35 seconds
Started Aug 02 07:24:17 PM PDT 24
Finished Aug 02 07:24:19 PM PDT 24
Peak memory 201028 kb
Host smart-c979c441-3090-4194-ae08-3923562b7418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871697546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1871697546
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.3115563188
Short name T717
Test name
Test status
Simulation time 17667122 ps
CPU time 0.79 seconds
Started Aug 02 07:24:32 PM PDT 24
Finished Aug 02 07:24:33 PM PDT 24
Peak memory 201168 kb
Host smart-f23a4f8e-29ab-45a4-b814-73bd0503bdc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115563188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.3115563188
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2599777805
Short name T118
Test name
Test status
Simulation time 62132482 ps
CPU time 0.92 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:24:28 PM PDT 24
Peak memory 201108 kb
Host smart-2d4199ae-1a14-4550-a6b6-f4e2a05d4645
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599777805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.2599777805
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.2295694753
Short name T421
Test name
Test status
Simulation time 29233532 ps
CPU time 0.76 seconds
Started Aug 02 07:24:19 PM PDT 24
Finished Aug 02 07:24:20 PM PDT 24
Peak memory 200312 kb
Host smart-d36f63c9-76c6-429d-b8be-8997f8d89699
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295694753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2295694753
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.2994312128
Short name T197
Test name
Test status
Simulation time 23043101 ps
CPU time 0.85 seconds
Started Aug 02 07:24:29 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201060 kb
Host smart-8b1e2b5a-5e42-451f-b828-c55da0f58067
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994312128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.2994312128
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.3892846910
Short name T791
Test name
Test status
Simulation time 41302342 ps
CPU time 0.96 seconds
Started Aug 02 07:24:17 PM PDT 24
Finished Aug 02 07:24:19 PM PDT 24
Peak memory 201092 kb
Host smart-fa05b4b5-87e0-4747-a163-c950632f37ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892846910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3892846910
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.1970777891
Short name T358
Test name
Test status
Simulation time 2234316456 ps
CPU time 17.44 seconds
Started Aug 02 07:24:21 PM PDT 24
Finished Aug 02 07:24:38 PM PDT 24
Peak memory 201412 kb
Host smart-6eadcb89-7dc2-4846-b1c7-c472571f9e5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970777891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1970777891
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.1416707476
Short name T596
Test name
Test status
Simulation time 134141981 ps
CPU time 1.57 seconds
Started Aug 02 07:24:22 PM PDT 24
Finished Aug 02 07:24:24 PM PDT 24
Peak memory 201204 kb
Host smart-65f10b88-1788-4a00-a84a-d5a53d3e89cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416707476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.1416707476
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.3926502038
Short name T226
Test name
Test status
Simulation time 669454466 ps
CPU time 2.86 seconds
Started Aug 02 07:24:20 PM PDT 24
Finished Aug 02 07:24:23 PM PDT 24
Peak memory 201052 kb
Host smart-2b26431b-3be5-40d8-9b5a-d152a49c0a66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926502038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.3926502038
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3691682847
Short name T309
Test name
Test status
Simulation time 26612864 ps
CPU time 0.88 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:29 PM PDT 24
Peak memory 201088 kb
Host smart-f127551d-7b15-48d9-8c97-bf7ebf49aaed
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691682847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.3691682847
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2984548373
Short name T498
Test name
Test status
Simulation time 23544403 ps
CPU time 0.78 seconds
Started Aug 02 07:24:18 PM PDT 24
Finished Aug 02 07:24:19 PM PDT 24
Peak memory 201100 kb
Host smart-95b2a762-f791-4893-9f57-35299980abab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984548373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.2984548373
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.2964131848
Short name T745
Test name
Test status
Simulation time 180435218 ps
CPU time 1.35 seconds
Started Aug 02 07:24:21 PM PDT 24
Finished Aug 02 07:24:22 PM PDT 24
Peak memory 201068 kb
Host smart-fae39b11-7e27-45f3-b1d3-0c6ff6c6f4fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964131848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.2964131848
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.2267903887
Short name T619
Test name
Test status
Simulation time 636567869 ps
CPU time 3.91 seconds
Started Aug 02 07:24:26 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201288 kb
Host smart-9f09e651-0aac-4192-a90e-92d85d12f270
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267903887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.2267903887
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.2342995829
Short name T723
Test name
Test status
Simulation time 18756539 ps
CPU time 0.83 seconds
Started Aug 02 07:24:22 PM PDT 24
Finished Aug 02 07:24:23 PM PDT 24
Peak memory 201072 kb
Host smart-5de1b5b9-000f-4047-ba0f-8e49febab8cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342995829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.2342995829
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.1214854503
Short name T664
Test name
Test status
Simulation time 8140929251 ps
CPU time 57.08 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201452 kb
Host smart-5c380f9d-e796-42d8-b3f2-358fe213629a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214854503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.1214854503
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.1643201518
Short name T87
Test name
Test status
Simulation time 89180614789 ps
CPU time 436.64 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:31:45 PM PDT 24
Peak memory 218020 kb
Host smart-6640276b-6a65-4347-b2e5-5465d021f353
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1643201518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.1643201518
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.2247734689
Short name T513
Test name
Test status
Simulation time 32548622 ps
CPU time 0.96 seconds
Started Aug 02 07:24:16 PM PDT 24
Finished Aug 02 07:24:17 PM PDT 24
Peak memory 201064 kb
Host smart-1c37d027-7204-46ab-bd65-8949fa61fcbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247734689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.2247734689
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.3669783196
Short name T95
Test name
Test status
Simulation time 17161406 ps
CPU time 0.79 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:24:28 PM PDT 24
Peak memory 201092 kb
Host smart-7b6f92d0-45c5-47ee-aa0d-d8c3dbd1ce4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669783196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.3669783196
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.177762171
Short name T741
Test name
Test status
Simulation time 39480876 ps
CPU time 0.92 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:24:28 PM PDT 24
Peak memory 201016 kb
Host smart-3b280841-d5ee-4546-a90a-8973e526e142
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177762171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.177762171
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.1570097328
Short name T284
Test name
Test status
Simulation time 45375611 ps
CPU time 0.78 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:29 PM PDT 24
Peak memory 200296 kb
Host smart-2826a822-926a-4531-a0ba-a247212884d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570097328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1570097328
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.1090182316
Short name T560
Test name
Test status
Simulation time 324068705 ps
CPU time 1.72 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201164 kb
Host smart-ca1a76ac-5c77-4023-b37a-c9c7235860b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090182316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.1090182316
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.2614580304
Short name T684
Test name
Test status
Simulation time 37144061 ps
CPU time 0.9 seconds
Started Aug 02 07:24:29 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201100 kb
Host smart-7ef83d50-d36c-4044-b539-242104db5bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614580304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2614580304
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.1250760601
Short name T475
Test name
Test status
Simulation time 1641435355 ps
CPU time 13.32 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:24:41 PM PDT 24
Peak memory 201156 kb
Host smart-9ddfc855-c88c-4a1c-857f-079bc54309cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250760601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1250760601
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.3354145427
Short name T461
Test name
Test status
Simulation time 143473876 ps
CPU time 1.41 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201192 kb
Host smart-e80aa88a-5bc1-4614-baac-48682888ba0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354145427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.3354145427
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.1581803405
Short name T481
Test name
Test status
Simulation time 37313343 ps
CPU time 0.78 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:24:28 PM PDT 24
Peak memory 201068 kb
Host smart-b24eda74-0163-45af-ad7d-a77c74679f5e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581803405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.1581803405
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.131291576
Short name T285
Test name
Test status
Simulation time 20203178 ps
CPU time 0.8 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:29 PM PDT 24
Peak memory 201108 kb
Host smart-3f900dc7-292a-429d-b5b8-c597747b728b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131291576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_clk_byp_req_intersig_mubi.131291576
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3630210047
Short name T240
Test name
Test status
Simulation time 16875713 ps
CPU time 0.78 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:24:28 PM PDT 24
Peak memory 201112 kb
Host smart-8a0c3e18-c0c1-4b31-8e2f-70b5728f0efe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630210047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.3630210047
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.43276116
Short name T302
Test name
Test status
Simulation time 17338575 ps
CPU time 0.81 seconds
Started Aug 02 07:24:26 PM PDT 24
Finished Aug 02 07:24:27 PM PDT 24
Peak memory 201072 kb
Host smart-e23350a6-80cc-4faa-80fc-035946499bfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43276116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.43276116
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.3049353862
Short name T450
Test name
Test status
Simulation time 631156372 ps
CPU time 2.6 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201240 kb
Host smart-a64fae5d-792e-40d6-b588-a52cc530852c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049353862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3049353862
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.902787377
Short name T327
Test name
Test status
Simulation time 147515736 ps
CPU time 1.25 seconds
Started Aug 02 07:24:29 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201068 kb
Host smart-18ca3d8a-b5ee-4c4d-93e4-83e0119e2688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902787377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.902787377
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.3049032436
Short name T546
Test name
Test status
Simulation time 2020253118 ps
CPU time 15.39 seconds
Started Aug 02 07:24:24 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201388 kb
Host smart-b850eb7d-3761-4213-ab97-40b0ca01b1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049032436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.3049032436
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.210704425
Short name T86
Test name
Test status
Simulation time 126624309888 ps
CPU time 861.8 seconds
Started Aug 02 07:24:29 PM PDT 24
Finished Aug 02 07:38:51 PM PDT 24
Peak memory 209832 kb
Host smart-b94898aa-0918-4f44-ab8c-9885c26d93ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=210704425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.210704425
Directory /workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_trans.4204056172
Short name T699
Test name
Test status
Simulation time 33175953 ps
CPU time 0.97 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:29 PM PDT 24
Peak memory 201148 kb
Host smart-067b1314-1507-482c-a232-01dc58edb700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204056172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.4204056172
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.1115621711
Short name T252
Test name
Test status
Simulation time 29317251 ps
CPU time 0.83 seconds
Started Aug 02 07:24:41 PM PDT 24
Finished Aug 02 07:24:42 PM PDT 24
Peak memory 201116 kb
Host smart-29a4a720-a587-43fd-ad74-a9096f1c1fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115621711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.1115621711
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.2487826797
Short name T783
Test name
Test status
Simulation time 14266696 ps
CPU time 0.75 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:24:28 PM PDT 24
Peak memory 201120 kb
Host smart-e43d7d64-1ea3-4231-ad10-252f3413993d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487826797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.2487826797
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.3693073792
Short name T297
Test name
Test status
Simulation time 72390654 ps
CPU time 0.82 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:29 PM PDT 24
Peak memory 200296 kb
Host smart-3b97c899-c132-46f7-b284-53203fae9be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693073792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.3693073792
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.2057371568
Short name T432
Test name
Test status
Simulation time 30595343 ps
CPU time 0.91 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:29 PM PDT 24
Peak memory 201052 kb
Host smart-83563f85-2825-4757-b0d9-e911de72abc6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057371568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.2057371568
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.3505412457
Short name T102
Test name
Test status
Simulation time 29101640 ps
CPU time 0.93 seconds
Started Aug 02 07:24:29 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201128 kb
Host smart-de3fb4ca-5828-4082-bf67-5dc6e6e728e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505412457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.3505412457
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.296479252
Short name T248
Test name
Test status
Simulation time 330328070 ps
CPU time 2.4 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:31 PM PDT 24
Peak memory 201212 kb
Host smart-865ddea2-2ed8-4a7c-bf64-e50379466c6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296479252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.296479252
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.2752581950
Short name T695
Test name
Test status
Simulation time 1223616141 ps
CPU time 6.6 seconds
Started Aug 02 07:24:31 PM PDT 24
Finished Aug 02 07:24:38 PM PDT 24
Peak memory 201252 kb
Host smart-7020c3f8-d153-40db-8232-e97e41ffba55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752581950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.2752581950
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.44002472
Short name T480
Test name
Test status
Simulation time 39767597 ps
CPU time 1.06 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201060 kb
Host smart-8b5b9bb4-4736-4133-974a-a2272a522eb0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44002472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.clkmgr_idle_intersig_mubi.44002472
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1620569382
Short name T62
Test name
Test status
Simulation time 14353476 ps
CPU time 0.73 seconds
Started Aug 02 07:24:31 PM PDT 24
Finished Aug 02 07:24:32 PM PDT 24
Peak memory 201172 kb
Host smart-0bc1f772-08c5-4bf2-9f32-93791b5be104
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620569382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.1620569382
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1572279393
Short name T583
Test name
Test status
Simulation time 25777125 ps
CPU time 0.76 seconds
Started Aug 02 07:24:27 PM PDT 24
Finished Aug 02 07:24:28 PM PDT 24
Peak memory 201088 kb
Host smart-9d42f639-5c64-4f87-84c5-27021503993a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572279393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1572279393
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.1408188542
Short name T543
Test name
Test status
Simulation time 37436345 ps
CPU time 0.79 seconds
Started Aug 02 07:24:29 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201096 kb
Host smart-9983ba4c-8dbf-44c8-bef7-ebba100707ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408188542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1408188542
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.3196144203
Short name T590
Test name
Test status
Simulation time 1195640221 ps
CPU time 4.63 seconds
Started Aug 02 07:24:31 PM PDT 24
Finished Aug 02 07:24:36 PM PDT 24
Peak memory 201352 kb
Host smart-f3f3142d-994c-4161-ba72-4caab472e437
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196144203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.3196144203
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.3782687036
Short name T809
Test name
Test status
Simulation time 18757043 ps
CPU time 0.81 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:24:29 PM PDT 24
Peak memory 201120 kb
Host smart-92daeeba-de07-4450-90ec-25c61712d7c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782687036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.3782687036
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.1733598921
Short name T706
Test name
Test status
Simulation time 8366956822 ps
CPU time 61.08 seconds
Started Aug 02 07:24:42 PM PDT 24
Finished Aug 02 07:25:43 PM PDT 24
Peak memory 200804 kb
Host smart-439d9883-b519-4d37-87bd-7a48e54b1e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733598921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.1733598921
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.1905259560
Short name T51
Test name
Test status
Simulation time 22841442676 ps
CPU time 218.16 seconds
Started Aug 02 07:24:28 PM PDT 24
Finished Aug 02 07:28:07 PM PDT 24
Peak memory 218016 kb
Host smart-4b9a9cd9-ccfd-4f7c-955f-e84a32fd4d14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1905259560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.1905259560
Directory /workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.clkmgr_trans.1556810178
Short name T351
Test name
Test status
Simulation time 19549089 ps
CPU time 0.8 seconds
Started Aug 02 07:24:29 PM PDT 24
Finished Aug 02 07:24:30 PM PDT 24
Peak memory 201140 kb
Host smart-ead4185c-fe87-409b-9663-5419b06f1a72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556810178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.1556810178
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.3881020010
Short name T818
Test name
Test status
Simulation time 38126699 ps
CPU time 0.84 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:39 PM PDT 24
Peak memory 201136 kb
Host smart-2ddbb461-2999-4316-919e-71b34a0fb7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881020010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.3881020010
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.159479301
Short name T237
Test name
Test status
Simulation time 18357409 ps
CPU time 0.83 seconds
Started Aug 02 07:24:41 PM PDT 24
Finished Aug 02 07:24:42 PM PDT 24
Peak memory 201172 kb
Host smart-fac19b40-d8b0-46cc-bb91-777d0734527a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159479301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.159479301
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.3814262885
Short name T365
Test name
Test status
Simulation time 14682532 ps
CPU time 0.71 seconds
Started Aug 02 07:24:37 PM PDT 24
Finished Aug 02 07:24:37 PM PDT 24
Peak memory 200372 kb
Host smart-02e05762-b2e2-473f-acbd-8e32e882bdcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814262885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.3814262885
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.4213400290
Short name T789
Test name
Test status
Simulation time 52145286 ps
CPU time 0.88 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201068 kb
Host smart-19b553c5-0d23-4ce7-baa5-e9d4dcc2305f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213400290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.4213400290
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.2198864965
Short name T762
Test name
Test status
Simulation time 46259054 ps
CPU time 0.97 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201076 kb
Host smart-156e908b-1fd6-4aaf-805e-91162f568caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198864965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.2198864965
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.56607008
Short name T337
Test name
Test status
Simulation time 2482499299 ps
CPU time 20.16 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:58 PM PDT 24
Peak memory 201404 kb
Host smart-21c6f05c-f056-470d-b303-d01796139fe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56607008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.56607008
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.1857627611
Short name T662
Test name
Test status
Simulation time 257266288 ps
CPU time 2.59 seconds
Started Aug 02 07:24:40 PM PDT 24
Finished Aug 02 07:24:43 PM PDT 24
Peak memory 201276 kb
Host smart-42a5c8f2-0721-4862-9daf-69cf183931fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857627611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.1857627611
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.2290209039
Short name T303
Test name
Test status
Simulation time 30540351 ps
CPU time 0.98 seconds
Started Aug 02 07:24:41 PM PDT 24
Finished Aug 02 07:24:42 PM PDT 24
Peak memory 201064 kb
Host smart-6c484e7c-4c45-40e1-9576-040155774d9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290209039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.2290209039
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.834905386
Short name T484
Test name
Test status
Simulation time 28316052 ps
CPU time 0.81 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:39 PM PDT 24
Peak memory 201040 kb
Host smart-ad5f11c8-a180-4dec-89d6-1a74dd816d19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834905386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_clk_byp_req_intersig_mubi.834905386
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.4217130828
Short name T332
Test name
Test status
Simulation time 51735395 ps
CPU time 1.01 seconds
Started Aug 02 07:24:37 PM PDT 24
Finished Aug 02 07:24:38 PM PDT 24
Peak memory 201120 kb
Host smart-b63c4799-cc35-43d9-ad4a-6903c9d0db83
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217130828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.4217130828
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.4077751624
Short name T30
Test name
Test status
Simulation time 20419624 ps
CPU time 0.74 seconds
Started Aug 02 07:24:41 PM PDT 24
Finished Aug 02 07:24:41 PM PDT 24
Peak memory 201088 kb
Host smart-26c513b1-ac86-4b1c-b83c-2fe52e577850
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077751624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.4077751624
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.2354590303
Short name T568
Test name
Test status
Simulation time 1035008689 ps
CPU time 5.64 seconds
Started Aug 02 07:24:40 PM PDT 24
Finished Aug 02 07:24:46 PM PDT 24
Peak memory 201360 kb
Host smart-d014816d-af84-4212-9571-193f2f3dc12d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354590303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2354590303
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.4178412186
Short name T547
Test name
Test status
Simulation time 17649400 ps
CPU time 0.81 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201036 kb
Host smart-9a35a88f-3852-4783-93e4-175f672949f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178412186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.4178412186
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.227093315
Short name T701
Test name
Test status
Simulation time 85994434 ps
CPU time 1.02 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201052 kb
Host smart-b176c53b-7a18-4221-843b-fc212cfade35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227093315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.227093315
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.4056579906
Short name T520
Test name
Test status
Simulation time 19837914 ps
CPU time 0.8 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201080 kb
Host smart-9d23f855-5a0b-4959-a55b-1a2614243ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056579906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.4056579906
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.1929354784
Short name T808
Test name
Test status
Simulation time 77020310 ps
CPU time 1 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201060 kb
Host smart-bf417ea6-c205-41f1-8721-09058d21c557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929354784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.1929354784
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.1415908998
Short name T67
Test name
Test status
Simulation time 47368256 ps
CPU time 0.93 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201084 kb
Host smart-9b612032-b812-451b-89f8-c3b999964a6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415908998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.1415908998
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.3587162963
Short name T788
Test name
Test status
Simulation time 16613915 ps
CPU time 0.74 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:38 PM PDT 24
Peak memory 200992 kb
Host smart-2a9e9b5d-5dad-488c-8874-8592ee321e3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587162963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.3587162963
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.1257781328
Short name T395
Test name
Test status
Simulation time 16257821 ps
CPU time 0.73 seconds
Started Aug 02 07:24:43 PM PDT 24
Finished Aug 02 07:24:44 PM PDT 24
Peak memory 200824 kb
Host smart-2addd377-c0a7-4ffc-aed0-f7a9e5267b4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257781328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.1257781328
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.3429230932
Short name T335
Test name
Test status
Simulation time 101480726 ps
CPU time 1.12 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:39 PM PDT 24
Peak memory 201128 kb
Host smart-d350d254-21bf-4790-8ba9-9ccf756de68c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429230932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3429230932
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.1967022169
Short name T508
Test name
Test status
Simulation time 1520910488 ps
CPU time 10.22 seconds
Started Aug 02 07:24:41 PM PDT 24
Finished Aug 02 07:24:51 PM PDT 24
Peak memory 201236 kb
Host smart-c5cd7624-0db1-4a05-87ba-c5ac67bd56da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967022169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1967022169
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.3079908811
Short name T666
Test name
Test status
Simulation time 1287863378 ps
CPU time 5.3 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:45 PM PDT 24
Peak memory 201216 kb
Host smart-7dd321eb-4057-449a-bbdc-0b4eaa5a65bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079908811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.3079908811
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.2645883906
Short name T645
Test name
Test status
Simulation time 57796270 ps
CPU time 0.91 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:39 PM PDT 24
Peak memory 201100 kb
Host smart-fdcaad87-30a0-4e06-a26e-deeda948d450
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645883906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.2645883906
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.1789150375
Short name T142
Test name
Test status
Simulation time 24498131 ps
CPU time 0.84 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:38 PM PDT 24
Peak memory 201060 kb
Host smart-07846239-1562-4451-a43e-9efc047bfcf7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789150375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.1789150375
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.325067708
Short name T729
Test name
Test status
Simulation time 22439758 ps
CPU time 0.84 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201100 kb
Host smart-4d5facd1-28ec-42ea-8c29-23fbcebd2688
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325067708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.clkmgr_lc_ctrl_intersig_mubi.325067708
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.3613436720
Short name T657
Test name
Test status
Simulation time 24716933 ps
CPU time 0.79 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201060 kb
Host smart-b4df62df-df1f-43c9-a954-10fe62fd65b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613436720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.3613436720
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.3621405270
Short name T426
Test name
Test status
Simulation time 349558084 ps
CPU time 1.68 seconds
Started Aug 02 07:24:41 PM PDT 24
Finished Aug 02 07:24:43 PM PDT 24
Peak memory 201128 kb
Host smart-d8b1678e-e054-47d9-b999-7346d8280962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621405270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3621405270
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.3394462718
Short name T490
Test name
Test status
Simulation time 18406380 ps
CPU time 0.83 seconds
Started Aug 02 07:24:39 PM PDT 24
Finished Aug 02 07:24:40 PM PDT 24
Peak memory 201084 kb
Host smart-241272b8-2cfc-4a29-8c5e-91f46a966275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394462718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.3394462718
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.3632622115
Short name T63
Test name
Test status
Simulation time 11943442801 ps
CPU time 48.15 seconds
Started Aug 02 07:24:37 PM PDT 24
Finished Aug 02 07:25:25 PM PDT 24
Peak memory 201444 kb
Host smart-a0e3d5a6-d7e2-4c6e-a61a-c2463fdd1258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632622115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.3632622115
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.4243887213
Short name T103
Test name
Test status
Simulation time 80354224 ps
CPU time 1.05 seconds
Started Aug 02 07:24:40 PM PDT 24
Finished Aug 02 07:24:41 PM PDT 24
Peak memory 201112 kb
Host smart-ca4e2643-ea5e-4f13-9987-930731354633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243887213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.4243887213
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.3567312554
Short name T294
Test name
Test status
Simulation time 26192786 ps
CPU time 0.79 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:24:51 PM PDT 24
Peak memory 201040 kb
Host smart-ef685340-56a6-4273-81b1-6574df64596a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567312554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.3567312554
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.2181565506
Short name T235
Test name
Test status
Simulation time 17376976 ps
CPU time 0.74 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:54 PM PDT 24
Peak memory 201096 kb
Host smart-8f7436bc-bac5-4f2a-8e08-3b656e0ffb41
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181565506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.2181565506
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.1223856730
Short name T170
Test name
Test status
Simulation time 23735131 ps
CPU time 0.7 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 200296 kb
Host smart-b466cfe8-2cc8-4bfe-a08e-0d0d2bcea318
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223856730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1223856730
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.4165609983
Short name T555
Test name
Test status
Simulation time 26368862 ps
CPU time 0.84 seconds
Started Aug 02 07:24:47 PM PDT 24
Finished Aug 02 07:24:48 PM PDT 24
Peak memory 201096 kb
Host smart-a5d6c4c4-7520-417a-9ead-da968ed7ab03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165609983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.4165609983
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.2685462163
Short name T494
Test name
Test status
Simulation time 27711618 ps
CPU time 0.93 seconds
Started Aug 02 07:24:43 PM PDT 24
Finished Aug 02 07:24:44 PM PDT 24
Peak memory 200864 kb
Host smart-eb47164d-3b86-483e-b73d-2244245d76a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685462163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2685462163
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.2561416537
Short name T412
Test name
Test status
Simulation time 1156439358 ps
CPU time 9.46 seconds
Started Aug 02 07:24:42 PM PDT 24
Finished Aug 02 07:24:51 PM PDT 24
Peak memory 200576 kb
Host smart-68742565-9130-4e92-a896-e86778388af8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561416537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.2561416537
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.2193579219
Short name T595
Test name
Test status
Simulation time 1841886820 ps
CPU time 7.66 seconds
Started Aug 02 07:24:40 PM PDT 24
Finished Aug 02 07:24:48 PM PDT 24
Peak memory 201240 kb
Host smart-abdfa2d5-2180-43b1-bca2-45cfc92b21d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193579219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.2193579219
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.2055056507
Short name T379
Test name
Test status
Simulation time 37392106 ps
CPU time 1.07 seconds
Started Aug 02 07:24:47 PM PDT 24
Finished Aug 02 07:24:48 PM PDT 24
Peak memory 201116 kb
Host smart-7bf782d2-c7c7-4af0-9a8e-1e656ae33585
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055056507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.2055056507
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.2851404566
Short name T473
Test name
Test status
Simulation time 27736305 ps
CPU time 0.8 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201184 kb
Host smart-4ab7b52a-160e-4edc-9a69-0a12be44b1fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851404566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.2851404566
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.2237748056
Short name T769
Test name
Test status
Simulation time 26796737 ps
CPU time 0.81 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:54 PM PDT 24
Peak memory 201132 kb
Host smart-d7068d18-17e7-4b00-ba85-f590633c9ed4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237748056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.2237748056
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.1119387624
Short name T491
Test name
Test status
Simulation time 16969853 ps
CPU time 0.76 seconds
Started Aug 02 07:24:43 PM PDT 24
Finished Aug 02 07:24:44 PM PDT 24
Peak memory 200992 kb
Host smart-aad0bada-00d9-478b-a9d6-85c71056865d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119387624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1119387624
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.1817319996
Short name T575
Test name
Test status
Simulation time 660167617 ps
CPU time 2.79 seconds
Started Aug 02 07:24:49 PM PDT 24
Finished Aug 02 07:24:52 PM PDT 24
Peak memory 201324 kb
Host smart-197b9bea-86ff-473a-9b6b-ace81dd9b9f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817319996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.1817319996
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.3678254595
Short name T155
Test name
Test status
Simulation time 87694761 ps
CPU time 1.02 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:39 PM PDT 24
Peak memory 201048 kb
Host smart-5bb4daf3-ba50-431c-8e66-9a6aaaf01ffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678254595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3678254595
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.2454655736
Short name T676
Test name
Test status
Simulation time 7225148533 ps
CPU time 38.07 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:25:31 PM PDT 24
Peak memory 201528 kb
Host smart-f1f0884f-d428-4b61-818d-829938f7bcee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454655736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.2454655736
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.3092699753
Short name T625
Test name
Test status
Simulation time 144906395385 ps
CPU time 868.85 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:39:19 PM PDT 24
Peak memory 217972 kb
Host smart-7c034f89-c04b-45cb-b042-b23d9012edf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3092699753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.3092699753
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.1218714187
Short name T760
Test name
Test status
Simulation time 25619539 ps
CPU time 0.94 seconds
Started Aug 02 07:24:38 PM PDT 24
Finished Aug 02 07:24:39 PM PDT 24
Peak memory 201056 kb
Host smart-12485b2c-af2b-4578-ba7a-705efa86404e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218714187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1218714187
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.1741987692
Short name T728
Test name
Test status
Simulation time 25933104 ps
CPU time 0.79 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201180 kb
Host smart-85759663-fa73-43ba-8791-ee02e58192ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741987692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.1741987692
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.287836004
Short name T123
Test name
Test status
Simulation time 22880749 ps
CPU time 0.89 seconds
Started Aug 02 07:24:47 PM PDT 24
Finished Aug 02 07:24:48 PM PDT 24
Peak memory 201140 kb
Host smart-2bbfd401-34c6-4e5a-b7b3-fa45b0a7c7f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287836004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.287836004
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.585324475
Short name T433
Test name
Test status
Simulation time 66744320 ps
CPU time 0.82 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:24:51 PM PDT 24
Peak memory 201016 kb
Host smart-20e72b92-d1ef-4b76-8ed7-ad6bb7575c48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585324475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.585324475
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.1248257282
Short name T329
Test name
Test status
Simulation time 34376049 ps
CPU time 0.86 seconds
Started Aug 02 07:24:56 PM PDT 24
Finished Aug 02 07:24:57 PM PDT 24
Peak memory 201196 kb
Host smart-09fcd8d7-dca5-4ae7-8cae-92bbabbf77fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248257282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.1248257282
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.3583306410
Short name T445
Test name
Test status
Simulation time 18872229 ps
CPU time 0.81 seconds
Started Aug 02 07:24:54 PM PDT 24
Finished Aug 02 07:24:55 PM PDT 24
Peak memory 201140 kb
Host smart-cf560ab3-559d-4886-a9dc-2cc863733cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583306410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3583306410
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.4208241807
Short name T2
Test name
Test status
Simulation time 1773217398 ps
CPU time 6.61 seconds
Started Aug 02 07:24:45 PM PDT 24
Finished Aug 02 07:24:52 PM PDT 24
Peak memory 201196 kb
Host smart-fe2d9faa-741d-4ec2-9ba0-35c5c29116d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208241807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.4208241807
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.3937995888
Short name T9
Test name
Test status
Simulation time 560105849 ps
CPU time 2.33 seconds
Started Aug 02 07:24:47 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201220 kb
Host smart-e852d366-ba95-4744-8f53-84b2381c9531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937995888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.3937995888
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.3406814315
Short name T271
Test name
Test status
Simulation time 22065734 ps
CPU time 0.8 seconds
Started Aug 02 07:24:46 PM PDT 24
Finished Aug 02 07:24:47 PM PDT 24
Peak memory 201160 kb
Host smart-aaa60199-502b-40ce-8965-98dd98ff1968
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406814315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.3406814315
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1039437711
Short name T817
Test name
Test status
Simulation time 30492253 ps
CPU time 0.8 seconds
Started Aug 02 07:24:55 PM PDT 24
Finished Aug 02 07:24:56 PM PDT 24
Peak memory 201136 kb
Host smart-ee598422-085a-41e1-b721-1c32c3dca792
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039437711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1039437711
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1432198716
Short name T366
Test name
Test status
Simulation time 23663335 ps
CPU time 0.79 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201084 kb
Host smart-ef4284f7-8031-44e1-b620-b3a10d9ee8f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432198716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.1432198716
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.1013444564
Short name T600
Test name
Test status
Simulation time 65993210 ps
CPU time 0.85 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:24:51 PM PDT 24
Peak memory 201052 kb
Host smart-35776589-11d0-421f-9807-3bd3bd0a80f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013444564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.1013444564
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.509368320
Short name T12
Test name
Test status
Simulation time 896660922 ps
CPU time 5.28 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201268 kb
Host smart-0a21c0b1-cec1-409c-a1be-7cde30f7cc88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509368320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.509368320
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.3500933343
Short name T739
Test name
Test status
Simulation time 79107569 ps
CPU time 1 seconds
Started Aug 02 07:24:55 PM PDT 24
Finished Aug 02 07:24:56 PM PDT 24
Peak memory 200976 kb
Host smart-388f0ff2-3ae4-4b89-bed2-807c61b1a02c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500933343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3500933343
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.3069871290
Short name T752
Test name
Test status
Simulation time 13052127630 ps
CPU time 67.36 seconds
Started Aug 02 07:24:51 PM PDT 24
Finished Aug 02 07:25:59 PM PDT 24
Peak memory 201508 kb
Host smart-490eb4f6-9e21-4754-a3b2-5ef4a63ac904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069871290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.3069871290
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.697684992
Short name T443
Test name
Test status
Simulation time 40210094 ps
CPU time 0.77 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201220 kb
Host smart-7824dae0-7be2-46e5-bcbd-9863c592410d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697684992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.697684992
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.3993015407
Short name T553
Test name
Test status
Simulation time 17787543 ps
CPU time 0.73 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:24:50 PM PDT 24
Peak memory 201048 kb
Host smart-7fb03df0-bbdf-445b-a298-b9eb0ce3fe78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993015407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.3993015407
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3817186156
Short name T785
Test name
Test status
Simulation time 22534698 ps
CPU time 0.92 seconds
Started Aug 02 07:24:51 PM PDT 24
Finished Aug 02 07:24:52 PM PDT 24
Peak memory 201176 kb
Host smart-9d0599f9-1a91-4dce-9bdd-eeb1e4acc0ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817186156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.3817186156
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.399126750
Short name T404
Test name
Test status
Simulation time 12322974 ps
CPU time 0.7 seconds
Started Aug 02 07:24:55 PM PDT 24
Finished Aug 02 07:24:56 PM PDT 24
Peak memory 201040 kb
Host smart-47872521-4b07-4427-bda5-0da5727d047a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399126750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.399126750
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.3182922590
Short name T346
Test name
Test status
Simulation time 202025531 ps
CPU time 1.31 seconds
Started Aug 02 07:24:52 PM PDT 24
Finished Aug 02 07:24:54 PM PDT 24
Peak memory 201156 kb
Host smart-aa88cf45-0e35-4b62-89bf-a4aee2af7d34
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182922590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.3182922590
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.2812833348
Short name T632
Test name
Test status
Simulation time 78805400 ps
CPU time 1.02 seconds
Started Aug 02 07:24:51 PM PDT 24
Finished Aug 02 07:24:52 PM PDT 24
Peak memory 201156 kb
Host smart-de22279b-3cfe-44b0-a44f-573c2a9a254f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812833348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2812833348
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.2900997590
Short name T213
Test name
Test status
Simulation time 441024707 ps
CPU time 2.94 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201208 kb
Host smart-955c1c27-8694-491b-81f8-fecd0b22e47c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900997590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.2900997590
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.162721409
Short name T388
Test name
Test status
Simulation time 2054343328 ps
CPU time 14.72 seconds
Started Aug 02 07:24:51 PM PDT 24
Finished Aug 02 07:25:06 PM PDT 24
Peak memory 201436 kb
Host smart-57318425-e22f-4df2-8321-13bc06d2de4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162721409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_ti
meout.162721409
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1237368539
Short name T203
Test name
Test status
Simulation time 76898819 ps
CPU time 0.97 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201084 kb
Host smart-3ca39060-17d8-4a7d-9d1f-ff86fde4aea3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237368539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.1237368539
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1737719197
Short name T160
Test name
Test status
Simulation time 24149955 ps
CPU time 0.86 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201236 kb
Host smart-9271c849-70d2-4f06-bba5-d83f1c0c52f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737719197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.1737719197
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3661702584
Short name T655
Test name
Test status
Simulation time 33863587 ps
CPU time 0.8 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:54 PM PDT 24
Peak memory 201108 kb
Host smart-2f987005-3c0c-467a-aa26-83a6483ffd31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661702584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.3661702584
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.629959340
Short name T459
Test name
Test status
Simulation time 47339168 ps
CPU time 0.84 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:24:51 PM PDT 24
Peak memory 201036 kb
Host smart-9bc065fc-9899-4550-a1cf-f2c4f4251968
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629959340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.629959340
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.3351803460
Short name T393
Test name
Test status
Simulation time 1336191656 ps
CPU time 5.88 seconds
Started Aug 02 07:24:55 PM PDT 24
Finished Aug 02 07:25:01 PM PDT 24
Peak memory 201228 kb
Host smart-65d54771-0f63-4b58-aa9c-97678995d01e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351803460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.3351803460
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.1736475621
Short name T506
Test name
Test status
Simulation time 53309774 ps
CPU time 0.96 seconds
Started Aug 02 07:24:52 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201184 kb
Host smart-733a1569-9016-418e-82a7-e98e9e86cec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736475621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.1736475621
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_trans.1328782543
Short name T766
Test name
Test status
Simulation time 15605771 ps
CPU time 0.78 seconds
Started Aug 02 07:24:52 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201096 kb
Host smart-c663dc11-91dc-4eea-a4a9-fdd6a05edfb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328782543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.1328782543
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.1068430311
Short name T206
Test name
Test status
Simulation time 28971788 ps
CPU time 0.86 seconds
Started Aug 02 07:24:52 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201156 kb
Host smart-3accb2e5-1dbe-44d5-9132-163719d58934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068430311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.1068430311
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.2192464993
Short name T414
Test name
Test status
Simulation time 15837458 ps
CPU time 0.76 seconds
Started Aug 02 07:24:49 PM PDT 24
Finished Aug 02 07:24:50 PM PDT 24
Peak memory 201168 kb
Host smart-5a286c9e-8ff0-43b6-9d3b-575d58fcf1e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192464993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.2192464993
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.3115162627
Short name T69
Test name
Test status
Simulation time 46063368 ps
CPU time 0.79 seconds
Started Aug 02 07:24:54 PM PDT 24
Finished Aug 02 07:24:55 PM PDT 24
Peak memory 201068 kb
Host smart-e1a8f82e-dc53-4229-a726-8a8a80b43004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115162627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.3115162627
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.658981305
Short name T179
Test name
Test status
Simulation time 31897545 ps
CPU time 1.01 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:54 PM PDT 24
Peak memory 201132 kb
Host smart-a0434e0e-3481-42f1-9cf0-c867540f8c08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658981305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.clkmgr_div_intersig_mubi.658981305
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.2958613637
Short name T685
Test name
Test status
Simulation time 16587929 ps
CPU time 0.77 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201180 kb
Host smart-796c1ebe-febf-4fe1-9960-1f07725f8fa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958613637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2958613637
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.2007474894
Short name T380
Test name
Test status
Simulation time 956454587 ps
CPU time 4.8 seconds
Started Aug 02 07:24:55 PM PDT 24
Finished Aug 02 07:25:00 PM PDT 24
Peak memory 201188 kb
Host smart-0d0cde1b-436d-4f37-b1fa-185f26fca660
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007474894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2007474894
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.3920207159
Short name T815
Test name
Test status
Simulation time 741649675 ps
CPU time 5.39 seconds
Started Aug 02 07:24:52 PM PDT 24
Finished Aug 02 07:24:58 PM PDT 24
Peak memory 201196 kb
Host smart-296f89bc-efcb-4085-8f7f-cf56fd4ad203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920207159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.3920207159
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.3481270367
Short name T648
Test name
Test status
Simulation time 13439806 ps
CPU time 0.72 seconds
Started Aug 02 07:24:47 PM PDT 24
Finished Aug 02 07:24:48 PM PDT 24
Peak memory 201164 kb
Host smart-abc2e509-4544-4f21-adb2-899eebfa165c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481270367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.3481270367
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.296713074
Short name T633
Test name
Test status
Simulation time 22563993 ps
CPU time 0.85 seconds
Started Aug 02 07:24:52 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201144 kb
Host smart-fdecff20-d9dd-42df-8fcc-c6548495cc2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296713074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.clkmgr_lc_clk_byp_req_intersig_mubi.296713074
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1217178914
Short name T643
Test name
Test status
Simulation time 21462636 ps
CPU time 0.83 seconds
Started Aug 02 07:24:51 PM PDT 24
Finished Aug 02 07:24:52 PM PDT 24
Peak memory 201096 kb
Host smart-c3b18adb-c657-4a8e-a770-d05cd4b3eaed
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217178914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.1217178914
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.317712638
Short name T814
Test name
Test status
Simulation time 17164032 ps
CPU time 0.79 seconds
Started Aug 02 07:24:49 PM PDT 24
Finished Aug 02 07:24:50 PM PDT 24
Peak memory 201096 kb
Host smart-46ec93f0-e425-4a85-b790-591a7fedaf82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317712638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.317712638
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.3642082536
Short name T211
Test name
Test status
Simulation time 334708963 ps
CPU time 1.72 seconds
Started Aug 02 07:24:47 PM PDT 24
Finished Aug 02 07:24:49 PM PDT 24
Peak memory 201040 kb
Host smart-1101d230-6787-4416-ae33-94292140846f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642082536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.3642082536
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.1153418281
Short name T156
Test name
Test status
Simulation time 74918344 ps
CPU time 1.01 seconds
Started Aug 02 07:24:47 PM PDT 24
Finished Aug 02 07:24:48 PM PDT 24
Peak memory 201004 kb
Host smart-424acc44-f5bd-4d6d-9f3b-6ff377e9dfcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153418281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1153418281
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.3069060076
Short name T624
Test name
Test status
Simulation time 1537328676 ps
CPU time 6.79 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:59 PM PDT 24
Peak memory 201484 kb
Host smart-0f80cecd-ca52-4ab6-a88a-777e12c84ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069060076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.3069060076
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.554486220
Short name T181
Test name
Test status
Simulation time 86266061180 ps
CPU time 859.5 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:39:10 PM PDT 24
Peak memory 215920 kb
Host smart-09511e28-0ad3-4774-9a9d-cb18233cfb5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=554486220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.554486220
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.2452498299
Short name T286
Test name
Test status
Simulation time 19464409 ps
CPU time 0.79 seconds
Started Aug 02 07:24:50 PM PDT 24
Finished Aug 02 07:24:51 PM PDT 24
Peak memory 201168 kb
Host smart-a36e032a-81ea-469c-9237-47cb4434cbc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452498299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2452498299
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.1479030075
Short name T24
Test name
Test status
Simulation time 52316774 ps
CPU time 0.84 seconds
Started Aug 02 07:22:31 PM PDT 24
Finished Aug 02 07:22:32 PM PDT 24
Peak memory 201140 kb
Host smart-64b446d3-e1c4-4f39-b0ff-485acdca1ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479030075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.1479030075
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1232398394
Short name T194
Test name
Test status
Simulation time 19788872 ps
CPU time 0.84 seconds
Started Aug 02 07:22:19 PM PDT 24
Finished Aug 02 07:22:20 PM PDT 24
Peak memory 201068 kb
Host smart-177e4b0b-b6ee-41cb-bd3e-ddf767e95529
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232398394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.1232398394
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.3938086054
Short name T174
Test name
Test status
Simulation time 17865727 ps
CPU time 0.73 seconds
Started Aug 02 07:22:18 PM PDT 24
Finished Aug 02 07:22:19 PM PDT 24
Peak memory 200296 kb
Host smart-63891b1a-d1ef-4b10-8d88-07b75df911a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938086054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3938086054
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.128032521
Short name T681
Test name
Test status
Simulation time 61566007 ps
CPU time 0.95 seconds
Started Aug 02 07:22:16 PM PDT 24
Finished Aug 02 07:22:17 PM PDT 24
Peak memory 201096 kb
Host smart-041f9e98-b6e6-416b-912e-8fd63dcbabc3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128032521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_div_intersig_mubi.128032521
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.4055949493
Short name T708
Test name
Test status
Simulation time 93445407 ps
CPU time 1.08 seconds
Started Aug 02 07:22:19 PM PDT 24
Finished Aug 02 07:22:20 PM PDT 24
Peak memory 201164 kb
Host smart-ebb13240-074b-497a-ac9b-1225ab1b9da3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055949493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.4055949493
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.4086041861
Short name T748
Test name
Test status
Simulation time 1912933623 ps
CPU time 7.09 seconds
Started Aug 02 07:22:21 PM PDT 24
Finished Aug 02 07:22:28 PM PDT 24
Peak memory 201368 kb
Host smart-bb2d2e7d-d356-4476-ba06-0797d8fc0224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086041861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.4086041861
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.2104327194
Short name T58
Test name
Test status
Simulation time 1467339134 ps
CPU time 6.19 seconds
Started Aug 02 07:22:17 PM PDT 24
Finished Aug 02 07:22:24 PM PDT 24
Peak memory 201228 kb
Host smart-0e13ca1b-fac1-4031-bef8-fdd8b3117ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104327194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.2104327194
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.2808042841
Short name T310
Test name
Test status
Simulation time 76868141 ps
CPU time 1.04 seconds
Started Aug 02 07:22:18 PM PDT 24
Finished Aug 02 07:22:19 PM PDT 24
Peak memory 201108 kb
Host smart-5b7e3549-f1f8-4f67-a871-d94c64f608b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808042841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.2808042841
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.950647289
Short name T195
Test name
Test status
Simulation time 52215809 ps
CPU time 0.89 seconds
Started Aug 02 07:22:18 PM PDT 24
Finished Aug 02 07:22:19 PM PDT 24
Peak memory 201060 kb
Host smart-d4933985-6ea7-4f1d-98e5-8ad69f6dc9cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950647289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_lc_clk_byp_req_intersig_mubi.950647289
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.655178092
Short name T654
Test name
Test status
Simulation time 86362068 ps
CPU time 1.07 seconds
Started Aug 02 07:22:18 PM PDT 24
Finished Aug 02 07:22:19 PM PDT 24
Peak memory 201108 kb
Host smart-c79bff61-56b3-4b51-9305-ea1e96f4f3ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655178092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_lc_ctrl_intersig_mubi.655178092
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.2677362131
Short name T454
Test name
Test status
Simulation time 18240720 ps
CPU time 0.78 seconds
Started Aug 02 07:22:17 PM PDT 24
Finished Aug 02 07:22:17 PM PDT 24
Peak memory 201060 kb
Host smart-f1eeb2eb-d5d9-49aa-9938-2a9faf8dece8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677362131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.2677362131
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.755702467
Short name T694
Test name
Test status
Simulation time 969371864 ps
CPU time 4.03 seconds
Started Aug 02 07:22:33 PM PDT 24
Finished Aug 02 07:22:37 PM PDT 24
Peak memory 201232 kb
Host smart-7e368941-0f85-45fa-bbc5-3aaba43ee474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755702467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.755702467
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.632839941
Short name T53
Test name
Test status
Simulation time 380425695 ps
CPU time 3.06 seconds
Started Aug 02 07:22:31 PM PDT 24
Finished Aug 02 07:22:34 PM PDT 24
Peak memory 217964 kb
Host smart-a488df74-6b2f-4fc4-b7de-cc3dd8e15d9d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632839941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr
_sec_cm.632839941
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.2158812993
Short name T32
Test name
Test status
Simulation time 68750064 ps
CPU time 0.96 seconds
Started Aug 02 07:22:11 PM PDT 24
Finished Aug 02 07:22:13 PM PDT 24
Peak memory 201056 kb
Host smart-a5c39eaa-a0d5-461a-b8cd-3f054d30397f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158812993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.2158812993
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.3135948371
Short name T528
Test name
Test status
Simulation time 7663012191 ps
CPU time 54.37 seconds
Started Aug 02 07:22:30 PM PDT 24
Finished Aug 02 07:23:25 PM PDT 24
Peak memory 201456 kb
Host smart-43c4a5d5-8eea-468a-aade-9f9b1fe01537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135948371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.3135948371
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.4149998557
Short name T517
Test name
Test status
Simulation time 142321471 ps
CPU time 1.09 seconds
Started Aug 02 07:22:21 PM PDT 24
Finished Aug 02 07:22:23 PM PDT 24
Peak memory 201116 kb
Host smart-70239ef5-6af2-41b3-9ffc-8459808644c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149998557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.4149998557
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1707073100
Short name T606
Test name
Test status
Simulation time 15030823 ps
CPU time 0.79 seconds
Started Aug 02 07:24:52 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201156 kb
Host smart-5938538e-cd9a-4595-ac1e-eab308b3f839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707073100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1707073100
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.3394273221
Short name T670
Test name
Test status
Simulation time 87355215 ps
CPU time 1.15 seconds
Started Aug 02 07:24:54 PM PDT 24
Finished Aug 02 07:24:56 PM PDT 24
Peak memory 201140 kb
Host smart-a2d452e9-7cc8-4f42-9d17-c6cd65e81051
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394273221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.3394273221
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.3924309360
Short name T721
Test name
Test status
Simulation time 17342563 ps
CPU time 0.7 seconds
Started Aug 02 07:24:46 PM PDT 24
Finished Aug 02 07:24:47 PM PDT 24
Peak memory 200292 kb
Host smart-3f43c57b-10a5-4049-8106-7977666b4e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924309360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.3924309360
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.1586116579
Short name T653
Test name
Test status
Simulation time 56272883 ps
CPU time 0.87 seconds
Started Aug 02 07:24:51 PM PDT 24
Finished Aug 02 07:24:52 PM PDT 24
Peak memory 201108 kb
Host smart-d8122a98-0877-4b87-9bf8-ff71b85963a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586116579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.1586116579
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.3463325344
Short name T56
Test name
Test status
Simulation time 70049191 ps
CPU time 1.14 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:54 PM PDT 24
Peak memory 201128 kb
Host smart-bcf23196-21bc-43cc-a2e8-44dcd1cd7a8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463325344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.3463325344
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.86162355
Short name T269
Test name
Test status
Simulation time 1878117032 ps
CPU time 13.67 seconds
Started Aug 02 07:24:56 PM PDT 24
Finished Aug 02 07:25:10 PM PDT 24
Peak memory 201428 kb
Host smart-321da7a4-e6b8-428e-91af-466c8fd20fe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86162355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.86162355
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.1572901252
Short name T361
Test name
Test status
Simulation time 2422751585 ps
CPU time 9.87 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:25:03 PM PDT 24
Peak memory 201516 kb
Host smart-250904b4-242b-41bd-a9a3-7f6c8681e17c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572901252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.1572901252
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.3196160514
Short name T714
Test name
Test status
Simulation time 35540834 ps
CPU time 0.76 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:53 PM PDT 24
Peak memory 201152 kb
Host smart-c335f936-20c1-4cdf-8cfd-ddf1d89ed43f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196160514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.3196160514
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.974382200
Short name T208
Test name
Test status
Simulation time 16040628 ps
CPU time 0.78 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:54 PM PDT 24
Peak memory 201128 kb
Host smart-6d44e118-4aa0-4664-9919-8001791f6aea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974382200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.clkmgr_lc_ctrl_intersig_mubi.974382200
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.1258131034
Short name T266
Test name
Test status
Simulation time 38076407 ps
CPU time 0.84 seconds
Started Aug 02 07:24:53 PM PDT 24
Finished Aug 02 07:24:54 PM PDT 24
Peak memory 201124 kb
Host smart-71fb05a7-2946-4546-be55-68a07eea404c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258131034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.1258131034
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.414844417
Short name T403
Test name
Test status
Simulation time 137235582 ps
CPU time 1.4 seconds
Started Aug 02 07:24:56 PM PDT 24
Finished Aug 02 07:24:58 PM PDT 24
Peak memory 201208 kb
Host smart-79309aa3-0454-4347-ad4b-3bdba8909fca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414844417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.414844417
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.2776869877
Short name T258
Test name
Test status
Simulation time 4076843235 ps
CPU time 30.28 seconds
Started Aug 02 07:24:48 PM PDT 24
Finished Aug 02 07:25:18 PM PDT 24
Peak memory 201472 kb
Host smart-793f0a2c-b43d-4c59-a2e4-5c7feaffc3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776869877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.2776869877
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.2067726978
Short name T60
Test name
Test status
Simulation time 48125217 ps
CPU time 0.9 seconds
Started Aug 02 07:24:55 PM PDT 24
Finished Aug 02 07:24:56 PM PDT 24
Peak memory 201188 kb
Host smart-a0b61a84-0d53-4a27-8daf-6e806c16bc33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067726978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2067726978
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.635476967
Short name T229
Test name
Test status
Simulation time 17554072 ps
CPU time 0.76 seconds
Started Aug 02 07:25:00 PM PDT 24
Finished Aug 02 07:25:01 PM PDT 24
Peak memory 201108 kb
Host smart-c1249cf9-2a19-405f-a562-e6547e326445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635476967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkm
gr_alert_test.635476967
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1220766056
Short name T120
Test name
Test status
Simulation time 21342409 ps
CPU time 0.93 seconds
Started Aug 02 07:25:03 PM PDT 24
Finished Aug 02 07:25:04 PM PDT 24
Peak memory 201180 kb
Host smart-33f9b99c-aec3-437c-9a44-e630f13dc5bf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220766056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.1220766056
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.3932280564
Short name T308
Test name
Test status
Simulation time 56767284 ps
CPU time 0.82 seconds
Started Aug 02 07:25:00 PM PDT 24
Finished Aug 02 07:25:01 PM PDT 24
Peak memory 201100 kb
Host smart-199f3c37-213d-4dad-b98b-26611d1c6f83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932280564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3932280564
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.1569194717
Short name T544
Test name
Test status
Simulation time 41651100 ps
CPU time 1.07 seconds
Started Aug 02 07:24:59 PM PDT 24
Finished Aug 02 07:25:00 PM PDT 24
Peak memory 201096 kb
Host smart-268a8048-e640-4370-9053-9ec4f16ebfc2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569194717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.1569194717
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.3096008227
Short name T501
Test name
Test status
Simulation time 42860603 ps
CPU time 0.79 seconds
Started Aug 02 07:24:59 PM PDT 24
Finished Aug 02 07:25:00 PM PDT 24
Peak memory 201108 kb
Host smart-263a19f8-4ffa-4deb-85ab-f3ea1a06c8e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096008227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.3096008227
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.1715514323
Short name T700
Test name
Test status
Simulation time 2480855162 ps
CPU time 18.56 seconds
Started Aug 02 07:25:01 PM PDT 24
Finished Aug 02 07:25:20 PM PDT 24
Peak memory 201384 kb
Host smart-aec1fd24-4ddf-4ba4-969b-a3f3298832c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715514323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1715514323
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.864656865
Short name T402
Test name
Test status
Simulation time 60324236 ps
CPU time 0.92 seconds
Started Aug 02 07:24:58 PM PDT 24
Finished Aug 02 07:24:59 PM PDT 24
Peak memory 201132 kb
Host smart-3d7aa20f-05e6-4da4-9914-7fe63d9eef52
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864656865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.clkmgr_idle_intersig_mubi.864656865
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2892124439
Short name T397
Test name
Test status
Simulation time 139707836 ps
CPU time 1.13 seconds
Started Aug 02 07:24:58 PM PDT 24
Finished Aug 02 07:25:00 PM PDT 24
Peak memory 201136 kb
Host smart-d75df4a7-c2a9-4f30-9ce7-2210d4ddd8d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892124439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.2892124439
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2275710714
Short name T210
Test name
Test status
Simulation time 15928867 ps
CPU time 0.77 seconds
Started Aug 02 07:25:00 PM PDT 24
Finished Aug 02 07:25:01 PM PDT 24
Peak memory 201052 kb
Host smart-bf5f04bf-54c7-4ad5-ba84-6002ed1c291c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275710714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.2275710714
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.2725375653
Short name T563
Test name
Test status
Simulation time 56664960 ps
CPU time 0.84 seconds
Started Aug 02 07:24:59 PM PDT 24
Finished Aug 02 07:25:00 PM PDT 24
Peak memory 200992 kb
Host smart-e5b13220-7e2b-4d11-8f89-4cae2c03d4cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725375653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2725375653
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.1605446286
Short name T556
Test name
Test status
Simulation time 266872125 ps
CPU time 1.97 seconds
Started Aug 02 07:24:58 PM PDT 24
Finished Aug 02 07:25:00 PM PDT 24
Peak memory 201072 kb
Host smart-5214e6da-9a4d-4b95-81f7-85f847ec354a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605446286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1605446286
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.2773884985
Short name T734
Test name
Test status
Simulation time 23769009 ps
CPU time 0.89 seconds
Started Aug 02 07:25:00 PM PDT 24
Finished Aug 02 07:25:01 PM PDT 24
Peak memory 201180 kb
Host smart-5d33938e-4274-49ec-a7bd-e160104a0ab0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773884985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2773884985
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.4292341697
Short name T629
Test name
Test status
Simulation time 55169240 ps
CPU time 1.19 seconds
Started Aug 02 07:24:58 PM PDT 24
Finished Aug 02 07:25:00 PM PDT 24
Peak memory 201092 kb
Host smart-a5470368-f709-4f65-8509-ce3e8c0c83c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292341697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.4292341697
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.2784610325
Short name T190
Test name
Test status
Simulation time 34380596 ps
CPU time 0.99 seconds
Started Aug 02 07:24:57 PM PDT 24
Finished Aug 02 07:24:58 PM PDT 24
Peak memory 201084 kb
Host smart-87d1524e-8592-4182-892b-7900c1afdec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784610325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2784610325
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.335970683
Short name T279
Test name
Test status
Simulation time 15425997 ps
CPU time 0.75 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:11 PM PDT 24
Peak memory 201132 kb
Host smart-7b399320-b2eb-43d3-963d-2cd0422484ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335970683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkm
gr_alert_test.335970683
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.4073272243
Short name T115
Test name
Test status
Simulation time 65157035 ps
CPU time 0.99 seconds
Started Aug 02 07:25:01 PM PDT 24
Finished Aug 02 07:25:02 PM PDT 24
Peak memory 201112 kb
Host smart-dec855e2-c8b7-4045-b147-676ff25f7cb5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073272243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.4073272243
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.3452043504
Short name T503
Test name
Test status
Simulation time 22809865 ps
CPU time 0.76 seconds
Started Aug 02 07:25:01 PM PDT 24
Finished Aug 02 07:25:02 PM PDT 24
Peak memory 200264 kb
Host smart-148c49ee-740a-440e-a457-89cfa001907d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452043504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.3452043504
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.1495112909
Short name T270
Test name
Test status
Simulation time 133335846 ps
CPU time 1.19 seconds
Started Aug 02 07:25:00 PM PDT 24
Finished Aug 02 07:25:02 PM PDT 24
Peak memory 201064 kb
Host smart-0a764a46-d5bc-4973-8c60-f620ba7be8ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495112909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.1495112909
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.3003248957
Short name T599
Test name
Test status
Simulation time 37397988 ps
CPU time 0.97 seconds
Started Aug 02 07:25:03 PM PDT 24
Finished Aug 02 07:25:04 PM PDT 24
Peak memory 201176 kb
Host smart-15de6087-3c53-4cfd-9fe3-377364f4c778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003248957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.3003248957
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3794535139
Short name T819
Test name
Test status
Simulation time 202067058 ps
CPU time 2.27 seconds
Started Aug 02 07:24:59 PM PDT 24
Finished Aug 02 07:25:01 PM PDT 24
Peak memory 201116 kb
Host smart-7e1a537d-4533-44d9-9159-83be5a38dc48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794535139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3794535139
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.3048937780
Short name T192
Test name
Test status
Simulation time 859903524 ps
CPU time 6.46 seconds
Started Aug 02 07:25:02 PM PDT 24
Finished Aug 02 07:25:09 PM PDT 24
Peak memory 201204 kb
Host smart-06a968e5-1031-4b94-8f8b-5145ac8649c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048937780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.3048937780
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.2483223790
Short name T246
Test name
Test status
Simulation time 33096120 ps
CPU time 1.01 seconds
Started Aug 02 07:25:00 PM PDT 24
Finished Aug 02 07:25:02 PM PDT 24
Peak memory 201116 kb
Host smart-c7896791-56f3-43bf-8eec-1434064e6c66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483223790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.2483223790
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.1953741049
Short name T586
Test name
Test status
Simulation time 45812657 ps
CPU time 0.81 seconds
Started Aug 02 07:24:59 PM PDT 24
Finished Aug 02 07:25:00 PM PDT 24
Peak memory 201128 kb
Host smart-d939b340-e71b-457c-926f-c27e433717a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953741049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.1953741049
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.4109733846
Short name T770
Test name
Test status
Simulation time 54072002 ps
CPU time 0.85 seconds
Started Aug 02 07:25:02 PM PDT 24
Finished Aug 02 07:25:03 PM PDT 24
Peak memory 201084 kb
Host smart-aa17c17a-b0f7-4b25-b176-35ea6abaa6e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109733846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.4109733846
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.38576661
Short name T368
Test name
Test status
Simulation time 18703812 ps
CPU time 0.76 seconds
Started Aug 02 07:25:00 PM PDT 24
Finished Aug 02 07:25:01 PM PDT 24
Peak memory 201064 kb
Host smart-8ef66310-9bd1-4f6c-b233-e57b48c2e9b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.38576661
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.2597161154
Short name T510
Test name
Test status
Simulation time 1260597994 ps
CPU time 5.66 seconds
Started Aug 02 07:25:09 PM PDT 24
Finished Aug 02 07:25:15 PM PDT 24
Peak memory 201376 kb
Host smart-354ec53e-ab47-459b-baaf-5139d1459aba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597161154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2597161154
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.1348315089
Short name T316
Test name
Test status
Simulation time 68598166 ps
CPU time 1.02 seconds
Started Aug 02 07:25:02 PM PDT 24
Finished Aug 02 07:25:03 PM PDT 24
Peak memory 201180 kb
Host smart-54e8b1e4-75d0-4a11-8b57-4410b96311a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348315089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1348315089
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.4115379980
Short name T674
Test name
Test status
Simulation time 7776538846 ps
CPU time 34.17 seconds
Started Aug 02 07:25:14 PM PDT 24
Finished Aug 02 07:25:48 PM PDT 24
Peak memory 201504 kb
Host smart-147d9233-8951-4916-9b40-84271f65be95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115379980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.4115379980
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.4135746512
Short name T90
Test name
Test status
Simulation time 84456994769 ps
CPU time 547.73 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:34:20 PM PDT 24
Peak memory 217944 kb
Host smart-edc63224-7695-4303-9a3d-d8e1b16917be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4135746512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.4135746512
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.2586122442
Short name T223
Test name
Test status
Simulation time 53837585 ps
CPU time 0.88 seconds
Started Aug 02 07:25:02 PM PDT 24
Finished Aug 02 07:25:03 PM PDT 24
Peak memory 201084 kb
Host smart-2597206f-3291-44e0-aa98-7947f7a11a5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586122442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2586122442
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.1249811293
Short name T381
Test name
Test status
Simulation time 16511475 ps
CPU time 0.78 seconds
Started Aug 02 07:25:16 PM PDT 24
Finished Aug 02 07:25:17 PM PDT 24
Peak memory 201136 kb
Host smart-2e02e6db-43d7-419b-8a47-e5000a9464b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249811293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.1249811293
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.1009543353
Short name T756
Test name
Test status
Simulation time 42464388 ps
CPU time 0.81 seconds
Started Aug 02 07:25:15 PM PDT 24
Finished Aug 02 07:25:16 PM PDT 24
Peak memory 201112 kb
Host smart-57fd5000-05c8-4b0c-85fa-281da998de5c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009543353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.1009543353
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.296025190
Short name T169
Test name
Test status
Simulation time 16012096 ps
CPU time 0.7 seconds
Started Aug 02 07:25:13 PM PDT 24
Finished Aug 02 07:25:14 PM PDT 24
Peak memory 200312 kb
Host smart-c006c9b8-8fb8-4dd0-a966-079540232c45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296025190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.296025190
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.3642028433
Short name T239
Test name
Test status
Simulation time 62163108 ps
CPU time 0.92 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201084 kb
Host smart-a733c13f-92e8-4b9c-a109-7f350aa7182f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642028433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.3642028433
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.2795377166
Short name T204
Test name
Test status
Simulation time 18161957 ps
CPU time 0.76 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201148 kb
Host smart-7805a072-19b9-4833-b504-64566a542f8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795377166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.2795377166
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.748226762
Short name T344
Test name
Test status
Simulation time 815431074 ps
CPU time 4.27 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:14 PM PDT 24
Peak memory 201188 kb
Host smart-64fa5ee7-2ab9-4b73-8f88-3e0afd37b2b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748226762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.748226762
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.3905358964
Short name T296
Test name
Test status
Simulation time 1256287237 ps
CPU time 4.86 seconds
Started Aug 02 07:25:14 PM PDT 24
Finished Aug 02 07:25:19 PM PDT 24
Peak memory 201280 kb
Host smart-7c358865-4c2a-495d-9c3a-8c59b269b776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905358964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.3905358964
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.233204167
Short name T540
Test name
Test status
Simulation time 49672812 ps
CPU time 0.89 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201176 kb
Host smart-571e7e05-bb60-42ae-a99b-d11427424eab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233204167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.clkmgr_idle_intersig_mubi.233204167
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.4237259476
Short name T781
Test name
Test status
Simulation time 20252683 ps
CPU time 0.8 seconds
Started Aug 02 07:25:11 PM PDT 24
Finished Aug 02 07:25:11 PM PDT 24
Peak memory 201056 kb
Host smart-d8a6b3f0-9b52-4865-b303-5219bbf8f5a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237259476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.4237259476
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.100459689
Short name T559
Test name
Test status
Simulation time 29565310 ps
CPU time 0.73 seconds
Started Aug 02 07:25:09 PM PDT 24
Finished Aug 02 07:25:10 PM PDT 24
Peak memory 201180 kb
Host smart-8351373d-db90-4174-8cdb-363860a2f345
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100459689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_ctrl_intersig_mubi.100459689
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.2121221932
Short name T66
Test name
Test status
Simulation time 22256375 ps
CPU time 0.76 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201068 kb
Host smart-bdc19d98-5beb-4d53-90a9-2d2c86b60d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121221932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2121221932
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.3565061505
Short name T4
Test name
Test status
Simulation time 267484292 ps
CPU time 2.16 seconds
Started Aug 02 07:25:14 PM PDT 24
Finished Aug 02 07:25:17 PM PDT 24
Peak memory 201124 kb
Host smart-d1ed6032-4d0b-4dc9-99f3-400af3e94456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565061505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3565061505
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.4033717812
Short name T608
Test name
Test status
Simulation time 29682101 ps
CPU time 0.86 seconds
Started Aug 02 07:25:15 PM PDT 24
Finished Aug 02 07:25:17 PM PDT 24
Peak memory 201120 kb
Host smart-54c8ea4c-c7f3-44a1-9d04-41c945f3c7dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033717812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.4033717812
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.1828526442
Short name T677
Test name
Test status
Simulation time 5580697546 ps
CPU time 20.97 seconds
Started Aug 02 07:25:15 PM PDT 24
Finished Aug 02 07:25:36 PM PDT 24
Peak memory 201468 kb
Host smart-9f028af2-c333-49fc-88dc-7dd11e6e50ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828526442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.1828526442
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.2235693755
Short name T516
Test name
Test status
Simulation time 54594551 ps
CPU time 0.9 seconds
Started Aug 02 07:25:13 PM PDT 24
Finished Aug 02 07:25:14 PM PDT 24
Peak memory 200980 kb
Host smart-131d47a9-9a05-4bf3-919c-aec947e5f283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235693755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2235693755
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.3126031264
Short name T594
Test name
Test status
Simulation time 31991164 ps
CPU time 0.81 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201088 kb
Host smart-3d09bd24-c713-4c7c-a505-a2a8dbf02fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126031264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.3126031264
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.3352731851
Short name T193
Test name
Test status
Simulation time 58012009 ps
CPU time 0.84 seconds
Started Aug 02 07:25:13 PM PDT 24
Finished Aug 02 07:25:14 PM PDT 24
Peak memory 201140 kb
Host smart-10b68097-bcf5-4189-84c9-d7dcaf0153f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352731851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.3352731851
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.2417304642
Short name T48
Test name
Test status
Simulation time 46657093 ps
CPU time 0.8 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:11 PM PDT 24
Peak memory 200272 kb
Host smart-03a19b02-b4f1-4569-bb1b-cda52497fe2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417304642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2417304642
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.1610869667
Short name T726
Test name
Test status
Simulation time 17879716 ps
CPU time 0.76 seconds
Started Aug 02 07:25:08 PM PDT 24
Finished Aug 02 07:25:09 PM PDT 24
Peak memory 201148 kb
Host smart-ef98fdae-af8a-4e34-b516-ea410b832de0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610869667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.1610869667
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.736499962
Short name T383
Test name
Test status
Simulation time 80248471 ps
CPU time 1.01 seconds
Started Aug 02 07:25:15 PM PDT 24
Finished Aug 02 07:25:16 PM PDT 24
Peak memory 201104 kb
Host smart-71206106-aeb6-4be2-a2c0-40644395db9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736499962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.736499962
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.2857553970
Short name T36
Test name
Test status
Simulation time 689336570 ps
CPU time 3.62 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:14 PM PDT 24
Peak memory 201224 kb
Host smart-cab8a982-3876-43fa-b854-a4a66cb60e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857553970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2857553970
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.4012197894
Short name T114
Test name
Test status
Simulation time 1392639920 ps
CPU time 6.31 seconds
Started Aug 02 07:25:11 PM PDT 24
Finished Aug 02 07:25:17 PM PDT 24
Peak memory 201156 kb
Host smart-f9bc4b9c-662e-4483-9284-9fcc8255cf23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012197894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.4012197894
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.835888864
Short name T467
Test name
Test status
Simulation time 57956261 ps
CPU time 0.93 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:11 PM PDT 24
Peak memory 201132 kb
Host smart-d0149f90-7240-4e79-b2b2-015bc6908c95
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835888864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_idle_intersig_mubi.835888864
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1525534488
Short name T376
Test name
Test status
Simulation time 23103710 ps
CPU time 0.92 seconds
Started Aug 02 07:25:09 PM PDT 24
Finished Aug 02 07:25:10 PM PDT 24
Peak memory 201100 kb
Host smart-3bededcd-0348-4492-9c63-bf516378cd08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525534488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1525534488
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.772113125
Short name T275
Test name
Test status
Simulation time 56959780 ps
CPU time 0.91 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201192 kb
Host smart-29f52b8c-c332-412a-8e4c-948cc0fa30d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772113125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_ctrl_intersig_mubi.772113125
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.839335417
Short name T158
Test name
Test status
Simulation time 31784312 ps
CPU time 0.79 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201084 kb
Host smart-b01d381f-1650-4750-901b-7c078e129bdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839335417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.839335417
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.2196996325
Short name T202
Test name
Test status
Simulation time 883474719 ps
CPU time 3.61 seconds
Started Aug 02 07:25:14 PM PDT 24
Finished Aug 02 07:25:18 PM PDT 24
Peak memory 201336 kb
Host smart-d79ec334-334a-4ccd-b05a-3c4f86196fc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196996325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.2196996325
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.4264302120
Short name T22
Test name
Test status
Simulation time 77635559 ps
CPU time 1.07 seconds
Started Aug 02 07:25:11 PM PDT 24
Finished Aug 02 07:25:12 PM PDT 24
Peak memory 201072 kb
Host smart-8943dea4-5046-46dd-a0ba-500fc3b37502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264302120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.4264302120
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3170324914
Short name T37
Test name
Test status
Simulation time 8765391997 ps
CPU time 36.48 seconds
Started Aug 02 07:25:08 PM PDT 24
Finished Aug 02 07:25:45 PM PDT 24
Peak memory 201468 kb
Host smart-555ed7e1-538b-48bc-a71d-04a11b12a6e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170324914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3170324914
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.116220313
Short name T779
Test name
Test status
Simulation time 58053731 ps
CPU time 0.97 seconds
Started Aug 02 07:25:13 PM PDT 24
Finished Aug 02 07:25:14 PM PDT 24
Peak memory 201056 kb
Host smart-7fb028ad-09c7-42a4-8706-55de14db3911
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116220313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.116220313
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.1674130781
Short name T529
Test name
Test status
Simulation time 38311045 ps
CPU time 0.81 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:25 PM PDT 24
Peak memory 201112 kb
Host smart-af527272-b79d-460c-acba-81290cb48fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674130781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.1674130781
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.1909413320
Short name T765
Test name
Test status
Simulation time 28023554 ps
CPU time 0.83 seconds
Started Aug 02 07:25:11 PM PDT 24
Finished Aug 02 07:25:12 PM PDT 24
Peak memory 201088 kb
Host smart-0a48913d-d870-4ec2-8f93-6c7bece00344
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909413320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.1909413320
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.2069703138
Short name T680
Test name
Test status
Simulation time 17815202 ps
CPU time 0.7 seconds
Started Aug 02 07:25:11 PM PDT 24
Finished Aug 02 07:25:12 PM PDT 24
Peak memory 200248 kb
Host smart-43422e63-f9ce-48d8-aa53-150e5acbcc4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069703138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.2069703138
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.840662646
Short name T773
Test name
Test status
Simulation time 17228660 ps
CPU time 0.78 seconds
Started Aug 02 07:25:15 PM PDT 24
Finished Aug 02 07:25:16 PM PDT 24
Peak memory 201128 kb
Host smart-dd08f4e3-497f-47fb-8207-eb092078b08a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840662646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_div_intersig_mubi.840662646
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.734195720
Short name T478
Test name
Test status
Simulation time 165681449 ps
CPU time 1.33 seconds
Started Aug 02 07:25:11 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201028 kb
Host smart-4839f460-cc68-4f98-bde6-faa02e016070
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734195720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.734195720
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.3922136585
Short name T582
Test name
Test status
Simulation time 333864165 ps
CPU time 2.49 seconds
Started Aug 02 07:25:13 PM PDT 24
Finished Aug 02 07:25:16 PM PDT 24
Peak memory 201016 kb
Host smart-0ed9305c-c3c2-4e52-af6e-ff74a04331a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922136585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3922136585
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.3080708951
Short name T322
Test name
Test status
Simulation time 620503063 ps
CPU time 4.84 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:15 PM PDT 24
Peak memory 201156 kb
Host smart-9fbda73f-4815-430d-9757-a18f24943980
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080708951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.3080708951
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.1798136553
Short name T98
Test name
Test status
Simulation time 29821134 ps
CPU time 0.93 seconds
Started Aug 02 07:25:11 PM PDT 24
Finished Aug 02 07:25:12 PM PDT 24
Peak memory 201076 kb
Host smart-174e1abc-7b69-4147-aa00-58f57b5456aa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798136553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.1798136553
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.4283517628
Short name T761
Test name
Test status
Simulation time 27856489 ps
CPU time 0.93 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:11 PM PDT 24
Peak memory 201084 kb
Host smart-03da4700-4e07-4b24-b9ab-8cfd84d8829f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283517628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.4283517628
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1886400184
Short name T219
Test name
Test status
Simulation time 25931919 ps
CPU time 0.91 seconds
Started Aug 02 07:25:09 PM PDT 24
Finished Aug 02 07:25:10 PM PDT 24
Peak memory 201112 kb
Host smart-7a541258-9cbe-4355-a03d-95e166197bb9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886400184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.1886400184
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.3047402837
Short name T458
Test name
Test status
Simulation time 24112182 ps
CPU time 0.73 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201128 kb
Host smart-421d0c69-3e21-4365-9667-d40eaf33fe08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047402837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.3047402837
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.3765107726
Short name T325
Test name
Test status
Simulation time 587087154 ps
CPU time 3.73 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:14 PM PDT 24
Peak memory 201208 kb
Host smart-9e857116-1b7e-4abc-b8eb-49c1f14cc6c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765107726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.3765107726
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.633589184
Short name T628
Test name
Test status
Simulation time 54745079 ps
CPU time 0.93 seconds
Started Aug 02 07:25:12 PM PDT 24
Finished Aug 02 07:25:13 PM PDT 24
Peak memory 201096 kb
Host smart-fc33001f-4dd1-4281-8174-51a69cdba79e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633589184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.633589184
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.351741297
Short name T16
Test name
Test status
Simulation time 6260742819 ps
CPU time 46.21 seconds
Started Aug 02 07:25:25 PM PDT 24
Finished Aug 02 07:26:11 PM PDT 24
Peak memory 201464 kb
Host smart-58837e4c-3445-4e7b-9266-b4318fae5a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351741297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.351741297
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.423941398
Short name T751
Test name
Test status
Simulation time 16311027 ps
CPU time 0.78 seconds
Started Aug 02 07:25:10 PM PDT 24
Finished Aug 02 07:25:11 PM PDT 24
Peak memory 201096 kb
Host smart-889112a6-68db-4352-ab97-1597f7062788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423941398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.423941398
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.3374956042
Short name T495
Test name
Test status
Simulation time 117798834 ps
CPU time 1.15 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:26 PM PDT 24
Peak memory 201056 kb
Host smart-b4fd425e-ce70-424e-8cd3-d76074449115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374956042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.3374956042
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1845238329
Short name T261
Test name
Test status
Simulation time 61685563 ps
CPU time 0.96 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201120 kb
Host smart-587a36b4-2d9c-4078-abbc-da3b4020ccc8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845238329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.1845238329
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1978653985
Short name T735
Test name
Test status
Simulation time 14262999 ps
CPU time 0.71 seconds
Started Aug 02 07:25:30 PM PDT 24
Finished Aug 02 07:25:31 PM PDT 24
Peak memory 200324 kb
Host smart-60005055-4bdf-4723-acaf-4e1b310024ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978653985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1978653985
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.3426731015
Short name T233
Test name
Test status
Simulation time 25065081 ps
CPU time 0.88 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:25 PM PDT 24
Peak memory 201100 kb
Host smart-07e30f9e-d406-458f-936e-0f37952b845f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426731015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.3426731015
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.3816680389
Short name T787
Test name
Test status
Simulation time 68411484 ps
CPU time 0.9 seconds
Started Aug 02 07:25:25 PM PDT 24
Finished Aug 02 07:25:26 PM PDT 24
Peak memory 201012 kb
Host smart-6d8ab954-ce2a-466b-94c8-defd8eaf187a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816680389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.3816680389
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.4029585291
Short name T324
Test name
Test status
Simulation time 2770621785 ps
CPU time 11.04 seconds
Started Aug 02 07:25:25 PM PDT 24
Finished Aug 02 07:25:36 PM PDT 24
Peak memory 201328 kb
Host smart-abf4a71b-c561-4c92-aeed-ec448177273e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029585291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.4029585291
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.4165149901
Short name T396
Test name
Test status
Simulation time 1099981723 ps
CPU time 8.63 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:32 PM PDT 24
Peak memory 201240 kb
Host smart-f5b8d3a3-bd0f-48ae-9977-09f2822af439
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165149901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.4165149901
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.2950598052
Short name T408
Test name
Test status
Simulation time 53495918 ps
CPU time 1.02 seconds
Started Aug 02 07:25:22 PM PDT 24
Finished Aug 02 07:25:23 PM PDT 24
Peak memory 201144 kb
Host smart-9fab17d8-1c3f-4db9-a180-237e5147735f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950598052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.2950598052
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1798682564
Short name T565
Test name
Test status
Simulation time 21742228 ps
CPU time 0.78 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201136 kb
Host smart-3fb8a8bb-b4ee-4a06-9aa9-894554d36c45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798682564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1798682564
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.1233837884
Short name T535
Test name
Test status
Simulation time 82722346 ps
CPU time 1.02 seconds
Started Aug 02 07:25:22 PM PDT 24
Finished Aug 02 07:25:23 PM PDT 24
Peak memory 201104 kb
Host smart-452336e5-3e02-4a6e-a461-f3d5246c68f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233837884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.1233837884
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.2669364897
Short name T21
Test name
Test status
Simulation time 15041585 ps
CPU time 0.73 seconds
Started Aug 02 07:25:25 PM PDT 24
Finished Aug 02 07:25:26 PM PDT 24
Peak memory 201096 kb
Host smart-49d5321a-9d2f-42af-bb1f-c020cfa5a51a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669364897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.2669364897
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.459681264
Short name T663
Test name
Test status
Simulation time 570734139 ps
CPU time 3.29 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:28 PM PDT 24
Peak memory 201268 kb
Host smart-ddbd6f9e-61ab-48f3-abcf-29018c9e42a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459681264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.459681264
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.2603577129
Short name T11
Test name
Test status
Simulation time 22046833 ps
CPU time 0.83 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201176 kb
Host smart-1cf814f1-f3fb-4fe3-865b-c116aaa50287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603577129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.2603577129
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.348919556
Short name T486
Test name
Test status
Simulation time 7549838580 ps
CPU time 40.4 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:26:04 PM PDT 24
Peak memory 201504 kb
Host smart-68e66ad1-2bf9-4ea9-89cd-643705883b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348919556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.348919556
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.1309675407
Short name T165
Test name
Test status
Simulation time 105036426274 ps
CPU time 613.14 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:35:37 PM PDT 24
Peak memory 209724 kb
Host smart-b08c7ec6-4688-44f8-84f5-f4e30d9a4dfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1309675407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.1309675407
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.2180707857
Short name T356
Test name
Test status
Simulation time 21638568 ps
CPU time 0.84 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:25 PM PDT 24
Peak memory 201116 kb
Host smart-570ff813-e7c3-427e-84e7-61f4f51f5657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180707857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2180707857
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.4074389346
Short name T537
Test name
Test status
Simulation time 37154739 ps
CPU time 0.81 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201172 kb
Host smart-f03c419c-9859-478c-a65a-34fed3a81bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074389346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.4074389346
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.1290123177
Short name T793
Test name
Test status
Simulation time 133540474 ps
CPU time 1.23 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201060 kb
Host smart-a0672f6f-69c0-4984-a55e-ae308907c356
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290123177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.1290123177
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.1708731713
Short name T605
Test name
Test status
Simulation time 16144725 ps
CPU time 0.7 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:26 PM PDT 24
Peak memory 201076 kb
Host smart-bfbc36b8-efe8-42bc-b99c-e56b384e67ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708731713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1708731713
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.1047239313
Short name T399
Test name
Test status
Simulation time 94345082 ps
CPU time 1.08 seconds
Started Aug 02 07:25:22 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201104 kb
Host smart-09bccf2b-1092-4197-8153-d31813e81230
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047239313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.1047239313
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.3546432544
Short name T573
Test name
Test status
Simulation time 64742740 ps
CPU time 0.98 seconds
Started Aug 02 07:25:25 PM PDT 24
Finished Aug 02 07:25:26 PM PDT 24
Peak memory 201040 kb
Host smart-5d76a141-199c-4d6e-94f8-dcc7cf107f41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546432544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3546432544
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.741416401
Short name T686
Test name
Test status
Simulation time 1493752873 ps
CPU time 6.42 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:31 PM PDT 24
Peak memory 201144 kb
Host smart-be13bf9e-30de-43f0-b5c8-81929dd461ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741416401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.741416401
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.925384429
Short name T460
Test name
Test status
Simulation time 1631266942 ps
CPU time 6.78 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:30 PM PDT 24
Peak memory 201216 kb
Host smart-29b39b70-c7e2-4692-8519-8f590a317f1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925384429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_ti
meout.925384429
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3220907444
Short name T298
Test name
Test status
Simulation time 78245878 ps
CPU time 1.2 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201016 kb
Host smart-383e6c99-fe63-47e6-b218-2f7eccef571f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220907444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.3220907444
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3698496157
Short name T217
Test name
Test status
Simulation time 18653437 ps
CPU time 0.8 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:26 PM PDT 24
Peak memory 201112 kb
Host smart-7a0909c2-fd47-4d91-80bd-44b6dafb90de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698496157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3698496157
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.406303215
Short name T205
Test name
Test status
Simulation time 139191689 ps
CPU time 1.1 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201056 kb
Host smart-b44d558b-ab73-42fb-a8ca-d756226ce169
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406303215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.clkmgr_lc_ctrl_intersig_mubi.406303215
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.422947221
Short name T531
Test name
Test status
Simulation time 19516547 ps
CPU time 0.78 seconds
Started Aug 02 07:25:30 PM PDT 24
Finished Aug 02 07:25:31 PM PDT 24
Peak memory 201108 kb
Host smart-26e6e573-e623-47a7-b8f1-1e5a096c3798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422947221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.422947221
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.832447232
Short name T39
Test name
Test status
Simulation time 719183518 ps
CPU time 2.91 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:27 PM PDT 24
Peak memory 201268 kb
Host smart-1f520cdf-66d8-4cf6-a14d-b2d990aa563a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832447232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.832447232
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.4060947736
Short name T812
Test name
Test status
Simulation time 22815933 ps
CPU time 0.86 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:25 PM PDT 24
Peak memory 201048 kb
Host smart-38021d4d-b7f1-46f5-8b0a-8ed64d49c84d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060947736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.4060947736
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.2277255430
Short name T411
Test name
Test status
Simulation time 6260853813 ps
CPU time 27.09 seconds
Started Aug 02 07:25:27 PM PDT 24
Finished Aug 02 07:25:55 PM PDT 24
Peak memory 201548 kb
Host smart-3239a2f7-1c5b-4329-a801-33588a09f3a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277255430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.2277255430
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.1283169954
Short name T354
Test name
Test status
Simulation time 98765594 ps
CPU time 1.13 seconds
Started Aug 02 07:25:24 PM PDT 24
Finished Aug 02 07:25:26 PM PDT 24
Peak memory 201120 kb
Host smart-e49ad829-ca3c-4406-8c10-19677a007b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283169954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1283169954
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.286672853
Short name T451
Test name
Test status
Simulation time 18592518 ps
CPU time 0.76 seconds
Started Aug 02 07:25:32 PM PDT 24
Finished Aug 02 07:25:33 PM PDT 24
Peak memory 201044 kb
Host smart-dacc3468-e9df-40cf-9f67-0b7ebcb020c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286672853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm
gr_alert_test.286672853
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.1022387345
Short name T317
Test name
Test status
Simulation time 73598522 ps
CPU time 1.06 seconds
Started Aug 02 07:25:37 PM PDT 24
Finished Aug 02 07:25:38 PM PDT 24
Peak memory 201124 kb
Host smart-02c37cc0-cd90-4e93-823d-8ce8c3ab627f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022387345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.1022387345
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.3610050376
Short name T736
Test name
Test status
Simulation time 47449243 ps
CPU time 0.8 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 200324 kb
Host smart-1087f80d-6313-4480-a0e6-ee219fb55c58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610050376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3610050376
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.1697242493
Short name T578
Test name
Test status
Simulation time 33237246 ps
CPU time 1.03 seconds
Started Aug 02 07:25:32 PM PDT 24
Finished Aug 02 07:25:33 PM PDT 24
Peak memory 201128 kb
Host smart-9aa800e0-2449-4298-bf6f-8ed1c8c90ed9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697242493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.1697242493
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.3713836960
Short name T413
Test name
Test status
Simulation time 17198499 ps
CPU time 0.77 seconds
Started Aug 02 07:25:26 PM PDT 24
Finished Aug 02 07:25:27 PM PDT 24
Peak memory 201108 kb
Host smart-d15c3e8a-f6e9-486d-92c5-d4afff43b92b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713836960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.3713836960
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.4134094648
Short name T661
Test name
Test status
Simulation time 1851280770 ps
CPU time 8.51 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:32 PM PDT 24
Peak memory 201312 kb
Host smart-b4e7bfc9-5e43-4287-8015-e2948b090a5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134094648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.4134094648
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.377422332
Short name T692
Test name
Test status
Simulation time 1819829551 ps
CPU time 9.5 seconds
Started Aug 02 07:25:26 PM PDT 24
Finished Aug 02 07:25:36 PM PDT 24
Peak memory 201284 kb
Host smart-a2d43b90-7cdb-4e54-bc3b-e3a6c7dc4685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377422332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_ti
meout.377422332
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.2396570736
Short name T334
Test name
Test status
Simulation time 16275195 ps
CPU time 0.79 seconds
Started Aug 02 07:25:23 PM PDT 24
Finished Aug 02 07:25:24 PM PDT 24
Peak memory 201096 kb
Host smart-291a0deb-9769-48c5-a0d8-e778858d610c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396570736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.2396570736
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1966348563
Short name T318
Test name
Test status
Simulation time 25633715 ps
CPU time 0.78 seconds
Started Aug 02 07:25:32 PM PDT 24
Finished Aug 02 07:25:33 PM PDT 24
Peak memory 201140 kb
Host smart-3bcad669-751d-4d38-a67f-0d16f9c70b4b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966348563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.1966348563
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.4086168374
Short name T253
Test name
Test status
Simulation time 59148757 ps
CPU time 0.9 seconds
Started Aug 02 07:25:31 PM PDT 24
Finished Aug 02 07:25:33 PM PDT 24
Peak memory 201036 kb
Host smart-67f41e36-1ef9-492d-a2a5-97096056e4a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086168374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.4086168374
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.1237262770
Short name T272
Test name
Test status
Simulation time 18262257 ps
CPU time 0.79 seconds
Started Aug 02 07:25:26 PM PDT 24
Finished Aug 02 07:25:27 PM PDT 24
Peak memory 201140 kb
Host smart-8994a9d8-f18d-4fb5-b55b-29be8811971a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237262770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1237262770
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.2974470671
Short name T455
Test name
Test status
Simulation time 516729098 ps
CPU time 2.79 seconds
Started Aug 02 07:25:34 PM PDT 24
Finished Aug 02 07:25:38 PM PDT 24
Peak memory 201300 kb
Host smart-45468764-dc4b-481a-8300-392fbcd445a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974470671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2974470671
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.888725782
Short name T821
Test name
Test status
Simulation time 20633976 ps
CPU time 0.85 seconds
Started Aug 02 07:25:21 PM PDT 24
Finished Aug 02 07:25:22 PM PDT 24
Peak memory 201088 kb
Host smart-e9a58c22-20af-4d25-8102-53300931ac00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888725782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.888725782
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.932562544
Short name T539
Test name
Test status
Simulation time 7115580425 ps
CPU time 31.39 seconds
Started Aug 02 07:25:33 PM PDT 24
Finished Aug 02 07:26:04 PM PDT 24
Peak memory 201460 kb
Host smart-5a46fa27-16b5-4d9e-bcf2-4629c155c4ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932562544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.932562544
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.3647616760
Short name T615
Test name
Test status
Simulation time 42487885 ps
CPU time 1.08 seconds
Started Aug 02 07:25:29 PM PDT 24
Finished Aug 02 07:25:30 PM PDT 24
Peak memory 201120 kb
Host smart-41e39766-33c2-43bf-b48a-f9cf69acff90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647616760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3647616760
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.4117221356
Short name T331
Test name
Test status
Simulation time 14427739 ps
CPU time 0.71 seconds
Started Aug 02 07:25:36 PM PDT 24
Finished Aug 02 07:25:37 PM PDT 24
Peak memory 201116 kb
Host smart-a6019c60-ee1a-47eb-90d8-016d996dc073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117221356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.4117221356
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1641673188
Short name T121
Test name
Test status
Simulation time 90513394 ps
CPU time 1.11 seconds
Started Aug 02 07:25:35 PM PDT 24
Finished Aug 02 07:25:36 PM PDT 24
Peak memory 201168 kb
Host smart-5874c354-fa44-42bc-ad2b-db7daaddb7e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641673188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.1641673188
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.166746939
Short name T281
Test name
Test status
Simulation time 15044356 ps
CPU time 0.71 seconds
Started Aug 02 07:25:33 PM PDT 24
Finished Aug 02 07:25:34 PM PDT 24
Peak memory 201024 kb
Host smart-359dbc2e-553b-4923-8ff3-25971b5d2964
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166746939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.166746939
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2966421955
Short name T221
Test name
Test status
Simulation time 67610652 ps
CPU time 0.93 seconds
Started Aug 02 07:25:33 PM PDT 24
Finished Aug 02 07:25:34 PM PDT 24
Peak memory 201092 kb
Host smart-782537cf-5df5-4938-91dd-ebd4b2a64f6b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966421955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.2966421955
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.3528038511
Short name T570
Test name
Test status
Simulation time 90881331 ps
CPU time 1.02 seconds
Started Aug 02 07:25:33 PM PDT 24
Finished Aug 02 07:25:34 PM PDT 24
Peak memory 201060 kb
Host smart-c78c9a91-b22d-4a50-8509-56a241cacacd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528038511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3528038511
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.2821940050
Short name T7
Test name
Test status
Simulation time 200728359 ps
CPU time 2.09 seconds
Started Aug 02 07:25:34 PM PDT 24
Finished Aug 02 07:25:37 PM PDT 24
Peak memory 201232 kb
Host smart-7f2e5288-e888-478f-a9ec-deee29f5751c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821940050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.2821940050
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.1090448127
Short name T218
Test name
Test status
Simulation time 385492025 ps
CPU time 2.55 seconds
Started Aug 02 07:25:34 PM PDT 24
Finished Aug 02 07:25:37 PM PDT 24
Peak memory 201356 kb
Host smart-cd50b98e-34a1-430b-99ec-0c2f2f50d5f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090448127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.1090448127
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.3471293717
Short name T330
Test name
Test status
Simulation time 30063047 ps
CPU time 0.84 seconds
Started Aug 02 07:25:36 PM PDT 24
Finished Aug 02 07:25:37 PM PDT 24
Peak memory 201132 kb
Host smart-d7c4c0e7-cb83-45f9-b39d-bd9a1bf4abde
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471293717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.3471293717
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.903536874
Short name T31
Test name
Test status
Simulation time 75580702 ps
CPU time 1.03 seconds
Started Aug 02 07:25:33 PM PDT 24
Finished Aug 02 07:25:34 PM PDT 24
Peak memory 201164 kb
Host smart-c5484141-c73f-4016-965d-5ff9aab32fea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903536874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.clkmgr_lc_clk_byp_req_intersig_mubi.903536874
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.1833955538
Short name T744
Test name
Test status
Simulation time 28429091 ps
CPU time 0.83 seconds
Started Aug 02 07:25:32 PM PDT 24
Finished Aug 02 07:25:33 PM PDT 24
Peak memory 201092 kb
Host smart-1580770e-8e5c-40dd-805d-6cdbf99f688f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833955538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.1833955538
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.552056713
Short name T759
Test name
Test status
Simulation time 19603568 ps
CPU time 0.76 seconds
Started Aug 02 07:25:33 PM PDT 24
Finished Aug 02 07:25:34 PM PDT 24
Peak memory 201096 kb
Host smart-6f8a4683-2d49-408f-857a-d1ca8a5768d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552056713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.552056713
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.2655666205
Short name T6
Test name
Test status
Simulation time 621433336 ps
CPU time 3.91 seconds
Started Aug 02 07:25:35 PM PDT 24
Finished Aug 02 07:25:39 PM PDT 24
Peak memory 201268 kb
Host smart-042dc7f6-0f3d-4d07-adb7-6dba976ceecb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655666205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2655666205
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.3770104155
Short name T660
Test name
Test status
Simulation time 39401756 ps
CPU time 0.92 seconds
Started Aug 02 07:25:32 PM PDT 24
Finished Aug 02 07:25:33 PM PDT 24
Peak memory 201100 kb
Host smart-1de51acf-7842-489e-81a3-23e0c826dc6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770104155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3770104155
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.2341315768
Short name T696
Test name
Test status
Simulation time 275088600 ps
CPU time 1.96 seconds
Started Aug 02 07:25:34 PM PDT 24
Finished Aug 02 07:25:37 PM PDT 24
Peak memory 201120 kb
Host smart-cadfe088-53c8-4ffe-bb76-37cf79ad389e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341315768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.2341315768
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.1306496582
Short name T72
Test name
Test status
Simulation time 140402207 ps
CPU time 1.34 seconds
Started Aug 02 07:25:34 PM PDT 24
Finished Aug 02 07:25:36 PM PDT 24
Peak memory 201236 kb
Host smart-b5b6fb29-955e-4ff1-a975-4ba1b611b453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306496582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1306496582
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.2831896302
Short name T638
Test name
Test status
Simulation time 18924960 ps
CPU time 0.78 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:22:53 PM PDT 24
Peak memory 201180 kb
Host smart-6d3430b6-c973-4d7e-afba-613ef29d0698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831896302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.2831896302
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.2349253597
Short name T243
Test name
Test status
Simulation time 85215564 ps
CPU time 1.11 seconds
Started Aug 02 07:22:46 PM PDT 24
Finished Aug 02 07:22:48 PM PDT 24
Peak memory 201112 kb
Host smart-2f2c2c19-9967-4af5-8ba7-cf596a6f340c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349253597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.2349253597
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.1398110291
Short name T549
Test name
Test status
Simulation time 40145414 ps
CPU time 0.78 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:22:53 PM PDT 24
Peak memory 201100 kb
Host smart-c4e14139-27dc-4e54-b3ec-65b225a3afde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398110291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1398110291
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.486421425
Short name T641
Test name
Test status
Simulation time 198421452 ps
CPU time 1.44 seconds
Started Aug 02 07:22:46 PM PDT 24
Finished Aug 02 07:22:48 PM PDT 24
Peak memory 201096 kb
Host smart-efe5ebc6-0dac-4781-9157-c722e9cfcc4b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486421425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.clkmgr_div_intersig_mubi.486421425
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.1963098335
Short name T525
Test name
Test status
Simulation time 61142318 ps
CPU time 0.92 seconds
Started Aug 02 07:22:44 PM PDT 24
Finished Aug 02 07:22:45 PM PDT 24
Peak memory 201100 kb
Host smart-97244359-1721-4fa5-bdb6-6e17e3c697cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963098335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.1963098335
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.2585843678
Short name T439
Test name
Test status
Simulation time 1539343445 ps
CPU time 8.19 seconds
Started Aug 02 07:22:44 PM PDT 24
Finished Aug 02 07:22:52 PM PDT 24
Peak memory 201160 kb
Host smart-3dedd6db-0482-40c7-8c4f-9f693d58e805
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585843678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2585843678
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.3040511770
Short name T822
Test name
Test status
Simulation time 2410320340 ps
CPU time 9.24 seconds
Started Aug 02 07:22:50 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201412 kb
Host smart-bf2c5fa7-3bb0-4a6d-ada3-6055b57e2d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040511770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.3040511770
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1984522517
Short name T437
Test name
Test status
Simulation time 70448522 ps
CPU time 1 seconds
Started Aug 02 07:22:46 PM PDT 24
Finished Aug 02 07:22:48 PM PDT 24
Peak memory 201120 kb
Host smart-d83d1f5e-937b-48bd-a840-7f1c0b3b96b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984522517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.1984522517
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2954182137
Short name T465
Test name
Test status
Simulation time 15398411 ps
CPU time 0.78 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:46 PM PDT 24
Peak memory 201188 kb
Host smart-9b2aab3f-56fd-47a7-9669-dc860d04fc59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954182137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.2954182137
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.3972291642
Short name T417
Test name
Test status
Simulation time 23153931 ps
CPU time 0.9 seconds
Started Aug 02 07:22:53 PM PDT 24
Finished Aug 02 07:22:54 PM PDT 24
Peak memory 201036 kb
Host smart-08da1c9d-16a6-484c-ae47-7662d8b09930
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972291642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.3972291642
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3592147621
Short name T683
Test name
Test status
Simulation time 92630817 ps
CPU time 0.97 seconds
Started Aug 02 07:22:43 PM PDT 24
Finished Aug 02 07:22:44 PM PDT 24
Peak memory 201148 kb
Host smart-0368713d-606c-41be-9023-3ad269883240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592147621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3592147621
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.1039260533
Short name T424
Test name
Test status
Simulation time 504392880 ps
CPU time 3.09 seconds
Started Aug 02 07:22:51 PM PDT 24
Finished Aug 02 07:22:54 PM PDT 24
Peak memory 201352 kb
Host smart-a054f3db-b5bb-48ca-8423-bde5ffc0e903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039260533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1039260533
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.4182493437
Short name T288
Test name
Test status
Simulation time 18050470 ps
CPU time 0.82 seconds
Started Aug 02 07:22:31 PM PDT 24
Finished Aug 02 07:22:32 PM PDT 24
Peak memory 201056 kb
Host smart-603264c7-5c2f-4506-b055-6662fcae07e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182493437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.4182493437
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.1630004683
Short name T264
Test name
Test status
Simulation time 5564811169 ps
CPU time 19.39 seconds
Started Aug 02 07:22:47 PM PDT 24
Finished Aug 02 07:23:07 PM PDT 24
Peak memory 201516 kb
Host smart-05c87360-983c-44d8-b26b-1a84a597a0a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630004683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.1630004683
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.2894847583
Short name T342
Test name
Test status
Simulation time 60541968 ps
CPU time 0.91 seconds
Started Aug 02 07:22:50 PM PDT 24
Finished Aug 02 07:22:52 PM PDT 24
Peak memory 200564 kb
Host smart-d067f46c-1a48-4434-a334-80f9804453e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894847583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2894847583
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.2511290845
Short name T518
Test name
Test status
Simulation time 31654545 ps
CPU time 0.76 seconds
Started Aug 02 07:22:46 PM PDT 24
Finished Aug 02 07:22:47 PM PDT 24
Peak memory 201108 kb
Host smart-c2329cae-b9d6-4dc6-9959-e2c94d953f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511290845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.2511290845
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1108299885
Short name T119
Test name
Test status
Simulation time 74232419 ps
CPU time 1.09 seconds
Started Aug 02 07:22:44 PM PDT 24
Finished Aug 02 07:22:45 PM PDT 24
Peak memory 201068 kb
Host smart-9671d170-804b-4a68-995a-f7a3f1ecf41a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108299885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.1108299885
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.2579698880
Short name T524
Test name
Test status
Simulation time 14624291 ps
CPU time 0.71 seconds
Started Aug 02 07:22:44 PM PDT 24
Finished Aug 02 07:22:45 PM PDT 24
Peak memory 200420 kb
Host smart-fe9a4334-c718-4b34-87e1-11a33125f210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579698880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2579698880
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3065237378
Short name T428
Test name
Test status
Simulation time 14736162 ps
CPU time 0.76 seconds
Started Aug 02 07:22:51 PM PDT 24
Finished Aug 02 07:22:52 PM PDT 24
Peak memory 200664 kb
Host smart-d35ce49e-b541-4e93-8a14-ad38ad9d3060
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065237378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.3065237378
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.2218331278
Short name T800
Test name
Test status
Simulation time 37043977 ps
CPU time 0.82 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:46 PM PDT 24
Peak memory 201148 kb
Host smart-ca3776ce-38d5-47f1-962b-f3ce94de46fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218331278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2218331278
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.3757552897
Short name T359
Test name
Test status
Simulation time 1899196479 ps
CPU time 7.03 seconds
Started Aug 02 07:22:48 PM PDT 24
Finished Aug 02 07:22:55 PM PDT 24
Peak memory 201240 kb
Host smart-d95b1efb-40aa-4480-b05d-31b0f28db1bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757552897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3757552897
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.4204658416
Short name T618
Test name
Test status
Simulation time 976813075 ps
CPU time 7.85 seconds
Started Aug 02 07:22:53 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201312 kb
Host smart-cf3fab7a-0c9b-488f-9723-f91ab2204ee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204658416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.4204658416
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.2729942942
Short name T526
Test name
Test status
Simulation time 116757244 ps
CPU time 1.22 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:46 PM PDT 24
Peak memory 201184 kb
Host smart-2f81bf61-bb5d-4595-92bb-3271ed3e1462
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729942942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.2729942942
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.1824898945
Short name T333
Test name
Test status
Simulation time 18334254 ps
CPU time 0.73 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:46 PM PDT 24
Peak memory 201124 kb
Host smart-ddea8049-5f23-4dc2-871c-fa326a602eec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824898945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.1824898945
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.481687273
Short name T550
Test name
Test status
Simulation time 18186921 ps
CPU time 0.82 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:22:53 PM PDT 24
Peak memory 201188 kb
Host smart-e0150bac-f32a-44d9-926d-22a908fa8e3d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481687273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_ctrl_intersig_mubi.481687273
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.4018372779
Short name T438
Test name
Test status
Simulation time 15541718 ps
CPU time 0.75 seconds
Started Aug 02 07:22:49 PM PDT 24
Finished Aug 02 07:22:50 PM PDT 24
Peak memory 201028 kb
Host smart-d70f06de-256d-481f-b7c8-e184294db156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018372779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.4018372779
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.3114617310
Short name T646
Test name
Test status
Simulation time 887801168 ps
CPU time 4.13 seconds
Started Aug 02 07:22:49 PM PDT 24
Finished Aug 02 07:22:53 PM PDT 24
Peak memory 201284 kb
Host smart-b7e33c45-af39-4336-88c8-b1acfdf7a5dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114617310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3114617310
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1834820447
Short name T343
Test name
Test status
Simulation time 22753345 ps
CPU time 0.85 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:46 PM PDT 24
Peak memory 201080 kb
Host smart-11774a99-701d-4906-b41e-87aaab4a4093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834820447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1834820447
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.3632509420
Short name T444
Test name
Test status
Simulation time 5549142881 ps
CPU time 39.18 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:23:32 PM PDT 24
Peak memory 201356 kb
Host smart-880edada-a622-4a16-9e2c-c46e79a4bf19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632509420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.3632509420
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.2487041805
Short name T191
Test name
Test status
Simulation time 29521463 ps
CPU time 0.95 seconds
Started Aug 02 07:22:49 PM PDT 24
Finished Aug 02 07:22:50 PM PDT 24
Peak memory 201044 kb
Host smart-c6f5df8b-a9c6-4013-9546-76b5316ae0ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487041805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.2487041805
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.255302619
Short name T295
Test name
Test status
Simulation time 51616925 ps
CPU time 0.85 seconds
Started Aug 02 07:22:44 PM PDT 24
Finished Aug 02 07:22:45 PM PDT 24
Peak memory 201172 kb
Host smart-302aca73-2580-4e40-b48b-d1c7a54ac5a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255302619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmg
r_alert_test.255302619
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.416692564
Short name T128
Test name
Test status
Simulation time 16929428 ps
CPU time 0.79 seconds
Started Aug 02 07:22:49 PM PDT 24
Finished Aug 02 07:22:50 PM PDT 24
Peak memory 201128 kb
Host smart-a8a5cc43-36fb-4e21-a37a-b52716ee79e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416692564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.416692564
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.2489787294
Short name T456
Test name
Test status
Simulation time 16245728 ps
CPU time 0.72 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:46 PM PDT 24
Peak memory 200316 kb
Host smart-929a41a8-b335-4801-9e27-cbe5b9be00f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489787294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2489787294
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.1975291337
Short name T447
Test name
Test status
Simulation time 23231725 ps
CPU time 0.89 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:22:53 PM PDT 24
Peak memory 201052 kb
Host smart-99cb189b-3f21-400d-adb1-d8dea23a6cf0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975291337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.1975291337
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.3544449513
Short name T750
Test name
Test status
Simulation time 60929594 ps
CPU time 1.04 seconds
Started Aug 02 07:22:50 PM PDT 24
Finished Aug 02 07:22:52 PM PDT 24
Peak memory 201156 kb
Host smart-4d88bc78-430a-4918-890c-20f2df309c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544449513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3544449513
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.1255464142
Short name T747
Test name
Test status
Simulation time 680567011 ps
CPU time 5.67 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:51 PM PDT 24
Peak memory 201188 kb
Host smart-da13348e-aeb8-42a7-8fd7-e96b7148b43c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255464142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.1255464142
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.429382136
Short name T436
Test name
Test status
Simulation time 1951021156 ps
CPU time 9.8 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:55 PM PDT 24
Peak memory 201200 kb
Host smart-3705c017-9421-49a7-8b1a-4678d2751086
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429382136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_tim
eout.429382136
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.3526132938
Short name T651
Test name
Test status
Simulation time 83157188 ps
CPU time 0.99 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:22:53 PM PDT 24
Peak memory 201172 kb
Host smart-f137938e-da9e-42d8-b1ab-7061f5b56038
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526132938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.3526132938
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.2864403151
Short name T557
Test name
Test status
Simulation time 19909117 ps
CPU time 0.86 seconds
Started Aug 02 07:22:47 PM PDT 24
Finished Aug 02 07:22:48 PM PDT 24
Peak memory 201132 kb
Host smart-c10f9ae4-98ba-4fc5-a619-bc7f42ab9408
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864403151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.2864403151
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.4171920137
Short name T792
Test name
Test status
Simulation time 78380079 ps
CPU time 1 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:22:53 PM PDT 24
Peak memory 201160 kb
Host smart-46a5755e-787c-4513-8638-7b616c881ee5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171920137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.4171920137
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.2887902976
Short name T163
Test name
Test status
Simulation time 36464321 ps
CPU time 0.77 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:46 PM PDT 24
Peak memory 201056 kb
Host smart-039bb3e4-654b-4f9b-b2b2-c485a109436e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887902976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2887902976
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.4228596870
Short name T718
Test name
Test status
Simulation time 1441336223 ps
CPU time 5.38 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:50 PM PDT 24
Peak memory 201288 kb
Host smart-bbeb3779-b465-471a-ad3d-c81fd206dc1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228596870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.4228596870
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.1913706343
Short name T617
Test name
Test status
Simulation time 22634546 ps
CPU time 0.84 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:22:53 PM PDT 24
Peak memory 200960 kb
Host smart-9312ea6c-d6bb-4bfb-bdb1-7132145065d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913706343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.1913706343
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.2255563993
Short name T609
Test name
Test status
Simulation time 8560376475 ps
CPU time 28.14 seconds
Started Aug 02 07:22:44 PM PDT 24
Finished Aug 02 07:23:12 PM PDT 24
Peak memory 201488 kb
Host smart-8aed77ad-7bb5-4970-951e-2e390edd9ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255563993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.2255563993
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.1414500282
Short name T626
Test name
Test status
Simulation time 45086108939 ps
CPU time 505.12 seconds
Started Aug 02 07:22:50 PM PDT 24
Finished Aug 02 07:31:16 PM PDT 24
Peak memory 209860 kb
Host smart-8c526651-4598-4c53-b6d7-56618de9cb6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1414500282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.1414500282
Directory /workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.clkmgr_trans.2900157297
Short name T440
Test name
Test status
Simulation time 23583216 ps
CPU time 0.87 seconds
Started Aug 02 07:22:43 PM PDT 24
Finished Aug 02 07:22:44 PM PDT 24
Peak memory 201040 kb
Host smart-8239143e-3375-42da-9c3e-1938b0834d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900157297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2900157297
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.1511428313
Short name T798
Test name
Test status
Simulation time 25972451 ps
CPU time 0.81 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201036 kb
Host smart-e6b740f1-9032-4154-8766-c4f15f7625bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511428313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.1511428313
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.966722863
Short name T227
Test name
Test status
Simulation time 49939348 ps
CPU time 0.98 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:00 PM PDT 24
Peak memory 201068 kb
Host smart-1dc2297e-ed29-45b1-bfbe-7cd4268e2ee1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966722863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.966722863
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.4238696282
Short name T487
Test name
Test status
Simulation time 15480450 ps
CPU time 0.74 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:58 PM PDT 24
Peak memory 200264 kb
Host smart-4bcac711-392c-4385-a6d4-8d202cbdc5e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238696282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.4238696282
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.284547565
Short name T712
Test name
Test status
Simulation time 71063527 ps
CPU time 0.98 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201148 kb
Host smart-b3cb8891-b194-442c-83eb-055c5ab7d96f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284547565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.clkmgr_div_intersig_mubi.284547565
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.3891500409
Short name T493
Test name
Test status
Simulation time 26432966 ps
CPU time 0.9 seconds
Started Aug 02 07:22:44 PM PDT 24
Finished Aug 02 07:22:45 PM PDT 24
Peak memory 201028 kb
Host smart-acc435c1-3747-4cd6-9624-83e63468d82c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891500409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3891500409
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.2986160212
Short name T620
Test name
Test status
Simulation time 1398750502 ps
CPU time 8.25 seconds
Started Aug 02 07:22:50 PM PDT 24
Finished Aug 02 07:22:58 PM PDT 24
Peak memory 201140 kb
Host smart-6aa5ea04-27dc-4814-98e4-616698feb045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986160212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2986160212
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.1713607040
Short name T538
Test name
Test status
Simulation time 1704391773 ps
CPU time 9.72 seconds
Started Aug 02 07:22:45 PM PDT 24
Finished Aug 02 07:22:55 PM PDT 24
Peak memory 201248 kb
Host smart-5573d0dd-c305-414b-9e5c-af3b037ef022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713607040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.1713607040
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.971582240
Short name T200
Test name
Test status
Simulation time 28322133 ps
CPU time 0.82 seconds
Started Aug 02 07:22:54 PM PDT 24
Finished Aug 02 07:22:55 PM PDT 24
Peak memory 201068 kb
Host smart-60dcc022-0ed7-4aac-a07f-5e9b153a8a2a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971582240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.clkmgr_idle_intersig_mubi.971582240
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.143354851
Short name T222
Test name
Test status
Simulation time 105747863 ps
CPU time 1.06 seconds
Started Aug 02 07:23:04 PM PDT 24
Finished Aug 02 07:23:05 PM PDT 24
Peak memory 201116 kb
Host smart-94b25504-89df-492c-ab05-509c17a5b130
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143354851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.clkmgr_lc_clk_byp_req_intersig_mubi.143354851
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2645425700
Short name T92
Test name
Test status
Simulation time 44950692 ps
CPU time 0.92 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201072 kb
Host smart-d0ee8524-d284-4a08-80e6-4e97c1a88333
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645425700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.2645425700
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.3753853318
Short name T418
Test name
Test status
Simulation time 12938851 ps
CPU time 0.72 seconds
Started Aug 02 07:22:53 PM PDT 24
Finished Aug 02 07:22:54 PM PDT 24
Peak memory 200992 kb
Host smart-5a20b590-19e9-402d-b324-63df2eac1fcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753853318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3753853318
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.2867986498
Short name T471
Test name
Test status
Simulation time 1112364727 ps
CPU time 6.23 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:09 PM PDT 24
Peak memory 201300 kb
Host smart-6dae6f65-771d-4aad-bc7d-ec779c6f9f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867986498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.2867986498
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.4148113818
Short name T634
Test name
Test status
Simulation time 27568799 ps
CPU time 0.85 seconds
Started Aug 02 07:22:53 PM PDT 24
Finished Aug 02 07:22:54 PM PDT 24
Peak memory 201020 kb
Host smart-ba9051d3-82f0-4ce8-920d-b59783ef266d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148113818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.4148113818
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.3755267543
Short name T464
Test name
Test status
Simulation time 3409162149 ps
CPU time 15.44 seconds
Started Aug 02 07:22:55 PM PDT 24
Finished Aug 02 07:23:10 PM PDT 24
Peak memory 201468 kb
Host smart-653706a0-87e2-444a-85f1-e43e40db5f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755267543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.3755267543
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.2796212301
Short name T810
Test name
Test status
Simulation time 414497194 ps
CPU time 2.12 seconds
Started Aug 02 07:22:52 PM PDT 24
Finished Aug 02 07:22:55 PM PDT 24
Peak memory 201052 kb
Host smart-e8202182-4072-48d3-b0ce-5eb0d5668482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796212301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2796212301
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.4149261505
Short name T312
Test name
Test status
Simulation time 14270820 ps
CPU time 0.78 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201208 kb
Host smart-4753fcec-c212-4776-afd5-5feb320eeed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149261505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.4149261505
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3681583410
Short name T768
Test name
Test status
Simulation time 81834789 ps
CPU time 1.08 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201208 kb
Host smart-095a67b1-e085-4026-83ca-65160bb620f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681583410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.3681583410
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.533317139
Short name T790
Test name
Test status
Simulation time 21132600 ps
CPU time 0.72 seconds
Started Aug 02 07:22:57 PM PDT 24
Finished Aug 02 07:22:58 PM PDT 24
Peak memory 201000 kb
Host smart-d8312d3f-e4ef-4d60-a1ad-cd1e6e5f7b05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533317139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.533317139
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.3239288720
Short name T59
Test name
Test status
Simulation time 37372654 ps
CPU time 0.88 seconds
Started Aug 02 07:23:00 PM PDT 24
Finished Aug 02 07:23:01 PM PDT 24
Peak memory 201128 kb
Host smart-0cb77abb-482f-4bd0-97f2-91f5b34f75f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239288720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.3239288720
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.2790964781
Short name T479
Test name
Test status
Simulation time 35506171 ps
CPU time 0.85 seconds
Started Aug 02 07:23:02 PM PDT 24
Finished Aug 02 07:23:03 PM PDT 24
Peak memory 201040 kb
Host smart-dceb5dd6-4f8b-4612-9ba5-ea8297bd15f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790964781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.2790964781
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.236773998
Short name T527
Test name
Test status
Simulation time 937020637 ps
CPU time 4.6 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201104 kb
Host smart-cb91c9b0-e3d6-4909-b6e1-0fc5ff005536
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236773998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.236773998
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.245922378
Short name T247
Test name
Test status
Simulation time 535891393 ps
CPU time 2.59 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201228 kb
Host smart-0d2015ca-5d48-404c-94dd-54b7702b581f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245922378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_tim
eout.245922378
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.3328199956
Short name T215
Test name
Test status
Simulation time 18006488 ps
CPU time 0.79 seconds
Started Aug 02 07:22:58 PM PDT 24
Finished Aug 02 07:22:59 PM PDT 24
Peak memory 201136 kb
Host smart-b39b3ca2-94ae-4fea-abad-57d1c3e430dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328199956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.3328199956
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.3366842269
Short name T391
Test name
Test status
Simulation time 19739078 ps
CPU time 0.81 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201100 kb
Host smart-05fc21d3-e1f4-49a8-ba84-94fe1c46d790
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366842269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.3366842269
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1365299586
Short name T462
Test name
Test status
Simulation time 43197310 ps
CPU time 0.98 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:04 PM PDT 24
Peak memory 201148 kb
Host smart-ab0bf866-558a-42e9-893f-2c74b8c06ceb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365299586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.1365299586
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.1093966924
Short name T611
Test name
Test status
Simulation time 35324530 ps
CPU time 0.83 seconds
Started Aug 02 07:22:57 PM PDT 24
Finished Aug 02 07:22:58 PM PDT 24
Peak memory 201084 kb
Host smart-8be51119-9d28-4934-a0ed-26b3f997ae50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093966924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.1093966924
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.1598833433
Short name T656
Test name
Test status
Simulation time 1493582449 ps
CPU time 4.82 seconds
Started Aug 02 07:23:03 PM PDT 24
Finished Aug 02 07:23:08 PM PDT 24
Peak memory 201356 kb
Host smart-9310a3d8-ae5a-4d7e-8e51-73f9193eebe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598833433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1598833433
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.3505208350
Short name T304
Test name
Test status
Simulation time 22001484 ps
CPU time 0.91 seconds
Started Aug 02 07:23:01 PM PDT 24
Finished Aug 02 07:23:02 PM PDT 24
Peak memory 201116 kb
Host smart-ecd4bc6e-b97d-445c-8064-26fa05b706b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505208350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.3505208350
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.595751433
Short name T782
Test name
Test status
Simulation time 5566053712 ps
CPU time 22.74 seconds
Started Aug 02 07:22:59 PM PDT 24
Finished Aug 02 07:23:22 PM PDT 24
Peak memory 201348 kb
Host smart-b3b1df3d-e789-4337-bfc3-8ad676d93ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595751433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.595751433
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_trans.3438422703
Short name T374
Test name
Test status
Simulation time 19223307 ps
CPU time 0.75 seconds
Started Aug 02 07:22:57 PM PDT 24
Finished Aug 02 07:22:58 PM PDT 24
Peak memory 201048 kb
Host smart-ec49e327-8caf-4f08-a641-cbcac8ad2933
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438422703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3438422703
Directory /workspace/9.clkmgr_trans/latest
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