Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	348010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1713082

1

T4

29

T5

22

T6

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	520727	1			T4	42		T5	25		T6	11
values[0x0]	709509	1			T4	19		T5	13		T6	13
values[0x1]	830856	1			T4	20		T5	14		T6	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1857743

1

T4

40

T5

26

T6

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7559	1			T1	1		T20	1		T40	3
valid_sources[0x01]	7895	1			T1	2		T2	5		T116	1
valid_sources[0x02]	8819	1			T1	1		T2	1		T81	4
valid_sources[0x03]	9109	1			T1	1		T2	4		T40	1
valid_sources[0x04]	7167	1			T1	1		T79	3		T8	165
valid_sources[0x05]	7293	1			T1	1		T117	1		T8	312
valid_sources[0x06]	7863	1			T2	1		T79	2		T80	1
valid_sources[0x07]	9368	1			T1	1		T15	1		T2	2
valid_sources[0x08]	7061	1			T1	1		T20	2		T2	6
valid_sources[0x09]	8358	1			T1	1		T40	2		T8	483
valid_sources[0x0a]	7288	1			T5	2		T1	2		T2	1
valid_sources[0x0b]	7606	1			T1	1		T2	2		T80	1
valid_sources[0x0c]	7627	1			T20	1		T2	10		T80	2
valid_sources[0x0d]	7343	1			T5	2		T19	1		T3	6
valid_sources[0x0e]	9296	1			T23	1		T16	4		T20	2
valid_sources[0x0f]	7246	1			T1	3		T2	2		T117	1
valid_sources[0x10]	7555	1			T15	1		T20	1		T2	6
valid_sources[0x11]	7191	1			T5	1		T1	1		T16	1
valid_sources[0x12]	7874	1			T1	3		T2	4		T80	1
valid_sources[0x13]	7524	1			T1	2		T2	3		T172	5
valid_sources[0x14]	7178	1			T23	1		T20	2		T172	2
valid_sources[0x15]	8327	1			T19	4		T2	2		T3	8
valid_sources[0x16]	6873	1			T1	2		T2	2		T8	24
valid_sources[0x17]	8320	1			T1	1		T2	3		T79	3
valid_sources[0x18]	8182	1			T23	1		T1	1		T2	1
valid_sources[0x19]	7029	1			T1	1		T20	1		T2	4
valid_sources[0x1a]	9288	1			T5	3		T79	4		T173	1
valid_sources[0x1b]	6941	1			T1	1		T2	2		T40	10
valid_sources[0x1c]	8438	1			T1	1		T18	4		T80	2
valid_sources[0x1d]	8292	1			T1	2		T15	1		T2	2
valid_sources[0x1e]	7462	1			T40	9		T8	669		T72	1
valid_sources[0x1f]	8066	1			T5	1		T2	1		T40	2
valid_sources[0x20]	7890	1			T5	1		T1	1		T2	1
valid_sources[0x21]	7940	1			T23	1		T1	1		T16	2
valid_sources[0x22]	8096	1			T1	1		T2	4		T80	1
valid_sources[0x23]	7750	1			T1	2		T2	2		T79	1
valid_sources[0x24]	8797	1			T2	2		T81	5		T116	3
valid_sources[0x25]	8196	1			T2	3		T174	3		T8	261
valid_sources[0x26]	7737	1			T5	1		T1	5		T2	1
valid_sources[0x27]	7575	1			T5	1		T1	3		T2	8
valid_sources[0x28]	7211	1			T2	2		T77	2		T8	524
valid_sources[0x29]	7672	1			T5	1		T1	2		T18	1
valid_sources[0x2a]	7803	1			T1	2		T2	1		T40	4
valid_sources[0x2b]	7066	1			T1	1		T16	2		T2	4
valid_sources[0x2c]	7271	1			T1	1		T20	1		T2	3
valid_sources[0x2d]	8295	1			T3	7		T79	2		T40	1
valid_sources[0x2e]	7617	1			T5	1		T2	2		T8	492
valid_sources[0x2f]	7223	1			T2	5		T172	3		T8	311
valid_sources[0x30]	8665	1			T23	1		T1	3		T2	3
valid_sources[0x31]	7135	1			T1	2		T16	1		T20	1
valid_sources[0x32]	6815	1			T16	1		T2	2		T79	6
valid_sources[0x33]	9119	1			T81	2		T116	1		T8	472
valid_sources[0x34]	8093	1			T23	1		T1	1		T40	3
valid_sources[0x35]	8329	1			T1	1		T16	1		T2	3
valid_sources[0x36]	8149	1			T1	1		T20	1		T79	1
valid_sources[0x37]	8029	1			T23	1		T1	1		T2	1
valid_sources[0x38]	9011	1			T1	2		T2	2		T40	2
valid_sources[0x39]	7371	1			T1	1		T20	1		T2	5
valid_sources[0x3a]	8319	1			T5	1		T20	3		T2	7
valid_sources[0x3b]	7364	1			T1	2		T2	3		T82	1
valid_sources[0x3c]	8259	1			T1	2		T2	1		T40	2
valid_sources[0x3d]	7417	1			T1	4		T80	1		T40	5
valid_sources[0x3e]	8985	1			T23	2		T1	1		T20	1
valid_sources[0x3f]	8051	1			T1	1		T2	1		T79	1
valid_sources[0x40]	8268	1			T1	1		T15	1		T20	1
valid_sources[0x41]	7424	1			T5	1		T23	2		T2	1
valid_sources[0x42]	8536	1			T1	2		T2	1		T167	1
valid_sources[0x43]	7314	1			T5	1		T1	3		T2	3
valid_sources[0x44]	7454	1			T1	2		T167	1		T8	332
valid_sources[0x45]	7356	1			T16	1		T2	1		T81	3
valid_sources[0x46]	7601	1			T5	1		T16	1		T20	1
valid_sources[0x47]	7186	1			T1	2		T40	3		T8	366
valid_sources[0x48]	8618	1			T2	1		T80	1		T40	3
valid_sources[0x49]	8353	1			T79	1		T8	16		T9	4
valid_sources[0x4a]	8903	1			T1	4		T2	2		T117	1
valid_sources[0x4b]	7683	1			T5	1		T2	1		T79	2
valid_sources[0x4c]	7782	1			T1	2		T81	4		T8	92
valid_sources[0x4d]	8050	1			T20	2		T2	4		T79	9
valid_sources[0x4e]	8309	1			T1	1		T2	2		T8	635
valid_sources[0x4f]	8227	1			T1	5		T2	2		T40	3
valid_sources[0x50]	8263	1			T5	3		T1	1		T20	1
valid_sources[0x51]	8645	1			T19	3		T2	1		T8	420
valid_sources[0x52]	7481	1			T23	1		T1	3		T16	1
valid_sources[0x53]	8206	1			T1	2		T2	3		T8	683
valid_sources[0x54]	9686	1			T1	2		T20	2		T2	1
valid_sources[0x55]	8072	1			T2	2		T81	4		T8	528
valid_sources[0x56]	7139	1			T20	1		T2	2		T40	1
valid_sources[0x57]	8114	1			T23	4		T1	1		T2	1
valid_sources[0x58]	7804	1			T16	2		T20	1		T2	2
valid_sources[0x59]	7314	1			T2	5		T40	5		T174	4
valid_sources[0x5a]	7929	1			T20	1		T40	2		T167	2
valid_sources[0x5b]	8096	1			T2	1		T79	1		T40	3
valid_sources[0x5c]	8780	1			T2	4		T173	1		T8	959
valid_sources[0x5d]	8970	1			T5	1		T2	1		T3	20
valid_sources[0x5e]	7671	1			T1	3		T19	1		T20	1
valid_sources[0x5f]	7534	1			T1	4		T2	3		T3	19
valid_sources[0x60]	7590	1			T23	1		T1	2		T2	1
valid_sources[0x61]	7165	1			T2	1		T117	1		T8	5
valid_sources[0x62]	8037	1			T1	1		T20	1		T2	2
valid_sources[0x63]	7170	1			T1	2		T2	5		T79	1
valid_sources[0x64]	8073	1			T1	1		T16	2		T20	1
valid_sources[0x65]	8134	1			T1	2		T2	3		T40	5
valid_sources[0x66]	8061	1			T3	4		T8	34		T29	2
valid_sources[0x67]	8926	1			T5	1		T23	1		T2	1
valid_sources[0x68]	7595	1			T1	1		T20	2		T40	3
valid_sources[0x69]	7616	1			T1	2		T2	4		T8	552
valid_sources[0x6a]	8754	1			T1	1		T19	4		T2	4
valid_sources[0x6b]	7684	1			T1	3		T16	1		T2	3
valid_sources[0x6c]	8340	1			T1	1		T2	2		T81	1
valid_sources[0x6d]	8237	1			T2	2		T40	3		T81	1
valid_sources[0x6e]	7672	1			T1	1		T8	277		T76	4
valid_sources[0x6f]	7435	1			T1	1		T20	1		T2	2
valid_sources[0x70]	8056	1			T5	1		T20	2		T2	2
valid_sources[0x71]	8539	1			T1	1		T2	1		T40	1
valid_sources[0x72]	8176	1			T23	2		T1	2		T2	6
valid_sources[0x73]	8416	1			T23	2		T1	1		T40	2
valid_sources[0x74]	7964	1			T1	3		T2	2		T116	1
valid_sources[0x75]	8225	1			T1	1		T16	1		T20	1
valid_sources[0x76]	8582	1			T23	2		T1	3		T2	2
valid_sources[0x77]	7205	1			T20	2		T2	2		T40	1
valid_sources[0x78]	12377	1			T20	1		T40	2		T8	738
valid_sources[0x79]	8202	1			T5	1		T23	1		T1	1
valid_sources[0x7a]	7937	1			T23	2		T173	2		T8	358
valid_sources[0x7b]	6922	1			T23	1		T2	2		T40	5
valid_sources[0x7c]	7426	1			T1	3		T40	3		T8	299
valid_sources[0x7d]	7589	1			T1	2		T2	2		T80	1
valid_sources[0x7e]	7879	1			T1	2		T2	2		T79	5
valid_sources[0x7f]	8227	1			T1	2		T16	1		T2	1
valid_sources[0x80]	9858	1			T23	2		T1	2		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

437800

1

T4

22

T5

14

T6

9

values[0x0]

all_enables

biggest_size

651478

1

T4

5

T5

4

T6

5

values[0x1]

all_enables

biggest_size

623804

1

T4

2

T5

4

T6

4