Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T2
0	1	Covered	T2,T40,T167
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T2
1	0	Covered	T21,T38,T39
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	589114370	8098	0	0
GateOpen_A	589114370	14455	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589114370	8098	0	0
T1	328594	0	0	0
T2	0	12	0	0
T4	14493	4	0	0
T5	9859	0	0	0
T6	14520	0	0	0
T15	8064	0	0	0
T16	5294	0	0	0
T17	18027	0	0	0
T18	4290	0	0	0
T20	0	4	0	0
T21	0	5	0	0
T22	3736	0	0	0
T23	5247	0	0	0
T38	0	20	0	0
T40	0	41	0	0
T77	0	9	0	0
T78	0	4	0	0
T118	0	4	0	0
T167	0	31	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589114370	14455	0	0
T1	328594	0	0	0
T2	0	36	0	0
T3	0	4	0	0
T4	14493	4	0	0
T5	9859	4	0	0
T6	14520	0	0	0
T15	8064	0	0	0
T16	5294	0	0	0
T17	18027	0	0	0
T18	4290	4	0	0
T20	0	8	0	0
T21	0	9	0	0
T22	3736	4	0	0
T23	5247	0	0	0
T77	0	9	0	0
T78	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T2
0	1	Covered	T2,T40,T167
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T2
1	0	Covered	T21,T38,T39
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	64846024	1920	0	0
GateOpen_A	64846024	3508	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64846024	1920	0	0
T1	36497	0	0	0
T2	0	3	0	0
T4	1600	1	0	0
T5	1166	0	0	0
T6	1641	0	0	0
T15	923	0	0	0
T16	571	0	0	0
T17	2131	0	0	0
T18	456	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	426	0	0	0
T23	561	0	0	0
T38	0	5	0	0
T40	0	8	0	0
T77	0	3	0	0
T78	0	1	0	0
T118	0	1	0	0
T167	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64846024	3508	0	0
T1	36497	0	0	0
T2	0	9	0	0
T3	0	1	0	0
T4	1600	1	0	0
T5	1166	1	0	0
T6	1641	0	0	0
T15	923	0	0	0
T16	571	0	0	0
T17	2131	0	0	0
T18	456	1	0	0
T20	0	2	0	0
T21	0	2	0	0
T22	426	1	0	0
T23	561	0	0	0
T77	0	3	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T2
0	1	Covered	T2,T40,T167
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T2
1	0	Covered	T21,T38,T39
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	129692546	2050	0	0
GateOpen_A	129692546	3638	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129692546	2050	0	0
T1	72994	0	0	0
T2	0	3	0	0
T4	3199	1	0	0
T5	2334	0	0	0
T6	3284	0	0	0
T15	1846	0	0	0
T16	1141	0	0	0
T17	4263	0	0	0
T18	910	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	853	0	0	0
T23	1121	0	0	0
T38	0	5	0	0
T40	0	11	0	0
T77	0	2	0	0
T78	0	1	0	0
T118	0	1	0	0
T167	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129692546	3638	0	0
T1	72994	0	0	0
T2	0	9	0	0
T3	0	1	0	0
T4	3199	1	0	0
T5	2334	1	0	0
T6	3284	0	0	0
T15	1846	0	0	0
T16	1141	0	0	0
T17	4263	0	0	0
T18	910	1	0	0
T20	0	2	0	0
T21	0	2	0	0
T22	853	1	0	0
T23	1121	0	0	0
T77	0	2	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T2
0	1	Covered	T2,T40,T167
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T2
1	0	Covered	T21,T38,T39
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	260871673	2065	0	0
GateOpen_A	260871673	3655	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260871673	2065	0	0
T1	146066	0	0	0
T2	0	3	0	0
T4	6462	1	0	0
T5	4239	0	0	0
T6	6396	0	0	0
T15	3530	0	0	0
T16	2388	0	0	0
T17	7755	0	0	0
T18	1949	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	1638	0	0	0
T23	2377	0	0	0
T38	0	5	0	0
T40	0	12	0	0
T77	0	2	0	0
T78	0	1	0	0
T118	0	1	0	0
T167	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260871673	3655	0	0
T1	146066	0	0	0
T2	0	9	0	0
T3	0	1	0	0
T4	6462	1	0	0
T5	4239	1	0	0
T6	6396	0	0	0
T15	3530	0	0	0
T16	2388	0	0	0
T17	7755	0	0	0
T18	1949	1	0	0
T20	0	2	0	0
T21	0	2	0	0
T22	1638	1	0	0
T23	2377	0	0	0
T77	0	2	0	0
T78	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T2
0	1	Covered	T2,T40,T167
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T2
1	0	Covered	T21,T38,T39
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	133704127	2063	0	0
GateOpen_A	133704127	3654	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133704127	2063	0	0
T1	73037	0	0	0
T2	0	3	0	0
T4	3232	1	0	0
T5	2120	0	0	0
T6	3199	0	0	0
T15	1765	0	0	0
T16	1194	0	0	0
T17	3878	0	0	0
T18	975	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	819	0	0	0
T23	1188	0	0	0
T38	0	5	0	0
T40	0	10	0	0
T77	0	2	0	0
T78	0	1	0	0
T118	0	1	0	0
T167	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133704127	3654	0	0
T1	73037	0	0	0
T2	0	9	0	0
T3	0	1	0	0
T4	3232	1	0	0
T5	2120	1	0	0
T6	3199	0	0	0
T15	1765	0	0	0
T16	1194	0	0	0
T17	3878	0	0	0
T18	975	1	0	0
T20	0	2	0	0
T21	0	3	0	0
T22	819	1	0	0
T23	1188	0	0	0
T77	0	2	0	0
T78	0	1	0	0