Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	436473630	45161	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	436473630	45161	0	0
T1	715160	208	0	0
T2	152670	40	0	0
T3	170395	105	0	0
T8	0	2215	0	0
T9	0	99	0	0
T10	0	1285	0	0
T11	0	429	0	0
T12	0	859	0	0
T13	0	1423	0	0
T14	0	1076	0	0
T15	6245	0	0	0
T16	12310	0	0	0
T17	10095	0	0	0
T18	4975	0	0	0
T19	8685	0	0	0
T20	10205	0	0	0
T21	3740	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	87294726	6739	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	6739	0	0
T1	143032	28	0	0
T2	30534	6	0	0
T3	34079	16	0	0
T8	0	355	0	0
T9	0	13	0	0
T10	0	180	0	0
T11	0	64	0	0
T12	0	116	0	0
T13	0	227	0	0
T14	0	172	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	0	0	0
T18	995	0	0	0
T19	1737	0	0	0
T20	2041	0	0	0
T21	748	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	87294726	6639	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	6639	0	0
T1	143032	27	0	0
T2	30534	6	0	0
T3	34079	15	0	0
T8	0	353	0	0
T9	0	13	0	0
T10	0	177	0	0
T11	0	62	0	0
T12	0	115	0	0
T13	0	227	0	0
T14	0	170	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	0	0	0
T18	995	0	0	0
T19	1737	0	0	0
T20	2041	0	0	0
T21	748	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	87294726	9122	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	9122	0	0
T1	143032	42	0	0
T2	30534	8	0	0
T3	34079	21	0	0
T8	0	447	0	0
T9	0	20	0	0
T10	0	288	0	0
T11	0	86	0	0
T12	0	173	0	0
T13	0	289	0	0
T14	0	218	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	0	0	0
T18	995	0	0	0
T19	1737	0	0	0
T20	2041	0	0	0
T21	748	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	87294726	9074	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	9074	0	0
T1	143032	43	0	0
T2	30534	9	0	0
T3	34079	21	0	0
T8	0	442	0	0
T9	0	20	0	0
T10	0	250	0	0
T11	0	85	0	0
T12	0	173	0	0
T13	0	291	0	0
T14	0	218	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	0	0	0
T18	995	0	0	0
T19	1737	0	0	0
T20	2041	0	0	0
T21	748	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	87294726	13587	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	13587	0	0
T1	143032	68	0	0
T2	30534	11	0	0
T3	34079	32	0	0
T8	0	618	0	0
T9	0	33	0	0
T10	0	390	0	0
T11	0	132	0	0
T12	0	282	0	0
T13	0	389	0	0
T14	0	298	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	0	0	0
T18	995	0	0	0
T19	1737	0	0	0
T20	2041	0	0	0
T21	748	0	0	0