Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T40,T8

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	87294726	85423875	0	0
AllClkBypReqTrue_A	87294726	86164	0	0
IoClkBypReqFalse_A	87294726	85367241	0	2334
IoClkBypReqTrue_A	87294726	138562	0	0
LcClkBypAckFalse_A	87294726	85430066	0	0
LcClkBypAckTrue_A	87294726	79973	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	85423875	0	0
T1	143032	142926	0	0
T4	1615	1570	0	0
T5	2031	1587	0	0
T6	1598	1480	0	0
T15	1249	1182	0	0
T16	2462	2308	0	0
T17	2019	1599	0	0
T18	995	912	0	0
T22	1637	1412	0	0
T23	2475	2219	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	86164	0	0
T1	143032	0	0	0
T2	0	336	0	0
T5	2031	326	0	0
T6	1598	77	0	0
T8	0	4991	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	380	0	0
T18	995	0	0	0
T19	1737	0	0	0
T22	1637	62	0	0
T23	2475	0	0	0
T74	0	31	0	0
T80	0	141	0	0
T116	0	71	0	0
T117	0	32	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	85367241	0	2334
T1	143032	142924	0	3
T4	1615	1568	0	3
T5	2031	1433	0	3
T6	1598	1555	0	3
T15	1249	957	0	3
T16	2462	2306	0	3
T17	2019	1550	0	3
T18	995	876	0	3
T22	1637	1383	0	3
T23	2475	2217	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	138562	0	0
T1	143032	0	0	0
T2	0	390	0	0
T5	2031	478	0	0
T6	1598	0	0	0
T8	0	6969	0	0
T15	1249	223	0	0
T16	2462	0	0	0
T17	2019	427	0	0
T18	995	34	0	0
T19	1737	0	0	0
T22	1637	89	0	0
T23	2475	0	0	0
T80	0	357	0	0
T116	0	138	0	0
T117	0	353	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	85430066	0	0
T1	143032	142926	0	0
T4	1615	1570	0	0
T5	2031	1724	0	0
T6	1598	1557	0	0
T15	1249	1097	0	0
T16	2462	2308	0	0
T17	2019	1833	0	0
T18	995	912	0	0
T22	1637	1395	0	0
T23	2475	2219	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	79973	0	0
T1	143032	0	0	0
T2	0	209	0	0
T5	2031	189	0	0
T6	1598	0	0	0
T8	0	4612	0	0
T15	1249	85	0	0
T16	2462	0	0	0
T17	2019	146	0	0
T18	995	0	0	0
T19	1737	0	0	0
T22	1637	79	0	0
T23	2475	0	0	0
T74	0	204	0	0
T80	0	153	0	0
T116	0	80	0	0
T117	0	207	0	0