Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1114105792	9298	0	0
TransStop_A	1114105792	4863	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114105792	9298	0	0
T1	608628	0	0	0
T2	0	57	0	0
T4	26928	4	0	0
T5	17660	0	0	0
T6	26652	0	0	0
T15	14712	0	0	0
T16	9948	22	0	0
T17	32316	0	0	0
T18	8124	0	0	0
T19	0	4	0	0
T20	0	4	0	0
T22	6828	0	0	0
T23	9904	18	0	0
T40	0	69	0	0
T78	0	4	0	0
T79	0	29	0	0
T81	0	46	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1114105792	4863	0	0
T1	608628	0	0	0
T2	0	35	0	0
T4	26928	4	0	0
T5	17660	0	0	0
T6	26652	0	0	0
T15	14712	0	0	0
T16	9948	12	0	0
T17	32316	0	0	0
T18	8124	0	0	0
T20	0	4	0	0
T22	6828	0	0	0
T23	9904	13	0	0
T40	0	31	0	0
T78	0	4	0	0
T79	0	6	0	0
T81	0	28	0	0
T82	0	7	0	0
T118	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	278526448	2346	0	0
TransStop_A	278526448	1236	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526448	2346	0	0
T1	152157	0	0	0
T2	0	17	0	0
T4	6732	1	0	0
T5	4415	0	0	0
T6	6663	0	0	0
T15	3678	0	0	0
T16	2487	3	0	0
T17	8079	0	0	0
T18	2031	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	1707	0	0	0
T23	2476	5	0	0
T40	0	13	0	0
T78	0	1	0	0
T79	0	6	0	0
T81	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526448	1236	0	0
T1	152157	0	0	0
T2	0	10	0	0
T4	6732	1	0	0
T5	4415	0	0	0
T6	6663	0	0	0
T15	3678	0	0	0
T16	2487	0	0	0
T17	8079	0	0	0
T18	2031	0	0	0
T20	0	1	0	0
T22	1707	0	0	0
T23	2476	4	0	0
T40	0	6	0	0
T78	0	1	0	0
T79	0	2	0	0
T81	0	8	0	0
T82	0	1	0	0
T118	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	278526448	2298	0	0
TransStop_A	278526448	1204	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526448	2298	0	0
T1	152157	0	0	0
T2	0	15	0	0
T4	6732	1	0	0
T5	4415	0	0	0
T6	6663	0	0	0
T15	3678	0	0	0
T16	2487	6	0	0
T17	8079	0	0	0
T18	2031	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	1707	0	0	0
T23	2476	5	0	0
T40	0	21	0	0
T78	0	1	0	0
T79	0	6	0	0
T81	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526448	1204	0	0
T1	152157	0	0	0
T2	0	10	0	0
T4	6732	1	0	0
T5	4415	0	0	0
T6	6663	0	0	0
T15	3678	0	0	0
T16	2487	4	0	0
T17	8079	0	0	0
T18	2031	0	0	0
T20	0	1	0	0
T22	1707	0	0	0
T23	2476	3	0	0
T40	0	9	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	4	0	0
T82	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	278526448	2352	0	0
TransStop_A	278526448	1231	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526448	2352	0	0
T1	152157	0	0	0
T2	0	13	0	0
T4	6732	1	0	0
T5	4415	0	0	0
T6	6663	0	0	0
T15	3678	0	0	0
T16	2487	7	0	0
T17	8079	0	0	0
T18	2031	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	1707	0	0	0
T23	2476	3	0	0
T40	0	20	0	0
T78	0	1	0	0
T79	0	8	0	0
T81	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526448	1231	0	0
T1	152157	0	0	0
T2	0	7	0	0
T4	6732	1	0	0
T5	4415	0	0	0
T6	6663	0	0	0
T15	3678	0	0	0
T16	2487	4	0	0
T17	8079	0	0	0
T18	2031	0	0	0
T20	0	1	0	0
T22	1707	0	0	0
T23	2476	2	0	0
T40	0	9	0	0
T78	0	1	0	0
T79	0	2	0	0
T81	0	8	0	0
T82	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	278526448	2302	0	0
TransStop_A	278526448	1192	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526448	2302	0	0
T1	152157	0	0	0
T2	0	12	0	0
T4	6732	1	0	0
T5	4415	0	0	0
T6	6663	0	0	0
T15	3678	0	0	0
T16	2487	6	0	0
T17	8079	0	0	0
T18	2031	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T22	1707	0	0	0
T23	2476	5	0	0
T40	0	15	0	0
T78	0	1	0	0
T79	0	9	0	0
T81	0	15	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526448	1192	0	0
T1	152157	0	0	0
T2	0	8	0	0
T4	6732	1	0	0
T5	4415	0	0	0
T6	6663	0	0	0
T15	3678	0	0	0
T16	2487	4	0	0
T17	8079	0	0	0
T18	2031	0	0	0
T20	0	1	0	0
T22	1707	0	0	0
T23	2476	4	0	0
T40	0	7	0	0
T78	0	1	0	0
T79	0	1	0	0
T81	0	8	0	0
T82	0	2	0	0