Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT5,T6,T22 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T22
11CoveredT5,T6,T22 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T6,T22
10CoveredT4,T5,T6
11CoveredT4,T5,T6
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 324029349 324027015 0 0
selKnown1 782613729 782611395 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 324029349 324027015 0 0
T1 182485 182482 0 0
T4 7995 7992 0 0
T5 5551 5548 0 0
T6 8070 8067 0 0
T15 4480 4477 0 0
T16 2850 2847 0 0
T17 10223 10220 0 0
T18 2273 2270 0 0
T22 2084 2081 0 0
T23 2802 2799 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 782613729 782611395 0 0
T1 438198 438195 0 0
T4 19386 19383 0 0
T5 12717 12714 0 0
T6 19188 19185 0 0
T15 10590 10587 0 0
T16 7161 7158 0 0
T17 23265 23262 0 0
T18 5847 5844 0 0
T22 4911 4908 0 0
T23 7128 7125 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T6
11CoveredT4,T5,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 129692164 129691386 0 0
selKnown1 260871243 260870465 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 129692164 129691386 0 0
T1 72994 72993 0 0
T4 3198 3197 0 0
T5 2333 2332 0 0
T6 3284 3283 0 0
T15 1846 1845 0 0
T16 1140 1139 0 0
T17 4262 4261 0 0
T18 910 909 0 0
T22 852 851 0 0
T23 1121 1120 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 260871243 260870465 0 0
T1 146066 146065 0 0
T4 6462 6461 0 0
T5 4239 4238 0 0
T6 6396 6395 0 0
T15 3530 3529 0 0
T16 2387 2386 0 0
T17 7755 7754 0 0
T18 1949 1948 0 0
T22 1637 1636 0 0
T23 2376 2375 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT5,T6,T22 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T22
11CoveredT5,T6,T22 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT5,T6,T22
10CoveredT4,T5,T6
11CoveredT4,T5,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 129491539 129490761 0 0
selKnown1 260871243 260870465 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 129491539 129490761 0 0
T1 72994 72993 0 0
T4 3198 3197 0 0
T5 2052 2051 0 0
T6 3145 3144 0 0
T15 1712 1711 0 0
T16 1140 1139 0 0
T17 3831 3830 0 0
T18 908 907 0 0
T22 806 805 0 0
T23 1121 1120 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 260871243 260870465 0 0
T1 146066 146065 0 0
T4 6462 6461 0 0
T5 4239 4238 0 0
T6 6396 6395 0 0
T15 3530 3529 0 0
T16 2387 2386 0 0
T17 7755 7754 0 0
T18 1949 1948 0 0
T22 1637 1636 0 0
T23 2376 2375 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT4,T5,T6
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT4,T5,T6
11CoveredT4,T5,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 64845646 64844868 0 0
selKnown1 260871243 260870465 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 64845646 64844868 0 0
T1 36497 36496 0 0
T4 1599 1598 0 0
T5 1166 1165 0 0
T6 1641 1640 0 0
T15 922 921 0 0
T16 570 569 0 0
T17 2130 2129 0 0
T18 455 454 0 0
T22 426 425 0 0
T23 560 559 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 260871243 260870465 0 0
T1 146066 146065 0 0
T4 6462 6461 0 0
T5 4239 4238 0 0
T6 6396 6395 0 0
T15 3530 3529 0 0
T16 2387 2386 0 0
T17 7755 7754 0 0
T18 1949 1948 0 0
T22 1637 1636 0 0
T23 2376 2375 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%