Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	87294726	12112747	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	12112747	0	59
T1	143032	23724	0	1
T2	30534	3780	0	0
T3	34079	11009	0	1
T8	0	718553	0	0
T9	0	9444	0	1
T10	0	114323	0	1
T11	0	36801	0	1
T12	0	88760	0	0
T13	0	156702	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	0	0	0
T18	995	0	0	0
T19	1737	0	0	0
T20	2041	0	0	0
T21	748	0	0	0
T24	0	0	0	1
T25	0	0	0	1
T30	0	932	0	1
T119	0	0	0	1
T120	0	0	0	1