Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	88164483	2459718	0	0
clk_enables_rd_A	88164483	18245	0	0
clk_hints_rd_A	88164483	16084	0	0
extclk_ctrl_rd_A	88164483	21038	0	0
extclk_ctrl_regwen_rd_A	88164483	14678	0	0
jitter_enable_rd_A	88164483	23375	0	0
jitter_regwen_rd_A	88164483	16741	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88164483	2459718	0	0
T8	483199	173888	0	0
T9	83289	0	0	0
T13	0	119275	0	0
T14	0	111322	0	0
T26	0	87270	0	0
T32	952	0	0	0
T33	978	0	0	0
T39	1097	0	0	0
T66	0	74924	0	0
T67	0	199703	0	0
T68	0	117817	0	0
T69	0	50765	0	0
T70	0	57398	0	0
T71	0	142795	0	0
T72	2406	0	0	0
T73	1544	0	0	0
T74	1965	0	0	0
T75	1915	0	0	0
T76	1406	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88164483	18245	0	0
T1	143032	0	0	0
T2	0	1	0	0
T4	1615	2	0	0
T5	2031	0	0	0
T6	1598	0	0	0
T12	0	7	0	0
T13	0	2564	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	0	0	0
T18	995	0	0	0
T22	1637	0	0	0
T23	2475	0	0	0
T66	0	1569	0	0
T68	0	4313	0	0
T136	0	1	0	0
T137	0	15	0	0
T138	0	4	0	0
T139	0	2	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88164483	16084	0	0
T2	30534	3	0	0
T3	34079	0	0	0
T12	0	7	0	0
T13	0	2144	0	0
T21	748	0	0	0
T38	1675	0	0	0
T40	6084	0	0	0
T66	0	1242	0	0
T68	0	4161	0	0
T77	692	0	0	0
T78	1444	0	0	0
T79	2795	0	0	0
T80	2278	0	0	0
T81	3434	0	0	0
T136	0	2	0	0
T137	0	8	0	0
T138	0	6	0	0
T139	0	3	0	0
T140	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88164483	21038	0	0
T1	143032	0	0	0
T2	30534	70	0	0
T12	0	64	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	37	0	0
T18	995	5	0	0
T19	1737	0	0	0
T20	2041	0	0	0
T22	1637	17	0	0
T23	2475	0	0	0
T75	0	30	0	0
T116	0	37	0	0
T141	0	27	0	0
T142	0	38	0	0
T143	0	40	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88164483	14678	0	0
T13	365194	2220	0	0
T31	13108	41	0	0
T47	0	14	0	0
T66	0	1177	0	0
T68	0	3655	0	0
T83	20187	0	0	0
T144	0	26	0	0
T145	0	19	0	0
T146	0	39	0	0
T147	0	2941	0	0
T148	0	69	0	0
T149	1557	0	0	0
T150	2130	0	0	0
T151	873	0	0	0
T152	89121	0	0	0
T153	1314	0	0	0
T154	1690	0	0	0
T155	980	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88164483	23375	0	0
T1	143032	0	0	0
T2	0	216	0	0
T4	1615	108	0	0
T5	2031	0	0	0
T6	1598	0	0	0
T12	0	60	0	0
T13	0	3204	0	0
T15	1249	0	0	0
T16	2462	0	0	0
T17	2019	0	0	0
T18	995	0	0	0
T22	1637	0	0	0
T23	2475	0	0	0
T66	0	1500	0	0
T68	0	4567	0	0
T136	0	122	0	0
T137	0	460	0	0
T138	0	107	0	0
T156	0	65	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88164483	16741	0	0
T13	365194	2430	0	0
T31	13108	0	0	0
T66	0	1455	0	0
T68	0	4485	0	0
T83	20187	0	0	0
T87	0	22	0	0
T88	0	55	0	0
T106	0	13	0	0
T147	0	3657	0	0
T149	1557	0	0	0
T150	2130	0	0	0
T151	873	0	0	0
T152	89121	0	0	0
T153	1314	0	0	0
T154	1690	0	0	0
T155	980	0	0	0
T157	0	3118	0	0
T158	0	264	0	0
T159	0	2	0	0