Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	261884178	455	0	0
StatusRise_A	261884178	455	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261884178	455	0	0
T21	2244	5	0	0
T38	5025	15	0	0
T39	0	16	0	0
T40	18252	0	0	0
T77	2076	0	0	0
T78	4332	0	0	0
T79	8385	0	0	0
T80	6834	0	0	0
T81	10302	0	0	0
T82	8040	0	0	0
T118	2838	0	0	0
T160	0	6	0	0
T161	0	15	0	0
T162	0	12	0	0
T163	0	4	0	0
T164	0	8	0	0
T165	0	6	0	0
T166	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261884178	455	0	0
T21	2244	5	0	0
T38	5025	15	0	0
T39	0	16	0	0
T40	18252	0	0	0
T77	2076	0	0	0
T78	4332	0	0	0
T79	8385	0	0	0
T80	6834	0	0	0
T81	10302	0	0	0
T82	8040	0	0	0
T118	2838	0	0	0
T160	0	6	0	0
T161	0	15	0	0
T162	0	12	0	0
T163	0	4	0	0
T164	0	8	0	0
T165	0	6	0	0
T166	0	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	87294726	152	0	0
StatusRise_A	87294726	152	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	152	0	0
T21	748	2	0	0
T38	1675	5	0	0
T39	0	6	0	0
T40	6084	0	0	0
T77	692	0	0	0
T78	1444	0	0	0
T79	2795	0	0	0
T80	2278	0	0	0
T81	3434	0	0	0
T82	2680	0	0	0
T118	946	0	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	3	0	0
T166	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	152	0	0
T21	748	2	0	0
T38	1675	5	0	0
T39	0	6	0	0
T40	6084	0	0	0
T77	692	0	0	0
T78	1444	0	0	0
T79	2795	0	0	0
T80	2278	0	0	0
T81	3434	0	0	0
T82	2680	0	0	0
T118	946	0	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	3	0	0
T166	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	87294726	153	0	0
StatusRise_A	87294726	153	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	153	0	0
T21	748	1	0	0
T38	1675	5	0	0
T39	0	5	0	0
T40	6084	0	0	0
T77	692	0	0	0
T78	1444	0	0	0
T79	2795	0	0	0
T80	2278	0	0	0
T81	3434	0	0	0
T82	2680	0	0	0
T118	946	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	153	0	0
T21	748	1	0	0
T38	1675	5	0	0
T39	0	5	0	0
T40	6084	0	0	0
T77	692	0	0	0
T78	1444	0	0	0
T79	2795	0	0	0
T80	2278	0	0	0
T81	3434	0	0	0
T82	2680	0	0	0
T118	946	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	87294726	150	0	0
StatusRise_A	87294726	150	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	150	0	0
T21	748	2	0	0
T38	1675	5	0	0
T39	0	5	0	0
T40	6084	0	0	0
T77	692	0	0	0
T78	1444	0	0	0
T79	2795	0	0	0
T80	2278	0	0	0
T81	3434	0	0	0
T82	2680	0	0	0
T118	946	0	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87294726	150	0	0
T21	748	2	0	0
T38	1675	5	0	0
T39	0	5	0	0
T40	6084	0	0	0
T77	692	0	0	0
T78	1444	0	0	0
T79	2795	0	0	0
T80	2278	0	0	0
T81	3434	0	0	0
T82	2680	0	0	0
T118	946	0	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	5	0	0