Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	31756	0	0
CgEnOn_A	2147483647	23289	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31756	0	0
T1	937221	3	0	0
T4	41414	7	0	0
T5	27517	3	0	0
T6	41167	3	0	0
T15	22771	3	0	0
T16	15238	6	0	0
T17	50336	3	0	0
T18	12409	3	0	0
T19	0	1	0	0
T21	12497	7	0	0
T22	10558	3	0	0
T23	15145	8	0	0
T38	7490	30	0	0
T39	0	25	0	0
T40	54175	0	0	0
T77	13330	0	0	0
T78	26719	0	0	0
T79	12920	0	0	0
T80	11166	0	0	0
T81	34605	0	0	0
T82	12785	0	0	0
T118	21797	0	0	0
T160	0	15	0	0
T161	0	35	0	0
T162	0	20	0	0
T163	0	5	0	0
T164	0	15	0	0
T165	0	10	0	0
T166	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23289	0	0
T1	937221	0	0	0
T2	0	28	0	0
T4	41414	4	0	0
T5	27517	0	0	0
T6	41167	0	0	0
T15	22771	0	0	0
T16	15238	3	0	0
T17	50336	0	0	0
T18	12409	0	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	12497	10	0	0
T22	10558	0	0	0
T23	15145	5	0	0
T38	7490	45	0	0
T39	0	25	0	0
T40	54175	45	0	0
T77	13330	7	0	0
T78	26719	4	0	0
T79	12920	0	0	0
T80	11166	0	0	0
T81	34605	0	0	0
T82	12785	0	0	0
T118	21797	3	0	0
T160	0	15	0	0
T161	0	35	0	0
T162	0	20	0	0
T163	0	5	0	0
T164	0	15	0	0
T165	0	10	0	0
T166	0	15	0	0
T167	0	38	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129692164	157	0	0
CgEnOn_A	129692164	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129692164	157	0	0
T21	1242	1	0	0
T38	768	5	0	0
T39	0	5	0	0
T40	5569	0	0	0
T77	1360	0	0	0
T78	2735	0	0	0
T79	1322	0	0	0
T80	1201	0	0	0
T81	3571	0	0	0
T82	1273	0	0	0
T118	2205	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129692164	157	0	0
T21	1242	1	0	0
T38	768	5	0	0
T39	0	5	0	0
T40	5569	0	0	0
T77	1360	0	0	0
T78	2735	0	0	0
T79	1322	0	0	0
T80	1201	0	0	0
T81	3571	0	0	0
T82	1273	0	0	0
T118	2205	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	64845646	157	0	0
CgEnOn_A	64845646	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64845646	157	0	0
T21	621	1	0	0
T38	384	5	0	0
T39	0	5	0	0
T40	2785	0	0	0
T77	680	0	0	0
T78	1367	0	0	0
T79	661	0	0	0
T80	600	0	0	0
T81	1785	0	0	0
T82	636	0	0	0
T118	1103	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64845646	157	0	0
T21	621	1	0	0
T38	384	5	0	0
T39	0	5	0	0
T40	2785	0	0	0
T77	680	0	0	0
T78	1367	0	0	0
T79	661	0	0	0
T80	600	0	0	0
T81	1785	0	0	0
T82	636	0	0	0
T118	1103	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	64845646	157	0	0
CgEnOn_A	64845646	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64845646	157	0	0
T21	621	1	0	0
T38	384	5	0	0
T39	0	5	0	0
T40	2785	0	0	0
T77	680	0	0	0
T78	1367	0	0	0
T79	661	0	0	0
T80	600	0	0	0
T81	1785	0	0	0
T82	636	0	0	0
T118	1103	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64845646	157	0	0
T21	621	1	0	0
T38	384	5	0	0
T39	0	5	0	0
T40	2785	0	0	0
T77	680	0	0	0
T78	1367	0	0	0
T79	661	0	0	0
T80	600	0	0	0
T81	1785	0	0	0
T82	636	0	0	0
T118	1103	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	64845646	157	0	0
CgEnOn_A	64845646	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64845646	157	0	0
T21	621	1	0	0
T38	384	5	0	0
T39	0	5	0	0
T40	2785	0	0	0
T77	680	0	0	0
T78	1367	0	0	0
T79	661	0	0	0
T80	600	0	0	0
T81	1785	0	0	0
T82	636	0	0	0
T118	1103	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64845646	157	0	0
T21	621	1	0	0
T38	384	5	0	0
T39	0	5	0	0
T40	2785	0	0	0
T77	680	0	0	0
T78	1367	0	0	0
T79	661	0	0	0
T80	600	0	0	0
T81	1785	0	0	0
T82	636	0	0	0
T118	1103	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	260871243	157	0	0
CgEnOn_A	260871243	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260871243	157	0	0
T21	2550	1	0	0
T38	1574	5	0	0
T39	0	5	0	0
T40	11233	0	0	0
T77	2771	0	0	0
T78	5549	0	0	0
T79	2683	0	0	0
T80	2278	0	0	0
T81	7166	0	0	0
T82	2680	0	0	0
T118	4545	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260871243	154	0	0
T21	2550	1	0	0
T38	1574	5	0	0
T39	0	5	0	0
T40	11233	0	0	0
T77	2771	0	0	0
T78	5549	0	0	0
T79	2683	0	0	0
T80	2278	0	0	0
T81	7166	0	0	0
T82	2680	0	0	0
T118	4545	0	0	0
T160	0	3	0	0
T161	0	7	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	2	0	0
T166	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	278526034	152	0	0
CgEnOn_A	278526034	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	152	0	0
T21	2747	2	0	0
T38	1599	5	0	0
T39	0	6	0	0
T40	11701	0	0	0
T77	2887	0	0	0
T78	5780	0	0	0
T79	2795	0	0	0
T80	2374	0	0	0
T81	7465	0	0	0
T82	2792	0	0	0
T118	4733	0	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	3	0	0
T166	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	152	0	0
T21	2747	2	0	0
T38	1599	5	0	0
T39	0	6	0	0
T40	11701	0	0	0
T77	2887	0	0	0
T78	5780	0	0	0
T79	2795	0	0	0
T80	2374	0	0	0
T81	7465	0	0	0
T82	2792	0	0	0
T118	4733	0	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	3	0	0
T166	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	278526034	152	0	0
CgEnOn_A	278526034	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	152	0	0
T21	2747	2	0	0
T38	1599	5	0	0
T39	0	6	0	0
T40	11701	0	0	0
T77	2887	0	0	0
T78	5780	0	0	0
T79	2795	0	0	0
T80	2374	0	0	0
T81	7465	0	0	0
T82	2792	0	0	0
T118	4733	0	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	3	0	0
T166	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	152	0	0
T21	2747	2	0	0
T38	1599	5	0	0
T39	0	6	0	0
T40	11701	0	0	0
T77	2887	0	0	0
T78	5780	0	0	0
T79	2795	0	0	0
T80	2374	0	0	0
T81	7465	0	0	0
T82	2792	0	0	0
T118	4733	0	0	0
T160	0	1	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	3	0	0
T166	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133703730	151	0	0
CgEnOn_A	133703730	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133703730	151	0	0
T21	1348	2	0	0
T38	798	5	0	0
T39	0	5	0	0
T40	5616	0	0	0
T69	0	1	0	0
T77	1385	0	0	0
T78	2774	0	0	0
T79	1342	0	0	0
T80	1139	0	0	0
T81	3583	0	0	0
T82	1340	0	0	0
T118	2272	0	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133703730	150	0	0
T21	1348	2	0	0
T38	798	5	0	0
T39	0	5	0	0
T40	5616	0	0	0
T77	1385	0	0	0
T78	2774	0	0	0
T79	1342	0	0	0
T80	1139	0	0	0
T81	3583	0	0	0
T82	1340	0	0	0
T118	2272	0	0	0
T160	0	2	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T166	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T38,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	64845646	5132	0	0
CgEnOn_A	64845646	3018	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64845646	5132	0	0
T1	36497	1	0	0
T4	1599	2	0	0
T5	1166	1	0	0
T6	1641	1	0	0
T15	922	1	0	0
T16	570	1	0	0
T17	2130	1	0	0
T18	455	1	0	0
T22	426	1	0	0
T23	560	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	64845646	3018	0	0
T1	36497	0	0	0
T2	0	4	0	0
T4	1599	1	0	0
T5	1166	0	0	0
T6	1641	0	0	0
T15	922	0	0	0
T16	570	0	0	0
T17	2130	0	0	0
T18	455	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	426	0	0	0
T23	560	0	0	0
T38	0	5	0	0
T40	0	15	0	0
T77	0	3	0	0
T78	0	1	0	0
T118	0	1	0	0
T167	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T38,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129692164	5155	0	0
CgEnOn_A	129692164	3041	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129692164	5155	0	0
T1	72994	1	0	0
T4	3198	2	0	0
T5	2333	1	0	0
T6	3284	1	0	0
T15	1846	1	0	0
T16	1140	1	0	0
T17	4262	1	0	0
T18	910	1	0	0
T22	852	1	0	0
T23	1121	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129692164	3041	0	0
T1	72994	0	0	0
T2	0	4	0	0
T4	3198	1	0	0
T5	2333	0	0	0
T6	3284	0	0	0
T15	1846	0	0	0
T16	1140	0	0	0
T17	4262	0	0	0
T18	910	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	852	0	0	0
T23	1121	0	0	0
T38	0	5	0	0
T40	0	14	0	0
T77	0	2	0	0
T78	0	1	0	0
T118	0	1	0	0
T167	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T38,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	260871243	5166	0	0
CgEnOn_A	260871243	3049	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260871243	5166	0	0
T1	146066	1	0	0
T4	6462	2	0	0
T5	4239	1	0	0
T6	6396	1	0	0
T15	3530	1	0	0
T16	2387	1	0	0
T17	7755	1	0	0
T18	1949	1	0	0
T22	1637	1	0	0
T23	2376	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	260871243	3049	0	0
T1	146066	0	0	0
T2	0	3	0	0
T4	6462	1	0	0
T5	4239	0	0	0
T6	6396	0	0	0
T15	3530	0	0	0
T16	2387	0	0	0
T17	7755	0	0	0
T18	1949	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	1637	0	0	0
T23	2376	0	0	0
T38	0	5	0	0
T40	0	16	0	0
T77	0	2	0	0
T78	0	1	0	0
T118	0	1	0	0
T167	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T21,T38,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133703730	5157	0	0
CgEnOn_A	133703730	3039	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133703730	5157	0	0
T1	73036	1	0	0
T4	3231	2	0	0
T5	2119	1	0	0
T6	3198	1	0	0
T15	1765	1	0	0
T16	1193	1	0	0
T17	3877	1	0	0
T18	975	1	0	0
T22	819	1	0	0
T23	1188	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133703730	3039	0	0
T1	73036	0	0	0
T2	0	3	0	0
T4	3231	1	0	0
T5	2119	0	0	0
T6	3198	0	0	0
T15	1765	0	0	0
T16	1193	0	0	0
T17	3877	0	0	0
T18	975	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	819	0	0	0
T23	1188	0	0	0
T38	0	5	0	0
T40	0	15	0	0
T77	0	2	0	0
T78	0	1	0	0
T118	0	1	0	0
T167	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Covered	T4,T23,T16
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	278526034	2498	0	0
CgEnOn_A	278526034	2498	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	2498	0	0
T1	152157	0	0	0
T2	0	17	0	0
T4	6731	1	0	0
T5	4415	0	0	0
T6	6662	0	0	0
T15	3677	0	0	0
T16	2487	3	0	0
T17	8078	0	0	0
T18	2030	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	1706	0	0	0
T23	2475	5	0	0
T38	0	5	0	0
T78	0	1	0	0
T79	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	2498	0	0
T1	152157	0	0	0
T2	0	17	0	0
T4	6731	1	0	0
T5	4415	0	0	0
T6	6662	0	0	0
T15	3677	0	0	0
T16	2487	3	0	0
T17	8078	0	0	0
T18	2030	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	1706	0	0	0
T23	2475	5	0	0
T38	0	5	0	0
T78	0	1	0	0
T79	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Covered	T4,T23,T16
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	278526034	2450	0	0
CgEnOn_A	278526034	2450	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	2450	0	0
T1	152157	0	0	0
T2	0	15	0	0
T4	6731	1	0	0
T5	4415	0	0	0
T6	6662	0	0	0
T15	3677	0	0	0
T16	2487	6	0	0
T17	8078	0	0	0
T18	2030	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	1706	0	0	0
T23	2475	5	0	0
T38	0	5	0	0
T78	0	1	0	0
T79	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	2450	0	0
T1	152157	0	0	0
T2	0	15	0	0
T4	6731	1	0	0
T5	4415	0	0	0
T6	6662	0	0	0
T15	3677	0	0	0
T16	2487	6	0	0
T17	8078	0	0	0
T18	2030	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	1706	0	0	0
T23	2475	5	0	0
T38	0	5	0	0
T78	0	1	0	0
T79	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Covered	T4,T23,T16
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	278526034	2504	0	0
CgEnOn_A	278526034	2504	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	2504	0	0
T1	152157	0	0	0
T2	0	13	0	0
T4	6731	1	0	0
T5	4415	0	0	0
T6	6662	0	0	0
T15	3677	0	0	0
T16	2487	7	0	0
T17	8078	0	0	0
T18	2030	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	1706	0	0	0
T23	2475	3	0	0
T38	0	5	0	0
T78	0	1	0	0
T79	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	2504	0	0
T1	152157	0	0	0
T2	0	13	0	0
T4	6731	1	0	0
T5	4415	0	0	0
T6	6662	0	0	0
T15	3677	0	0	0
T16	2487	7	0	0
T17	8078	0	0	0
T18	2030	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	1706	0	0	0
T23	2475	3	0	0
T38	0	5	0	0
T78	0	1	0	0
T79	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T21,T38
1	0	Covered	T4,T23,T16
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	278526034	2454	0	0
CgEnOn_A	278526034	2454	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	2454	0	0
T1	152157	0	0	0
T2	0	12	0	0
T4	6731	1	0	0
T5	4415	0	0	0
T6	6662	0	0	0
T15	3677	0	0	0
T16	2487	6	0	0
T17	8078	0	0	0
T18	2030	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	1706	0	0	0
T23	2475	5	0	0
T38	0	5	0	0
T78	0	1	0	0
T79	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	278526034	2454	0	0
T1	152157	0	0	0
T2	0	12	0	0
T4	6731	1	0	0
T5	4415	0	0	0
T6	6662	0	0	0
T15	3677	0	0	0
T16	2487	6	0	0
T17	8078	0	0	0
T18	2030	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	1706	0	0	0
T23	2475	5	0	0
T38	0	5	0	0
T78	0	1	0	0
T79	0	9	0	0