Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	294361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1398095

1

T8

14

T9

1

T6

55

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	433797	1			T8	13		T9	4		T6	6
values[0x0]	581224	1			T8	15		T6	51		T7	71
values[0x1]	677435	1			T8	12		T9	3		T6	76

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	174090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1518366

1

T8

17

T9

2

T6

90

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6506	1			T1	1		T3	6		T39	1
valid_sources[0x01]	6865	1			T25	1		T27	1		T29	3
valid_sources[0x02]	7073	1			T27	2		T1	1		T2	4
valid_sources[0x03]	6136	1			T25	1		T1	4		T2	1
valid_sources[0x04]	5861	1			T29	2		T35	1		T64	1
valid_sources[0x05]	6311	1			T28	2		T2	5		T3	6
valid_sources[0x06]	7594	1			T27	1		T2	18		T3	4
valid_sources[0x07]	8130	1			T25	1		T26	1		T27	6
valid_sources[0x08]	6438	1			T27	4		T1	2		T3	6
valid_sources[0x09]	7408	1			T25	1		T27	1		T1	1
valid_sources[0x0a]	6052	1			T27	1		T23	35		T2	8
valid_sources[0x0b]	6155	1			T7	3		T25	1		T35	1
valid_sources[0x0c]	6668	1			T7	1		T25	1		T29	2
valid_sources[0x0d]	6651	1			T26	1		T27	3		T2	3
valid_sources[0x0e]	6618	1			T64	1		T1	1		T2	6
valid_sources[0x0f]	6822	1			T7	2		T27	2		T1	2
valid_sources[0x10]	6484	1			T27	2		T1	3		T2	1
valid_sources[0x11]	6450	1			T27	3		T29	1		T64	1
valid_sources[0x12]	5740	1			T27	1		T28	1		T3	5
valid_sources[0x13]	6657	1			T7	1		T28	2		T29	1
valid_sources[0x14]	6181	1			T27	5		T1	1		T2	5
valid_sources[0x15]	6192	1			T27	2		T1	3		T2	1
valid_sources[0x16]	7010	1			T7	1		T25	1		T27	1
valid_sources[0x17]	6078	1			T27	2		T1	2		T3	2
valid_sources[0x18]	7713	1			T27	1		T28	2		T1	3
valid_sources[0x19]	7105	1			T2	3		T3	11		T39	1
valid_sources[0x1a]	6685	1			T26	1		T27	1		T1	3
valid_sources[0x1b]	6173	1			T29	1		T2	2		T3	7
valid_sources[0x1c]	6762	1			T9	2		T27	1		T1	1
valid_sources[0x1d]	5947	1			T7	1		T27	4		T29	1
valid_sources[0x1e]	7234	1			T25	1		T28	1		T1	3
valid_sources[0x1f]	6296	1			T3	23		T122	2		T123	1
valid_sources[0x20]	6825	1			T27	1		T35	1		T1	4
valid_sources[0x21]	6548	1			T25	1		T29	1		T1	3
valid_sources[0x22]	7502	1			T1	2		T2	21		T3	24
valid_sources[0x23]	6279	1			T7	1		T27	2		T29	2
valid_sources[0x24]	6006	1			T26	1		T27	2		T1	2
valid_sources[0x25]	6538	1			T25	1		T27	2		T1	1
valid_sources[0x26]	6745	1			T7	1		T25	2		T27	2
valid_sources[0x27]	6463	1			T7	4		T27	3		T35	1
valid_sources[0x28]	6468	1			T7	1		T27	4		T29	1
valid_sources[0x29]	6802	1			T9	1		T7	3		T27	6
valid_sources[0x2a]	6534	1			T7	1		T27	2		T35	1
valid_sources[0x2b]	7300	1			T7	3		T29	1		T35	1
valid_sources[0x2c]	6299	1			T27	5		T3	14		T122	4
valid_sources[0x2d]	6011	1			T25	2		T2	6		T3	8
valid_sources[0x2e]	6065	1			T29	1		T35	1		T1	2
valid_sources[0x2f]	6489	1			T27	1		T37	3		T39	1
valid_sources[0x30]	6110	1			T27	4		T28	1		T1	2
valid_sources[0x31]	7080	1			T27	2		T1	2		T3	8
valid_sources[0x32]	6607	1			T29	3		T1	1		T2	2
valid_sources[0x33]	6108	1			T9	1		T26	1		T27	1
valid_sources[0x34]	6907	1			T25	1		T29	1		T64	1
valid_sources[0x35]	6447	1			T27	2		T35	2		T1	1
valid_sources[0x36]	6099	1			T64	1		T1	3		T3	2
valid_sources[0x37]	6223	1			T27	3		T28	4		T1	4
valid_sources[0x38]	5695	1			T7	1		T25	1		T26	1
valid_sources[0x39]	5942	1			T26	1		T27	2		T1	2
valid_sources[0x3a]	6635	1			T25	1		T27	2		T1	1
valid_sources[0x3b]	6325	1			T7	1		T25	1		T27	5
valid_sources[0x3c]	6516	1			T25	2		T27	1		T1	1
valid_sources[0x3d]	6143	1			T25	1		T26	1		T2	5
valid_sources[0x3e]	5787	1			T7	3		T27	1		T29	1
valid_sources[0x3f]	6139	1			T27	7		T2	6		T12	260
valid_sources[0x40]	6229	1			T25	1		T26	1		T27	3
valid_sources[0x41]	8821	1			T25	2		T27	1		T29	1
valid_sources[0x42]	6294	1			T7	2		T28	3		T2	8
valid_sources[0x43]	6767	1			T27	3		T28	1		T1	1
valid_sources[0x44]	6259	1			T25	1		T2	20		T3	6
valid_sources[0x45]	5925	1			T7	2		T25	1		T27	1
valid_sources[0x46]	6905	1			T29	1		T1	1		T2	10
valid_sources[0x47]	7555	1			T1	1		T2	4		T3	1
valid_sources[0x48]	7605	1			T27	1		T29	1		T64	1
valid_sources[0x49]	5667	1			T7	2		T27	2		T29	1
valid_sources[0x4a]	6458	1			T7	2		T25	3		T26	1
valid_sources[0x4b]	7317	1			T25	2		T28	8		T29	2
valid_sources[0x4c]	5693	1			T27	1		T35	1		T2	4
valid_sources[0x4d]	6842	1			T25	1		T26	1		T27	2
valid_sources[0x4e]	7012	1			T27	4		T1	3		T2	4
valid_sources[0x4f]	6779	1			T25	2		T27	1		T29	2
valid_sources[0x50]	6426	1			T26	1		T27	2		T29	1
valid_sources[0x51]	6421	1			T7	2		T27	1		T1	1
valid_sources[0x52]	6696	1			T1	4		T2	2		T3	21
valid_sources[0x53]	6254	1			T27	5		T1	2		T2	3
valid_sources[0x54]	6178	1			T26	2		T27	5		T1	1
valid_sources[0x55]	6348	1			T7	1		T27	1		T29	1
valid_sources[0x56]	6424	1			T25	1		T26	1		T35	1
valid_sources[0x57]	6226	1			T35	1		T1	2		T2	5
valid_sources[0x58]	6137	1			T27	1		T1	1		T2	7
valid_sources[0x59]	6469	1			T7	1		T25	1		T27	6
valid_sources[0x5a]	6299	1			T26	1		T27	2		T1	1
valid_sources[0x5b]	6649	1			T1	1		T2	2		T3	3
valid_sources[0x5c]	6813	1			T27	1		T28	1		T29	1
valid_sources[0x5d]	6593	1			T27	5		T2	1		T122	5
valid_sources[0x5e]	6992	1			T27	9		T28	3		T3	22
valid_sources[0x5f]	5895	1			T7	2		T27	1		T64	1
valid_sources[0x60]	6503	1			T7	1		T3	7		T36	3
valid_sources[0x61]	6467	1			T27	2		T2	3		T38	1
valid_sources[0x62]	7949	1			T25	1		T27	5		T1	6
valid_sources[0x63]	6965	1			T27	1		T1	2		T2	15
valid_sources[0x64]	6699	1			T7	2		T27	3		T1	1
valid_sources[0x65]	6151	1			T7	2		T25	2		T3	11
valid_sources[0x66]	6398	1			T7	2		T27	3		T1	7
valid_sources[0x67]	6927	1			T7	1		T25	1		T27	2
valid_sources[0x68]	6418	1			T7	1		T25	1		T27	1
valid_sources[0x69]	6640	1			T7	1		T1	1		T2	8
valid_sources[0x6a]	6768	1			T2	23		T36	3		T12	322
valid_sources[0x6b]	5786	1			T7	2		T25	1		T35	3
valid_sources[0x6c]	6109	1			T29	1		T122	1		T36	1
valid_sources[0x6d]	5923	1			T7	3		T27	1		T64	1
valid_sources[0x6e]	6203	1			T26	1		T27	3		T29	1
valid_sources[0x6f]	6602	1			T7	1		T4	329		T27	1
valid_sources[0x70]	7271	1			T7	1		T27	1		T29	1
valid_sources[0x71]	6730	1			T7	4		T27	4		T29	1
valid_sources[0x72]	6524	1			T27	2		T28	2		T1	2
valid_sources[0x73]	7254	1			T27	3		T1	1		T3	1
valid_sources[0x74]	6220	1			T25	1		T1	2		T36	4
valid_sources[0x75]	6842	1			T26	1		T27	3		T29	1
valid_sources[0x76]	6022	1			T27	2		T2	6		T3	2
valid_sources[0x77]	6239	1			T27	1		T28	1		T29	1
valid_sources[0x78]	5866	1			T7	2		T27	1		T64	1
valid_sources[0x79]	5921	1			T7	1		T25	1		T26	2
valid_sources[0x7a]	7227	1			T25	1		T27	3		T64	1
valid_sources[0x7b]	7913	1			T27	4		T64	2		T1	2
valid_sources[0x7c]	7217	1			T27	1		T29	1		T2	8
valid_sources[0x7d]	6414	1			T25	1		T29	1		T35	1
valid_sources[0x7e]	6052	1			T7	2		T27	1		T1	5
valid_sources[0x7f]	6687	1			T27	6		T1	2		T2	19
valid_sources[0x80]	6645	1			T28	2		T1	3		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

359934

1

T8

6

T9

1

T6

3

values[0x0]

all_enables

biggest_size

532140

1

T8

7

T6

31

T7

46

values[0x1]

all_enables

biggest_size

506021

1

T8

1

T6

21

T7

24