Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T4
0	1	Covered	T18,T23,T2
1	0	Covered	T8,T9,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T28
1	0	Covered	T24,T17,T41
1	1	Covered	T8,T9,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	414929851	7194	0	0
GateOpen_A	414929851	12906	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414929851	7194	0	0
T2	0	101	0	0
T4	102568	0	0	0
T17	0	22	0	0
T18	0	63	0	0
T22	0	4	0	0
T23	0	34	0	0
T24	2693	12	0	0
T25	4064	4	0	0
T26	18704	0	0	0
T27	393559	0	0	0
T28	12005	4	0	0
T29	32564	4	0	0
T30	64346	0	0	0
T35	4544	0	0	0
T64	22838	0	0	0
T121	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414929851	12906	0	0
T1	0	4	0	0
T4	102568	28	0	0
T6	146907	0	0	0
T7	133517	4	0	0
T9	5127	4	0	0
T17	0	26	0	0
T24	2693	16	0	0
T25	4064	4	0	0
T26	18704	0	0	0
T27	393559	0	0	0
T28	12005	8	0	0
T29	32564	8	0	0
T30	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T4
0	1	Covered	T18,T23,T2
1	0	Covered	T8,T9,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T28
1	0	Covered	T24,T17,T41
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	45594196	1724	0	0
GateOpen_A	45594196	3152	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45594196	1724	0	0
T2	0	23	0	0
T4	7303	0	0	0
T17	0	6	0	0
T18	0	15	0	0
T22	0	1	0	0
T23	0	8	0	0
T24	290	3	0	0
T25	432	1	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	1	0	0
T29	3610	1	0	0
T30	6494	0	0	0
T35	516	0	0	0
T64	2718	0	0	0
T121	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45594196	3152	0	0
T1	0	1	0	0
T4	7303	7	0	0
T6	15661	0	0	0
T7	14184	1	0	0
T9	552	1	0	0
T17	0	7	0	0
T24	290	4	0	0
T25	432	1	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	2	0	0
T29	3610	2	0	0
T30	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T4
0	1	Covered	T18,T23,T2
1	0	Covered	T8,T9,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T28
1	0	Covered	T24,T17,T41
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	91188782	1819	0	0
GateOpen_A	91188782	3247	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188782	1819	0	0
T2	0	26	0	0
T4	14603	0	0	0
T17	0	6	0	0
T18	0	15	0	0
T22	0	1	0	0
T23	0	9	0	0
T24	579	3	0	0
T25	863	1	0	0
T26	4468	0	0	0
T27	81684	0	0	0
T28	2660	1	0	0
T29	7219	1	0	0
T30	12988	0	0	0
T35	1032	0	0	0
T64	5438	0	0	0
T121	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188782	3247	0	0
T1	0	1	0	0
T4	14603	7	0	0
T6	31321	0	0	0
T7	28368	1	0	0
T9	1104	1	0	0
T17	0	7	0	0
T24	579	4	0	0
T25	863	1	0	0
T26	4468	0	0	0
T27	81684	0	0	0
T28	2660	2	0	0
T29	7219	2	0	0
T30	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T4
0	1	Covered	T18,T23,T2
1	0	Covered	T8,T9,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T28
1	0	Covered	T24,T17,T41
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	183819597	1827	0	0
GateOpen_A	183819597	3255	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819597	1827	0	0
T2	0	26	0	0
T4	53774	0	0	0
T17	0	6	0	0
T18	0	17	0	0
T22	0	1	0	0
T23	0	8	0	0
T24	1209	3	0	0
T25	1846	1	0	0
T26	8002	0	0	0
T27	163406	0	0	0
T28	5343	1	0	0
T29	14490	1	0	0
T30	26069	0	0	0
T35	1998	0	0	0
T64	9788	0	0	0
T121	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819597	3255	0	0
T1	0	1	0	0
T4	53774	7	0	0
T6	62776	0	0	0
T7	56802	1	0	0
T9	2314	1	0	0
T17	0	7	0	0
T24	1209	4	0	0
T25	1846	1	0	0
T26	8002	0	0	0
T27	163406	0	0	0
T28	5343	2	0	0
T29	14490	2	0	0
T30	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T4
0	1	Covered	T18,T23,T2
1	0	Covered	T8,T9,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T4,T28
1	0	Covered	T24,T17,T41
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	94327276	1824	0	0
GateOpen_A	94327276	3252	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94327276	1824	0	0
T2	0	26	0	0
T4	26888	0	0	0
T17	0	4	0	0
T18	0	16	0	0
T22	0	1	0	0
T23	0	9	0	0
T24	615	3	0	0
T25	923	1	0	0
T26	4002	0	0	0
T27	107627	0	0	0
T28	2672	1	0	0
T29	7245	1	0	0
T30	18795	0	0	0
T35	998	0	0	0
T64	4894	0	0	0
T121	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94327276	3252	0	0
T1	0	1	0	0
T4	26888	7	0	0
T6	37149	0	0	0
T7	34163	1	0	0
T9	1157	1	0	0
T17	0	5	0	0
T24	615	4	0	0
T25	923	1	0	0
T26	4002	0	0	0
T27	107627	0	0	0
T28	2672	2	0	0
T29	7245	2	0	0
T30	0	1	0	0