Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	383994330	38798	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383994330	38798	0	0
T1	161635	129	0	0
T2	535135	185	0	0
T3	0	268	0	0
T5	99530	0	0	0
T10	0	554	0	0
T11	0	149	0	0
T12	0	1020	0	0
T13	0	62	0	0
T14	0	1350	0	0
T15	0	1412	0	0
T16	0	218	0	0
T17	5420	0	0	0
T18	311465	0	0	0
T19	4590	0	0	0
T20	5265	0	0	0
T21	7505	0	0	0
T22	10435	0	0	0
T23	5930	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	76798866	5675	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	5675	0	0
T1	32327	20	0	0
T2	107027	29	0	0
T3	0	39	0	0
T5	19906	0	0	0
T10	0	79	0	0
T11	0	25	0	0
T12	0	150	0	0
T13	0	12	0	0
T14	0	214	0	0
T15	0	226	0	0
T16	0	28	0	0
T17	1084	0	0	0
T18	62293	0	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	76798866	5661	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	5661	0	0
T1	32327	20	0	0
T2	107027	30	0	0
T3	0	39	0	0
T5	19906	0	0	0
T10	0	77	0	0
T11	0	23	0	0
T12	0	149	0	0
T13	0	12	0	0
T14	0	210	0	0
T15	0	224	0	0
T16	0	31	0	0
T17	1084	0	0	0
T18	62293	0	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	76798866	7846	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	7846	0	0
T1	32327	26	0	0
T2	107027	39	0	0
T3	0	60	0	0
T5	19906	0	0	0
T10	0	109	0	0
T11	0	29	0	0
T12	0	203	0	0
T13	0	12	0	0
T14	0	269	0	0
T15	0	286	0	0
T16	0	45	0	0
T17	1084	0	0	0
T18	62293	0	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	76798866	7764	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	7764	0	0
T1	32327	27	0	0
T2	107027	36	0	0
T3	0	52	0	0
T5	19906	0	0	0
T10	0	112	0	0
T11	0	30	0	0
T12	0	204	0	0
T13	0	12	0	0
T14	0	271	0	0
T15	0	286	0	0
T16	0	43	0	0
T17	1084	0	0	0
T18	62293	0	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	76798866	11852	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	11852	0	0
T1	32327	36	0	0
T2	107027	51	0	0
T3	0	78	0	0
T5	19906	0	0	0
T10	0	177	0	0
T11	0	42	0	0
T12	0	314	0	0
T13	0	14	0	0
T14	0	386	0	0
T15	0	390	0	0
T16	0	71	0	0
T17	1084	0	0	0
T18	62293	0	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0