Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T6
0	1	Unreachable
1	0	Covered	T4,T18,T5

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	76798866	75239110	0	0
AllClkBypReqTrue_A	76798866	75895	0	0
IoClkBypReqFalse_A	76798866	75186676	0	2319
IoClkBypReqTrue_A	76798866	124363	0	0
LcClkBypAckFalse_A	76798866	75245549	0	0
LcClkBypAckTrue_A	76798866	69456	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	75239110	0	0
T4	14003	1942	0	0
T6	19347	19305	0	0
T7	19292	19242	0	0
T8	2620	2436	0	0
T9	1157	1034	0	0
T24	1340	1191	0	0
T25	1827	1652	0	0
T26	1249	1133	0	0
T27	230218	230048	0	0
T28	1335	1314	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	75895	0	0
T1	32327	0	0	0
T2	0	567	0	0
T3	0	960	0	0
T17	1084	0	0	0
T18	62293	121	0	0
T20	0	90	0	0
T26	1249	95	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	9788	0	0	0
T35	2060	139	0	0
T64	1528	138	0	0
T108	0	186	0	0
T119	0	406	0	0
T120	0	16	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	75186676	0	2319
T4	14003	1926	0	3
T6	19347	19303	0	3
T7	19292	19240	0	3
T8	2620	1819	0	3
T9	1157	1032	0	3
T24	1340	1189	0	3
T25	1827	1650	0	3
T26	1249	1054	0	3
T27	230218	230046	0	3
T28	1335	1312	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	124363	0	0
T2	0	851	0	0
T3	0	1434	0	0
T4	14003	0	0	0
T6	19347	0	0	0
T7	19292	0	0	0
T8	2620	615	0	0
T9	1157	0	0	0
T18	0	318	0	0
T20	0	195	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	172	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T35	0	28	0	0
T64	0	356	0	0
T108	0	190	0	0
T119	0	538	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	75245549	0	0
T4	14003	1942	0	0
T6	19347	19305	0	0
T7	19292	19242	0	0
T8	2620	2150	0	0
T9	1157	1034	0	0
T24	1340	1191	0	0
T25	1827	1652	0	0
T26	1249	1126	0	0
T27	230218	230048	0	0
T28	1335	1314	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	69456	0	0
T2	0	426	0	0
T3	0	860	0	0
T4	14003	0	0	0
T6	19347	0	0	0
T7	19292	0	0	0
T8	2620	286	0	0
T9	1157	0	0	0
T18	0	117	0	0
T20	0	72	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	102	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T35	0	24	0	0
T64	0	173	0	0
T108	0	71	0	0
T119	0	352	0	0