Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	785778120	7942	0	0
TransStop_A	785778120	4056	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785778120	7942	0	0
T1	461820	0	0	0
T2	0	21	0	0
T3	0	43	0	0
T4	224064	0	0	0
T6	59394	0	0	0
T7	65171	0	0	0
T9	2410	1	0	0
T18	0	23	0	0
T21	0	11	0	0
T22	0	4	0	0
T24	1271	0	0	0
T25	7692	4	0	0
T26	33344	0	0	0
T27	872876	0	0	0
T28	22268	4	0	0
T29	60376	4	0	0
T30	117468	0	0	0
T35	6243	0	0	0
T64	30588	0	0	0
T121	0	4	0	0
T122	0	18	0	0
T123	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785778120	4056	0	0
T1	615760	0	0	0
T2	0	14	0	0
T3	0	17	0	0
T4	224064	0	0	0
T18	0	16	0	0
T21	0	5	0	0
T22	0	4	0	0
T25	7692	4	0	0
T26	33344	0	0	0
T27	872876	0	0	0
T28	22268	4	0	0
T29	60376	4	0	0
T30	156624	0	0	0
T35	8324	0	0	0
T64	40784	0	0	0
T121	0	4	0	0
T122	0	6	0	0
T123	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	196444530	1982	0	0
TransStop_A	196444530	994	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444530	1982	0	0
T2	0	4	0	0
T3	0	11	0	0
T4	56016	0	0	0
T6	59394	0	0	0
T7	65171	0	0	0
T9	2410	1	0	0
T18	0	6	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	1271	0	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218219	0	0	0
T28	5567	1	0	0
T29	15094	1	0	0
T121	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444530	994	0	0
T1	153940	0	0	0
T2	0	2	0	0
T3	0	5	0	0
T4	56016	0	0	0
T18	0	4	0	0
T21	0	1	0	0
T22	0	1	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218219	0	0	0
T28	5567	1	0	0
T29	15094	1	0	0
T30	39156	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0
T122	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	196444530	1975	0	0
TransStop_A	196444530	1025	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444530	1975	0	0
T1	153940	0	0	0
T2	0	6	0	0
T3	0	10	0	0
T4	56016	0	0	0
T18	0	7	0	0
T22	0	1	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218219	0	0	0
T28	5567	1	0	0
T29	15094	1	0	0
T30	39156	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0
T122	0	6	0	0
T123	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444530	1025	0	0
T1	153940	0	0	0
T2	0	4	0	0
T3	0	4	0	0
T4	56016	0	0	0
T18	0	4	0	0
T22	0	1	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218219	0	0	0
T28	5567	1	0	0
T29	15094	1	0	0
T30	39156	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	196444530	2005	0	0
TransStop_A	196444530	1030	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444530	2005	0	0
T1	153940	0	0	0
T2	0	7	0	0
T3	0	11	0	0
T4	56016	0	0	0
T18	0	6	0	0
T21	0	3	0	0
T22	0	1	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218219	0	0	0
T28	5567	1	0	0
T29	15094	1	0	0
T30	39156	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0
T122	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444530	1030	0	0
T1	153940	0	0	0
T2	0	5	0	0
T3	0	5	0	0
T4	56016	0	0	0
T18	0	5	0	0
T21	0	2	0	0
T22	0	1	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218219	0	0	0
T28	5567	1	0	0
T29	15094	1	0	0
T30	39156	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0
T122	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	196444530	1980	0	0
TransStop_A	196444530	1007	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444530	1980	0	0
T1	153940	0	0	0
T2	0	4	0	0
T3	0	11	0	0
T4	56016	0	0	0
T18	0	4	0	0
T21	0	5	0	0
T22	0	1	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218219	0	0	0
T28	5567	1	0	0
T29	15094	1	0	0
T30	39156	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0
T122	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444530	1007	0	0
T1	153940	0	0	0
T2	0	3	0	0
T3	0	3	0	0
T4	56016	0	0	0
T18	0	3	0	0
T21	0	2	0	0
T22	0	1	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218219	0	0	0
T28	5567	1	0	0
T29	15094	1	0	0
T30	39156	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0
T122	0	2	0	0