Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T9,T6
01CoveredT8,T9,T6
10CoveredT8,T26,T35 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T9,T6
10CoveredT8,T26,T35
11CoveredT8,T26,T35 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT8,T26,T35
10CoveredT8,T9,T6
11CoveredT8,T9,T6
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 227816317 227813998 0 0
selKnown1 551457564 551455245 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 227816317 227813998 0 0
T4 36507 36504 0 0
T6 78300 78297 0 0
T7 70920 70917 0 0
T8 3242 3239 0 0
T9 2758 2755 0 0
T24 1445 1442 0 0
T25 2155 2152 0 0
T26 10648 10645 0 0
T27 204210 204207 0 0
T28 6648 6645 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 551457564 551455245 0 0
T4 161322 161319 0 0
T6 188325 188322 0 0
T7 170403 170400 0 0
T8 7548 7545 0 0
T9 6939 6936 0 0
T24 3624 3621 0 0
T25 5535 5532 0 0
T26 24006 24003 0 0
T27 490218 490215 0 0
T28 16029 16026 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T9,T6
01CoveredT8,T9,T6
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T9,T6
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T9,T6
11CoveredT8,T9,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 91188387 91187614 0 0
selKnown1 183819188 183818415 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 91188387 91187614 0 0
T4 14602 14601 0 0
T6 31320 31319 0 0
T7 28368 28367 0 0
T8 1354 1353 0 0
T9 1103 1102 0 0
T24 578 577 0 0
T25 862 861 0 0
T26 4468 4467 0 0
T27 81684 81683 0 0
T28 2659 2658 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 183819188 183818415 0 0
T4 53774 53773 0 0
T6 62775 62774 0 0
T7 56801 56800 0 0
T8 2516 2515 0 0
T9 2313 2312 0 0
T24 1208 1207 0 0
T25 1845 1844 0 0
T26 8002 8001 0 0
T27 163406 163405 0 0
T28 5343 5342 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T9,T6
01CoveredT8,T9,T6
10CoveredT8,T26,T35 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T9,T6
10CoveredT8,T26,T35
11CoveredT8,T26,T35 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT8,T26,T35
10CoveredT8,T9,T6
11CoveredT8,T9,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 91034109 91033336 0 0
selKnown1 183819188 183818415 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 91034109 91033336 0 0
T4 14602 14601 0 0
T6 31320 31319 0 0
T7 28368 28367 0 0
T8 1212 1211 0 0
T9 1103 1102 0 0
T24 578 577 0 0
T25 862 861 0 0
T26 3948 3947 0 0
T27 81684 81683 0 0
T28 2659 2658 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 183819188 183818415 0 0
T4 53774 53773 0 0
T6 62775 62774 0 0
T7 56801 56800 0 0
T8 2516 2515 0 0
T9 2313 2312 0 0
T24 1208 1207 0 0
T25 1845 1844 0 0
T26 8002 8001 0 0
T27 163406 163405 0 0
T28 5343 5342 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT8,T9,T6
01CoveredT8,T9,T6
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT8,T9,T6
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT8,T9,T6
11CoveredT8,T9,T6
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 45593821 45593048 0 0
selKnown1 183819188 183818415 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 45593821 45593048 0 0
T4 7303 7302 0 0
T6 15660 15659 0 0
T7 14184 14183 0 0
T8 676 675 0 0
T9 552 551 0 0
T24 289 288 0 0
T25 431 430 0 0
T26 2232 2231 0 0
T27 40842 40841 0 0
T28 1330 1329 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 183819188 183818415 0 0
T4 53774 53773 0 0
T6 62775 62774 0 0
T7 56801 56800 0 0
T8 2516 2515 0 0
T9 2313 2312 0 0
T24 1208 1207 0 0
T25 1845 1844 0 0
T26 8002 8001 0 0
T27 163406 163405 0 0
T28 5343 5342 0 0

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