Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	76798866	7475207	0	62

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	7475207	0	62
T1	32327	8187	0	1
T2	107027	12022	0	0
T3	0	24150	0	0
T5	19906	0	0	0
T10	0	58212	0	0
T11	0	10721	0	1
T12	0	97704	0	0
T13	0	3051	0	1
T16	0	0	0	1
T17	1084	0	0	0
T18	62293	544	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0
T31	0	811	0	1
T32	0	716	0	1
T33	0	0	0	1
T34	0	0	0	1
T124	0	0	0	1
T125	0	0	0	1