Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	77786784	1977907	0	0
clk_enables_rd_A	77786784	29907	0	0
clk_hints_rd_A	77786784	26669	0	0
extclk_ctrl_rd_A	77786784	30864	0	0
extclk_ctrl_regwen_rd_A	77786784	24347	0	0
jitter_enable_rd_A	77786784	35814	0	0
jitter_regwen_rd_A	77786784	26022	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	1977907	0	0
T12	275279	94614	0	0
T14	0	132099	0	0
T15	0	180165	0	0
T65	0	116319	0	0
T66	0	71402	0	0
T67	0	77436	0	0
T68	0	89043	0	0
T69	0	60051	0	0
T70	0	44661	0	0
T71	0	106506	0	0
T72	1643	0	0	0
T73	2024	0	0	0
T74	1939	0	0	0
T75	1371	0	0	0
T76	859	0	0	0
T77	3401	0	0	0
T78	869	0	0	0
T79	1398	0	0	0
T80	2280	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	29907	0	0
T2	107027	0	0	0
T3	224344	15	0	0
T5	19906	0	0	0
T14	0	5070	0	0
T15	0	7172	0	0
T18	62293	8	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0
T80	0	1	0	0
T121	1344	0	0	0
T142	0	1	0	0
T143	0	6	0	0
T144	0	3	0	0
T145	0	1	0	0
T146	0	1	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	26669	0	0
T2	107027	0	0	0
T3	224344	8	0	0
T5	19906	0	0	0
T14	0	4375	0	0
T15	0	6435	0	0
T18	62293	4	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0
T80	0	3	0	0
T121	1344	0	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	1	0	0
T147	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	30864	0	0
T3	0	198	0	0
T4	14003	0	0	0
T6	19347	0	0	0
T7	19292	0	0	0
T8	2620	65	0	0
T9	1157	0	0	0
T18	0	29	0	0
T24	1340	0	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T64	0	34	0	0
T78	0	17	0	0
T79	0	13	0	0
T108	0	36	0	0
T109	0	29	0	0
T148	0	8	0	0
T149	0	8	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	24347	0	0
T14	458750	4276	0	0
T15	609167	6445	0	0
T70	0	1507	0	0
T71	0	1731	0	0
T150	0	28	0	0
T151	0	4	0	0
T152	0	44	0	0
T153	0	2	0	0
T154	0	61	0	0
T155	0	49	0	0
T156	1926	0	0	0
T157	115642	0	0	0
T158	1841	0	0	0
T159	1197	0	0	0
T160	22361	0	0	0
T161	2964	0	0	0
T162	28951	0	0	0
T163	1131	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	35814	0	0
T2	107027	0	0	0
T3	224344	407	0	0
T5	19906	0	0	0
T14	0	6166	0	0
T15	0	8694	0	0
T18	62293	247	0	0
T19	918	0	0	0
T20	1053	0	0	0
T21	1501	0	0	0
T22	2087	0	0	0
T23	1186	0	0	0
T80	0	88	0	0
T121	1344	0	0	0
T142	0	191	0	0
T143	0	163	0	0
T144	0	120	0	0
T145	0	51	0	0
T147	0	29	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	77786784	26022	0	0
T14	458750	4871	0	0
T15	609167	6921	0	0
T54	0	129	0	0
T57	0	22	0	0
T70	0	1690	0	0
T71	0	2061	0	0
T110	0	74	0	0
T156	1926	0	0	0
T157	115642	0	0	0
T158	1841	0	0	0
T159	1197	0	0	0
T160	22361	0	0	0
T161	2964	0	0	0
T162	28951	0	0	0
T163	1131	0	0	0
T164	0	5109	0	0
T165	0	2318	0	0
T166	0	10	0	0