Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T25
1	0	Covered	T8,T26,T35
1	1	Covered	T8,T26,T35

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	183819597	2730	0	0
g_div2.Div2Whole_A	183819597	3364	0	0
g_div4.Div4Stepped_A	91188782	2672	0	0
g_div4.Div4Whole_A	91188782	3167	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819597	2730	0	0
T2	0	20	0	0
T3	0	28	0	0
T4	53774	0	0	0
T6	62776	0	0	0
T7	56802	0	0	0
T8	2516	7	0	0
T9	2314	0	0	0
T18	0	4	0	0
T20	0	3	0	0
T24	1209	0	0	0
T25	1846	0	0	0
T26	8002	8	0	0
T27	163406	0	0	0
T28	5343	0	0	0
T35	0	1	0	0
T64	0	6	0	0
T108	0	3	0	0
T119	0	16	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819597	3364	0	0
T2	0	25	0	0
T3	0	31	0	0
T4	53774	0	0	0
T6	62776	0	0	0
T7	56802	0	0	0
T8	2516	12	0	0
T9	2314	0	0	0
T18	0	5	0	0
T20	0	4	0	0
T24	1209	0	0	0
T25	1846	0	0	0
T26	8002	7	0	0
T27	163406	0	0	0
T28	5343	0	0	0
T35	0	8	0	0
T64	0	8	0	0
T108	0	4	0	0
T119	0	16	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188782	2672	0	0
T2	0	19	0	0
T3	0	28	0	0
T4	14603	0	0	0
T6	31321	0	0	0
T7	28368	0	0	0
T8	1354	7	0	0
T9	1104	0	0	0
T18	0	4	0	0
T20	0	3	0	0
T24	579	0	0	0
T25	863	0	0	0
T26	4468	8	0	0
T27	81684	0	0	0
T28	2660	0	0	0
T35	0	1	0	0
T64	0	6	0	0
T108	0	3	0	0
T119	0	16	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188782	3167	0	0
T2	0	25	0	0
T3	0	31	0	0
T4	14603	0	0	0
T6	31321	0	0	0
T7	28368	0	0	0
T8	1354	12	0	0
T9	1104	0	0	0
T18	0	5	0	0
T20	0	3	0	0
T24	579	0	0	0
T25	863	0	0	0
T26	4468	7	0	0
T27	81684	0	0	0
T28	2660	0	0	0
T35	0	5	0	0
T64	0	7	0	0
T108	0	4	0	0
T119	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T25
1	0	Covered	T8,T26,T35
1	1	Covered	T8,T26,T35

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	183819597	2730	0	0
g_div2.Div2Whole_A	183819597	3364	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819597	2730	0	0
T2	0	20	0	0
T3	0	28	0	0
T4	53774	0	0	0
T6	62776	0	0	0
T7	56802	0	0	0
T8	2516	7	0	0
T9	2314	0	0	0
T18	0	4	0	0
T20	0	3	0	0
T24	1209	0	0	0
T25	1846	0	0	0
T26	8002	8	0	0
T27	163406	0	0	0
T28	5343	0	0	0
T35	0	1	0	0
T64	0	6	0	0
T108	0	3	0	0
T119	0	16	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819597	3364	0	0
T2	0	25	0	0
T3	0	31	0	0
T4	53774	0	0	0
T6	62776	0	0	0
T7	56802	0	0	0
T8	2516	12	0	0
T9	2314	0	0	0
T18	0	5	0	0
T20	0	4	0	0
T24	1209	0	0	0
T25	1846	0	0	0
T26	8002	7	0	0
T27	163406	0	0	0
T28	5343	0	0	0
T35	0	8	0	0
T64	0	8	0	0
T108	0	4	0	0
T119	0	16	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T8,T6,T25
1	0	Covered	T8,T26,T35
1	1	Covered	T8,T26,T35

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	91188782	2672	0	0
g_div4.Div4Whole_A	91188782	3167	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188782	2672	0	0
T2	0	19	0	0
T3	0	28	0	0
T4	14603	0	0	0
T6	31321	0	0	0
T7	28368	0	0	0
T8	1354	7	0	0
T9	1104	0	0	0
T18	0	4	0	0
T20	0	3	0	0
T24	579	0	0	0
T25	863	0	0	0
T26	4468	8	0	0
T27	81684	0	0	0
T28	2660	0	0	0
T35	0	1	0	0
T64	0	6	0	0
T108	0	3	0	0
T119	0	16	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188782	3167	0	0
T2	0	25	0	0
T3	0	31	0	0
T4	14603	0	0	0
T6	31321	0	0	0
T7	28368	0	0	0
T8	1354	12	0	0
T9	1104	0	0	0
T18	0	5	0	0
T20	0	3	0	0
T24	579	0	0	0
T25	863	0	0	0
T26	4468	7	0	0
T27	81684	0	0	0
T28	2660	0	0	0
T35	0	5	0	0
T64	0	7	0	0
T108	0	4	0	0
T119	0	16	0	0