Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	230396598	460	0	0
StatusRise_A	230396598	460	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230396598	460	0	0
T4	42009	0	0	0
T17	0	15	0	0
T24	4020	9	0	0
T25	5481	0	0	0
T26	3747	0	0	0
T27	690654	0	0	0
T28	4005	0	0	0
T29	3618	0	0	0
T30	29364	0	0	0
T35	6180	0	0	0
T41	0	11	0	0
T49	0	5	0	0
T64	4584	0	0	0
T159	0	9	0	0
T167	0	17	0	0
T168	0	6	0	0
T169	0	12	0	0
T170	0	18	0	0
T171	0	13	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230396598	460	0	0
T4	42009	0	0	0
T17	0	15	0	0
T24	4020	9	0	0
T25	5481	0	0	0
T26	3747	0	0	0
T27	690654	0	0	0
T28	4005	0	0	0
T29	3618	0	0	0
T30	29364	0	0	0
T35	6180	0	0	0
T41	0	11	0	0
T49	0	5	0	0
T64	4584	0	0	0
T159	0	9	0	0
T167	0	17	0	0
T168	0	6	0	0
T169	0	12	0	0
T170	0	18	0	0
T171	0	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	76798866	161	0	0
StatusRise_A	76798866	161	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	161	0	0
T4	14003	0	0	0
T17	0	5	0	0
T24	1340	3	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	9788	0	0	0
T35	2060	0	0	0
T41	0	5	0	0
T49	0	2	0	0
T64	1528	0	0	0
T159	0	2	0	0
T167	0	6	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	6	0	0
T171	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	161	0	0
T4	14003	0	0	0
T17	0	5	0	0
T24	1340	3	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	9788	0	0	0
T35	2060	0	0	0
T41	0	5	0	0
T49	0	2	0	0
T64	1528	0	0	0
T159	0	2	0	0
T167	0	6	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	6	0	0
T171	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	76798866	148	0	0
StatusRise_A	76798866	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	148	0	0
T4	14003	0	0	0
T17	0	6	0	0
T24	1340	3	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	9788	0	0	0
T35	2060	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	1528	0	0	0
T159	0	4	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	148	0	0
T4	14003	0	0	0
T17	0	6	0	0
T24	1340	3	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	9788	0	0	0
T35	2060	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	1528	0	0	0
T159	0	4	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	76798866	151	0	0
StatusRise_A	76798866	151	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	151	0	0
T4	14003	0	0	0
T17	0	4	0	0
T24	1340	3	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	9788	0	0	0
T35	2060	0	0	0
T41	0	2	0	0
T49	0	2	0	0
T64	1528	0	0	0
T159	0	3	0	0
T167	0	6	0	0
T168	0	3	0	0
T169	0	4	0	0
T170	0	7	0	0
T171	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76798866	151	0	0
T4	14003	0	0	0
T17	0	4	0	0
T24	1340	3	0	0
T25	1827	0	0	0
T26	1249	0	0	0
T27	230218	0	0	0
T28	1335	0	0	0
T29	1206	0	0	0
T30	9788	0	0	0
T35	2060	0	0	0
T41	0	2	0	0
T49	0	2	0	0
T64	1528	0	0	0
T159	0	3	0	0
T167	0	6	0	0
T168	0	3	0	0
T169	0	4	0	0
T170	0	7	0	0
T171	0	3	0	0