Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Covered	T8,T9,T6
1	1	Covered	T8,T9,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2099708852	28639	0	0
CgEnOn_A	2099708852	20701	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2099708852	28639	0	0
T4	555836	24	0	0
T6	206298	3	0	0
T7	198686	3	0	0
T8	5803	3	0	0
T9	7535	4	0	0
T14	0	5	0	0
T17	0	35	0	0
T18	0	6	0	0
T24	13582	30	0	0
T25	20522	7	0	0
T26	91886	3	0	0
T27	2178108	3	0	0
T28	60062	7	0	0
T29	130336	1	0	0
T30	273107	0	0	0
T35	15976	0	0	0
T41	0	20	0	0
T49	0	5	0	0
T64	79252	0	0	0
T167	0	25	0	0
T168	0	5	0	0
T169	0	25	0	0
T170	0	25	0	0
T171	0	25	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2099708852	20701	0	0
T2	0	158	0	0
T4	555836	0	0	0
T6	59394	0	0	0
T7	65171	0	0	0
T9	2410	1	0	0
T14	0	4	0	0
T17	0	53	0	0
T18	0	82	0	0
T21	0	3	0	0
T22	0	4	0	0
T23	0	40	0	0
T24	13582	27	0	0
T25	20522	4	0	0
T26	91886	0	0	0
T27	2178108	0	0	0
T28	60062	4	0	0
T29	162896	4	0	0
T30	337451	0	0	0
T35	20517	0	0	0
T41	0	20	0	0
T49	0	5	0	0
T64	102088	0	0	0
T121	0	3	0	0
T159	0	4	0	0
T167	0	25	0	0
T168	0	5	0	0
T169	0	25	0	0
T170	0	25	0	0
T171	0	25	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Unreachable
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91188387	149	0	0
CgEnOn_A	91188387	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188387	149	0	0
T4	14602	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	578	3	0	0
T25	862	0	0	0
T26	4468	0	0	0
T27	81684	0	0	0
T28	2659	0	0	0
T29	7218	0	0	0
T30	12988	0	0	0
T35	1031	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	5437	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188387	149	0	0
T4	14602	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	578	3	0	0
T25	862	0	0	0
T26	4468	0	0	0
T27	81684	0	0	0
T28	2659	0	0	0
T29	7218	0	0	0
T30	12988	0	0	0
T35	1031	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	5437	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Unreachable
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	45593821	149	0	0
CgEnOn_A	45593821	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45593821	149	0	0
T4	7303	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	289	3	0	0
T25	431	0	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	0	0	0
T29	3609	0	0	0
T30	6494	0	0	0
T35	515	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	2718	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45593821	149	0	0
T4	7303	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	289	3	0	0
T25	431	0	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	0	0	0
T29	3609	0	0	0
T30	6494	0	0	0
T35	515	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	2718	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Unreachable
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	45593821	149	0	0
CgEnOn_A	45593821	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45593821	149	0	0
T4	7303	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	289	3	0	0
T25	431	0	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	0	0	0
T29	3609	0	0	0
T30	6494	0	0	0
T35	515	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	2718	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45593821	149	0	0
T4	7303	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	289	3	0	0
T25	431	0	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	0	0	0
T29	3609	0	0	0
T30	6494	0	0	0
T35	515	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	2718	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Unreachable
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	45593821	149	0	0
CgEnOn_A	45593821	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45593821	149	0	0
T4	7303	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	289	3	0	0
T25	431	0	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	0	0	0
T29	3609	0	0	0
T30	6494	0	0	0
T35	515	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	2718	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45593821	149	0	0
T4	7303	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	289	3	0	0
T25	431	0	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	0	0	0
T29	3609	0	0	0
T30	6494	0	0	0
T35	515	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	2718	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Unreachable
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	183819188	149	0	0
CgEnOn_A	183819188	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819188	149	0	0
T4	53774	0	0	0
T14	0	1	0	0
T17	0	6	0	0
T24	1208	3	0	0
T25	1845	0	0	0
T26	8002	0	0	0
T27	163406	0	0	0
T28	5343	0	0	0
T29	14489	0	0	0
T30	26068	0	0	0
T35	1997	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	9788	0	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819188	148	0	0
T4	53774	0	0	0
T17	0	6	0	0
T24	1208	3	0	0
T25	1845	0	0	0
T26	8002	0	0	0
T27	163406	0	0	0
T28	5343	0	0	0
T29	14489	0	0	0
T30	26068	0	0	0
T35	1997	0	0	0
T41	0	4	0	0
T49	0	1	0	0
T64	9788	0	0	0
T159	0	4	0	0
T167	0	5	0	0
T168	0	1	0	0
T169	0	5	0	0
T170	0	5	0	0
T171	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Unreachable
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	196444110	162	0	0
CgEnOn_A	196444110	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	162	0	0
T4	56016	0	0	0
T17	0	5	0	0
T24	1271	3	0	0
T25	1923	0	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	0	0	0
T29	15093	0	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T41	0	5	0	0
T49	0	2	0	0
T64	10196	0	0	0
T159	0	2	0	0
T167	0	6	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	6	0	0
T171	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	161	0	0
T4	56016	0	0	0
T17	0	5	0	0
T24	1271	3	0	0
T25	1923	0	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	0	0	0
T29	15093	0	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T41	0	5	0	0
T49	0	2	0	0
T64	10196	0	0	0
T159	0	2	0	0
T167	0	6	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	6	0	0
T171	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Unreachable
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	196444110	162	0	0
CgEnOn_A	196444110	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	162	0	0
T4	56016	0	0	0
T17	0	5	0	0
T24	1271	3	0	0
T25	1923	0	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	0	0	0
T29	15093	0	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T41	0	5	0	0
T49	0	2	0	0
T64	10196	0	0	0
T159	0	2	0	0
T167	0	6	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	6	0	0
T171	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	161	0	0
T4	56016	0	0	0
T17	0	5	0	0
T24	1271	3	0	0
T25	1923	0	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	0	0	0
T29	15093	0	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T41	0	5	0	0
T49	0	2	0	0
T64	10196	0	0	0
T159	0	2	0	0
T167	0	6	0	0
T168	0	2	0	0
T169	0	3	0	0
T170	0	6	0	0
T171	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Unreachable
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	94326879	152	0	0
CgEnOn_A	94326879	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94326879	152	0	0
T4	26888	0	0	0
T15	0	1	0	0
T17	0	4	0	0
T24	614	3	0	0
T25	923	0	0	0
T26	4001	0	0	0
T27	107626	0	0	0
T28	2671	0	0	0
T29	7244	0	0	0
T30	18794	0	0	0
T35	998	0	0	0
T41	0	2	0	0
T49	0	2	0	0
T64	4893	0	0	0
T167	0	6	0	0
T168	0	3	0	0
T169	0	4	0	0
T170	0	7	0	0
T171	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94326879	151	0	0
T4	26888	0	0	0
T17	0	4	0	0
T24	614	3	0	0
T25	923	0	0	0
T26	4001	0	0	0
T27	107626	0	0	0
T28	2671	0	0	0
T29	7244	0	0	0
T30	18794	0	0	0
T35	998	0	0	0
T41	0	2	0	0
T49	0	2	0	0
T64	4893	0	0	0
T159	0	3	0	0
T167	0	6	0	0
T168	0	3	0	0
T169	0	4	0	0
T170	0	7	0	0
T171	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T17,T41
1	0	Covered	T8,T9,T6
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	45593821	4676	0	0
CgEnOn_A	45593821	2694	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45593821	4676	0	0
T4	7303	8	0	0
T6	15660	1	0	0
T7	14184	1	0	0
T8	676	1	0	0
T9	552	1	0	0
T24	289	4	0	0
T25	431	2	0	0
T26	2232	1	0	0
T27	40842	1	0	0
T28	1330	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	45593821	2694	0	0
T2	0	51	0	0
T4	7303	0	0	0
T17	0	6	0	0
T18	0	25	0	0
T22	0	1	0	0
T23	0	14	0	0
T24	289	3	0	0
T25	431	1	0	0
T26	2232	0	0	0
T27	40842	0	0	0
T28	1330	1	0	0
T29	3609	1	0	0
T30	6494	0	0	0
T35	515	0	0	0
T64	2718	0	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T17,T41
1	0	Covered	T8,T9,T6
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91188387	4710	0	0
CgEnOn_A	91188387	2728	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188387	4710	0	0
T4	14602	8	0	0
T6	31320	1	0	0
T7	28368	1	0	0
T8	1354	1	0	0
T9	1103	1	0	0
T24	578	4	0	0
T25	862	2	0	0
T26	4468	1	0	0
T27	81684	1	0	0
T28	2659	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91188387	2728	0	0
T2	0	51	0	0
T4	14602	0	0	0
T17	0	6	0	0
T18	0	25	0	0
T22	0	1	0	0
T23	0	14	0	0
T24	578	3	0	0
T25	862	1	0	0
T26	4468	0	0	0
T27	81684	0	0	0
T28	2659	1	0	0
T29	7218	1	0	0
T30	12988	0	0	0
T35	1031	0	0	0
T64	5437	0	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T17,T41
1	0	Covered	T8,T9,T6
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	183819188	4722	0	0
CgEnOn_A	183819188	2739	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819188	4722	0	0
T4	53774	8	0	0
T6	62775	1	0	0
T7	56801	1	0	0
T8	2516	1	0	0
T9	2313	1	0	0
T24	1208	4	0	0
T25	1845	2	0	0
T26	8002	1	0	0
T27	163406	1	0	0
T28	5343	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183819188	2739	0	0
T2	0	52	0	0
T4	53774	0	0	0
T17	0	6	0	0
T18	0	26	0	0
T22	0	1	0	0
T23	0	12	0	0
T24	1208	3	0	0
T25	1845	1	0	0
T26	8002	0	0	0
T27	163406	0	0	0
T28	5343	1	0	0
T29	14489	1	0	0
T30	26068	0	0	0
T35	1997	0	0	0
T64	9788	0	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T17,T41
1	0	Covered	T8,T9,T6
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	94326879	4720	0	0
CgEnOn_A	94326879	2737	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94326879	4720	0	0
T4	26888	8	0	0
T6	37149	1	0	0
T7	34162	1	0	0
T8	1257	1	0	0
T9	1157	1	0	0
T24	614	4	0	0
T25	923	2	0	0
T26	4001	1	0	0
T27	107626	1	0	0
T28	2671	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94326879	2737	0	0
T2	0	47	0	0
T4	26888	0	0	0
T17	0	4	0	0
T18	0	24	0	0
T22	0	1	0	0
T23	0	14	0	0
T24	614	3	0	0
T25	923	1	0	0
T26	4001	0	0	0
T27	107626	0	0	0
T28	2671	1	0	0
T29	7244	1	0	0
T30	18794	0	0	0
T35	998	0	0	0
T64	4893	0	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Covered	T9,T25,T28
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	196444110	2144	0	0
CgEnOn_A	196444110	2143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	2144	0	0
T2	0	4	0	0
T4	56016	0	0	0
T6	59394	0	0	0
T7	65171	0	0	0
T9	2410	1	0	0
T17	0	5	0	0
T18	0	6	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	1271	3	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	1	0	0
T29	15093	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	2143	0	0
T2	0	4	0	0
T4	56016	0	0	0
T6	59394	0	0	0
T7	65171	0	0	0
T9	2410	1	0	0
T17	0	5	0	0
T18	0	6	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	1271	3	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	1	0	0
T29	15093	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Covered	T25,T28,T29
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	196444110	2137	0	0
CgEnOn_A	196444110	2136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	2137	0	0
T2	0	6	0	0
T3	0	10	0	0
T4	56016	0	0	0
T17	0	5	0	0
T18	0	7	0	0
T22	0	1	0	0
T24	1271	3	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	1	0	0
T29	15093	1	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	2136	0	0
T2	0	6	0	0
T3	0	10	0	0
T4	56016	0	0	0
T17	0	5	0	0
T18	0	7	0	0
T22	0	1	0	0
T24	1271	3	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	1	0	0
T29	15093	1	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Covered	T25,T28,T29
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	196444110	2167	0	0
CgEnOn_A	196444110	2166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	2167	0	0
T2	0	7	0	0
T4	56016	0	0	0
T17	0	5	0	0
T18	0	6	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	1271	3	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	1	0	0
T29	15093	1	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	2166	0	0
T2	0	7	0	0
T4	56016	0	0	0
T17	0	5	0	0
T18	0	6	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	1271	3	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	1	0	0
T29	15093	1	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T4,T17
1	0	Covered	T25,T28,T29
1	1	Covered	T8,T9,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	196444110	2142	0	0
CgEnOn_A	196444110	2141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	2142	0	0
T2	0	4	0	0
T4	56016	0	0	0
T17	0	5	0	0
T18	0	4	0	0
T21	0	5	0	0
T22	0	1	0	0
T24	1271	3	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	1	0	0
T29	15093	1	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196444110	2141	0	0
T2	0	4	0	0
T4	56016	0	0	0
T17	0	5	0	0
T18	0	4	0	0
T21	0	5	0	0
T22	0	1	0	0
T24	1271	3	0	0
T25	1923	1	0	0
T26	8336	0	0	0
T27	218218	0	0	0
T28	5566	1	0	0
T29	15093	1	0	0
T30	39155	0	0	0
T35	2081	0	0	0
T64	10196	0	0	0
T121	0	1	0	0