Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	239999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

906040

1

T5

219

T7

14

T8

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	304380	1			T5	106		T7	11		T8	14
values[0x0]	388970	1			T5	190		T7	15		T8	17
values[0x1]	452689	1			T5	226		T7	8		T8	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

996659

1

T5

296

T7

14

T8

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4588	1			T6	8		T2	12		T20	2
valid_sources[0x01]	4082	1			T2	19		T12	117		T79	1
valid_sources[0x02]	4089	1			T5	4		T4	31		T2	24
valid_sources[0x03]	4438	1			T2	16		T12	116		T76	1
valid_sources[0x04]	4870	1			T1	5		T2	12		T12	115
valid_sources[0x05]	4223	1			T2	13		T12	148		T79	1
valid_sources[0x06]	4485	1			T1	6		T2	13		T3	1
valid_sources[0x07]	5175	1			T1	9		T2	15		T3	2
valid_sources[0x08]	4342	1			T7	1		T1	5		T2	12
valid_sources[0x09]	4505	1			T6	1		T1	4		T2	9
valid_sources[0x0a]	4352	1			T2	11		T3	2		T12	101
valid_sources[0x0b]	4527	1			T7	1		T6	1		T1	7
valid_sources[0x0c]	4632	1			T1	11		T2	29		T3	3
valid_sources[0x0d]	4416	1			T5	8		T2	21		T3	2
valid_sources[0x0e]	4409	1			T1	3		T2	10		T3	2
valid_sources[0x0f]	4650	1			T5	3		T2	5		T3	1
valid_sources[0x10]	4468	1			T5	1		T6	1		T1	4
valid_sources[0x11]	4229	1			T1	4		T2	15		T3	1
valid_sources[0x12]	4469	1			T30	1		T1	20		T2	6
valid_sources[0x13]	4836	1			T26	2		T27	1		T2	14
valid_sources[0x14]	4752	1			T6	2		T1	21		T2	14
valid_sources[0x15]	4801	1			T2	19		T3	1		T12	119
valid_sources[0x16]	4428	1			T5	4		T6	6		T2	18
valid_sources[0x17]	4419	1			T1	9		T2	5		T3	2
valid_sources[0x18]	4280	1			T7	2		T1	2		T2	11
valid_sources[0x19]	4498	1			T5	10		T26	1		T2	3
valid_sources[0x1a]	4134	1			T35	1		T1	4		T2	1
valid_sources[0x1b]	4922	1			T1	1		T2	9		T12	119
valid_sources[0x1c]	4373	1			T5	15		T1	5		T2	6
valid_sources[0x1d]	5512	1			T2	13		T12	141		T13	2
valid_sources[0x1e]	4700	1			T7	2		T1	1		T2	25
valid_sources[0x1f]	4716	1			T5	1		T7	2		T8	43
valid_sources[0x20]	4376	1			T5	34		T26	2		T2	2
valid_sources[0x21]	4176	1			T5	4		T27	2		T4	10
valid_sources[0x22]	4112	1			T1	1		T2	10		T3	2
valid_sources[0x23]	4480	1			T1	1		T2	2		T3	1
valid_sources[0x24]	4071	1			T6	2		T1	3		T2	3
valid_sources[0x25]	4225	1			T1	9		T2	15		T3	1
valid_sources[0x26]	4096	1			T5	3		T2	17		T12	119
valid_sources[0x27]	4352	1			T4	21		T6	2		T1	1
valid_sources[0x28]	4306	1			T1	1		T2	4		T3	2
valid_sources[0x29]	4323	1			T2	18		T12	143		T15	454
valid_sources[0x2a]	4366	1			T2	6		T3	2		T20	3
valid_sources[0x2b]	4371	1			T1	1		T2	12		T3	1
valid_sources[0x2c]	4556	1			T1	6		T2	25		T3	1
valid_sources[0x2d]	4274	1			T2	18		T3	1		T20	2
valid_sources[0x2e]	4664	1			T2	23		T3	3		T20	1
valid_sources[0x2f]	4177	1			T5	27		T27	2		T2	8
valid_sources[0x30]	4326	1			T1	3		T2	9		T20	3
valid_sources[0x31]	4267	1			T1	2		T2	12		T12	142
valid_sources[0x32]	4176	1			T1	5		T2	17		T20	2
valid_sources[0x33]	4794	1			T2	10		T3	1		T12	104
valid_sources[0x34]	4717	1			T7	1		T6	3		T1	1
valid_sources[0x35]	4276	1			T4	7		T2	5		T12	141
valid_sources[0x36]	4113	1			T24	3		T1	5		T2	9
valid_sources[0x37]	4386	1			T30	1		T2	20		T12	140
valid_sources[0x38]	4561	1			T6	3		T1	9		T2	7
valid_sources[0x39]	4054	1			T1	4		T2	13		T3	4
valid_sources[0x3a]	4260	1			T2	9		T12	98		T13	2
valid_sources[0x3b]	4111	1			T2	10		T3	4		T12	129
valid_sources[0x3c]	4521	1			T1	2		T2	11		T12	130
valid_sources[0x3d]	4257	1			T26	5		T27	1		T1	3
valid_sources[0x3e]	3970	1			T7	1		T26	3		T2	1
valid_sources[0x3f]	4119	1			T30	1		T2	19		T12	136
valid_sources[0x40]	5880	1			T5	19		T7	2		T1	5
valid_sources[0x41]	4410	1			T2	10		T3	1		T12	109
valid_sources[0x42]	4335	1			T5	6		T1	12		T2	4
valid_sources[0x43]	4303	1			T5	8		T26	4		T1	2
valid_sources[0x44]	4273	1			T5	10		T27	2		T1	10
valid_sources[0x45]	4229	1			T1	4		T2	17		T12	119
valid_sources[0x46]	4725	1			T1	4		T2	2		T3	1
valid_sources[0x47]	4340	1			T5	2		T1	3		T2	22
valid_sources[0x48]	4123	1			T2	2		T12	119		T13	1
valid_sources[0x49]	4025	1			T5	6		T6	1		T1	5
valid_sources[0x4a]	4228	1			T1	1		T2	1		T12	132
valid_sources[0x4b]	4447	1			T2	16		T3	4		T20	1
valid_sources[0x4c]	4011	1			T1	1		T2	8		T3	2
valid_sources[0x4d]	4516	1			T30	1		T1	1		T2	1
valid_sources[0x4e]	4065	1			T30	1		T1	8		T2	5
valid_sources[0x4f]	5008	1			T30	4		T1	5		T2	18
valid_sources[0x50]	4729	1			T7	1		T6	3		T2	8
valid_sources[0x51]	4231	1			T5	8		T1	2		T2	15
valid_sources[0x52]	5911	1			T5	15		T1	10		T2	6
valid_sources[0x53]	4151	1			T6	5		T1	5		T2	5
valid_sources[0x54]	4864	1			T6	2		T1	5		T2	2
valid_sources[0x55]	4598	1			T1	3		T2	5		T12	151
valid_sources[0x56]	5185	1			T1	4		T2	13		T3	1
valid_sources[0x57]	4298	1			T2	6		T3	1		T12	125
valid_sources[0x58]	4462	1			T6	6		T1	7		T2	38
valid_sources[0x59]	4607	1			T2	9		T3	3		T12	137
valid_sources[0x5a]	4354	1			T5	33		T1	3		T2	11
valid_sources[0x5b]	4594	1			T1	1		T2	2		T12	109
valid_sources[0x5c]	6045	1			T5	12		T7	1		T1	4
valid_sources[0x5d]	4129	1			T4	5		T1	2		T2	15
valid_sources[0x5e]	4257	1			T5	35		T7	1		T1	7
valid_sources[0x5f]	4458	1			T4	69		T1	3		T2	13
valid_sources[0x60]	4330	1			T1	7		T2	9		T3	2
valid_sources[0x61]	4729	1			T1	12		T2	28		T3	3
valid_sources[0x62]	4456	1			T5	9		T7	1		T2	12
valid_sources[0x63]	4513	1			T7	1		T1	2		T2	21
valid_sources[0x64]	4246	1			T1	1		T2	8		T3	2
valid_sources[0x65]	4997	1			T1	3		T2	7		T12	120
valid_sources[0x66]	4559	1			T26	1		T6	1		T30	1
valid_sources[0x67]	4432	1			T1	4		T3	1		T12	122
valid_sources[0x68]	4224	1			T1	2		T2	9		T12	116
valid_sources[0x69]	4633	1			T4	62		T1	8		T2	4
valid_sources[0x6a]	4499	1			T1	8		T2	24		T12	120
valid_sources[0x6b]	4336	1			T27	3		T2	15		T3	2
valid_sources[0x6c]	4677	1			T1	1		T2	1		T3	1
valid_sources[0x6d]	4068	1			T1	1		T2	11		T12	127
valid_sources[0x6e]	4651	1			T5	3		T1	2		T2	16
valid_sources[0x6f]	4382	1			T30	1		T1	5		T2	4
valid_sources[0x70]	4147	1			T1	9		T3	2		T12	126
valid_sources[0x71]	4382	1			T5	10		T26	2		T6	2
valid_sources[0x72]	4355	1			T6	2		T1	4		T2	12
valid_sources[0x73]	4310	1			T1	10		T2	9		T3	1
valid_sources[0x74]	4342	1			T1	11		T2	10		T3	2
valid_sources[0x75]	5294	1			T1	1		T2	11		T3	2
valid_sources[0x76]	4703	1			T4	1		T1	4		T2	14
valid_sources[0x77]	5363	1			T5	5		T2	12		T3	5
valid_sources[0x78]	4080	1			T1	4		T2	2		T3	3
valid_sources[0x79]	4389	1			T6	2		T1	1		T2	5
valid_sources[0x7a]	3985	1			T5	5		T6	1		T2	13
valid_sources[0x7b]	4338	1			T2	11		T12	135		T15	410
valid_sources[0x7c]	4224	1			T2	9		T12	131		T15	411
valid_sources[0x7d]	4552	1			T4	3		T2	17		T12	122
valid_sources[0x7e]	4358	1			T28	13		T1	2		T2	3
valid_sources[0x7f]	4309	1			T6	1		T2	1		T3	2
valid_sources[0x80]	4223	1			T5	10		T1	9		T2	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

237599

1

T5

43

T7

5

T8

6

values[0x0]

all_enables

biggest_size

345591

1

T5

97

T7

7

T8

10

values[0x1]

all_enables

biggest_size

322850

1

T5

79

T7

2

T8

4