Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T4
0	1	Covered	T5,T30,T1
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T30
1	0	Covered	T25,T19,T41
1	1	Covered	T5,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	731772106	7083	0	0
GateOpen_A	731772106	13435	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731772106	7083	0	0
T1	0	16	0	0
T2	0	25	0	0
T4	74982	0	0	0
T5	325498	41	0	0
T6	98952	0	0	0
T7	15567	0	0	0
T8	18273	0	0	0
T12	0	169	0	0
T19	0	17	0	0
T23	0	18	0	0
T24	3243	0	0	0
T25	3956	16	0	0
T26	3812	0	0	0
T27	3300	0	0	0
T28	4825	0	0	0
T30	0	25	0	0
T90	0	37	0	0
T164	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	731772106	13435	0	0
T1	0	32	0	0
T4	74982	28	0	0
T5	325498	53	0	0
T6	98952	4	0	0
T7	15567	0	0	0
T8	18273	4	0	0
T24	3243	4	0	0
T25	3956	20	0	0
T26	3812	4	0	0
T27	3300	4	0	0
T28	4825	0	0	0
T30	0	25	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T4
0	1	Covered	T5,T30,T1
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T30
1	0	Covered	T25,T19,T41
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	80813793	1707	0	0
GateOpen_A	80813793	3295	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813793	1707	0	0
T1	0	4	0	0
T2	0	6	0	0
T4	4477	0	0	0
T5	35774	10	0	0
T6	10989	0	0	0
T7	1846	0	0	0
T8	2156	0	0	0
T12	0	42	0	0
T19	0	4	0	0
T23	0	5	0	0
T24	354	0	0	0
T25	433	4	0	0
T26	411	0	0	0
T27	347	0	0	0
T28	562	0	0	0
T30	0	4	0	0
T90	0	9	0	0
T164	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813793	3295	0	0
T1	0	8	0	0
T4	4477	7	0	0
T5	35774	13	0	0
T6	10989	1	0	0
T7	1846	0	0	0
T8	2156	1	0	0
T24	354	1	0	0
T25	433	5	0	0
T26	411	1	0	0
T27	347	1	0	0
T28	562	0	0	0
T30	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T4
0	1	Covered	T5,T30,T1
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T30
1	0	Covered	T25,T19,T41
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	161627806	1772	0	0
GateOpen_A	161627806	3360	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161627806	1772	0	0
T1	0	4	0	0
T2	0	6	0	0
T4	8954	0	0	0
T5	71548	9	0	0
T6	21977	0	0	0
T7	3693	0	0	0
T8	4312	0	0	0
T12	0	43	0	0
T19	0	4	0	0
T23	0	5	0	0
T24	708	0	0	0
T25	865	4	0	0
T26	821	0	0	0
T27	693	0	0	0
T28	1125	0	0	0
T30	0	6	0	0
T90	0	9	0	0
T164	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161627806	3360	0	0
T1	0	8	0	0
T4	8954	7	0	0
T5	71548	12	0	0
T6	21977	1	0	0
T7	3693	0	0	0
T8	4312	1	0	0
T24	708	1	0	0
T25	865	5	0	0
T26	821	1	0	0
T27	693	1	0	0
T28	1125	0	0	0
T30	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T4
0	1	Covered	T5,T30,T1
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T30
1	0	Covered	T25,T19,T41
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	324680670	1815	0	0
GateOpen_A	324680670	3403	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324680670	1815	0	0
T1	0	4	0	0
T2	0	7	0	0
T4	41033	0	0	0
T5	143528	11	0	0
T6	43990	0	0	0
T7	6685	0	0	0
T8	7870	0	0	0
T12	0	43	0	0
T19	0	4	0	0
T23	0	4	0	0
T24	1454	0	0	0
T25	1807	4	0	0
T26	1720	0	0	0
T27	1506	0	0	0
T28	2092	0	0	0
T30	0	7	0	0
T90	0	9	0	0
T164	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324680670	3403	0	0
T1	0	8	0	0
T4	41033	7	0	0
T5	143528	14	0	0
T6	43990	1	0	0
T7	6685	0	0	0
T8	7870	1	0	0
T24	1454	1	0	0
T25	1807	5	0	0
T26	1720	1	0	0
T27	1506	1	0	0
T28	2092	0	0	0
T30	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T25,T4
0	1	Covered	T5,T30,T1
1	0	Covered	T5,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T30
1	0	Covered	T25,T19,T41
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	164649837	1789	0	0
GateOpen_A	164649837	3377	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164649837	1789	0	0
T1	0	4	0	0
T2	0	6	0	0
T4	20518	0	0	0
T5	74648	11	0	0
T6	21996	0	0	0
T7	3343	0	0	0
T8	3935	0	0	0
T12	0	41	0	0
T19	0	5	0	0
T23	0	4	0	0
T24	727	0	0	0
T25	851	4	0	0
T26	860	0	0	0
T27	754	0	0	0
T28	1046	0	0	0
T30	0	8	0	0
T90	0	10	0	0
T164	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164649837	3377	0	0
T1	0	8	0	0
T4	20518	7	0	0
T5	74648	14	0	0
T6	21996	1	0	0
T7	3343	0	0	0
T8	3935	1	0	0
T24	727	1	0	0
T25	851	5	0	0
T26	860	1	0	0
T27	754	1	0	0
T28	1046	0	0	0
T30	0	8	0	0