Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	300278350	30970	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	300278350	30970	0	0
T1	876600	111	0	0
T2	786870	239	0	0
T3	941165	95	0	0
T9	409280	0	0	0
T12	554825	658	0	0
T13	0	123	0	0
T14	0	101	0	0
T15	0	1067	0	0
T16	0	59	0	0
T17	0	213	0	0
T18	0	93	0	0
T19	6010	0	0	0
T20	13990	0	0	0
T21	24565	0	0	0
T22	7480	0	0	0
T23	3745	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	60055670	4690	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	4690	0	0
T1	175320	16	0	0
T2	157374	43	0	0
T3	188233	12	0	0
T9	81856	0	0	0
T12	110965	120	0	0
T13	0	18	0	0
T14	0	12	0	0
T15	0	197	0	0
T16	0	9	0	0
T17	0	28	0	0
T18	0	15	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	0	0	0
T23	749	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	60055670	4645	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	4645	0	0
T1	175320	16	0	0
T2	157374	43	0	0
T3	188233	14	0	0
T9	81856	0	0	0
T12	110965	120	0	0
T13	0	17	0	0
T14	0	13	0	0
T15	0	197	0	0
T16	0	9	0	0
T17	0	28	0	0
T18	0	15	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	0	0	0
T23	749	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	60055670	6190	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	6190	0	0
T1	175320	22	0	0
T2	157374	47	0	0
T3	188233	19	0	0
T9	81856	0	0	0
T12	110965	128	0	0
T13	0	25	0	0
T14	0	21	0	0
T15	0	204	0	0
T16	0	12	0	0
T17	0	43	0	0
T18	0	19	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	0	0	0
T23	749	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	60055670	6209	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	6209	0	0
T1	175320	22	0	0
T2	157374	47	0	0
T3	188233	19	0	0
T9	81856	0	0	0
T12	110965	128	0	0
T13	0	24	0	0
T14	0	21	0	0
T15	0	208	0	0
T16	0	12	0	0
T17	0	42	0	0
T18	0	19	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	0	0	0
T23	749	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	60055670	9236	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	9236	0	0
T1	175320	35	0	0
T2	157374	59	0	0
T3	188233	31	0	0
T9	81856	0	0	0
T12	110965	162	0	0
T13	0	39	0	0
T14	0	34	0	0
T15	0	261	0	0
T16	0	17	0	0
T17	0	72	0	0
T18	0	25	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	0	0	0
T23	749	0	0	0