Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Unreachable
1	0	Covered	T5,T4,T1

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	60055670	57835154	0	0
AllClkBypReqTrue_A	60055670	65047	0	0
IoClkBypReqFalse_A	60055670	57790129	0	2307
IoClkBypReqTrue_A	60055670	105866	0	0
LcClkBypAckFalse_A	60055670	57840125	0	0
LcClkBypAckTrue_A	60055670	60076	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	57835154	0	0
T4	42743	2616	0	0
T5	87962	87539	0	0
T6	10997	10969	0	0
T7	1670	1566	0	0
T8	1722	1425	0	0
T24	1500	1345	0	0
T25	1055	951	0	0
T26	1739	1546	0	0
T27	1568	1327	0	0
T28	1068	940	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	65047	0	0
T1	0	44	0	0
T2	0	229	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T7	1670	87	0	0
T8	1722	240	0	0
T12	0	1704	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	80	0	0
T30	1175	0	0	0
T35	0	4	0	0
T76	0	43	0	0
T77	0	264	0	0
T79	0	334	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	57790129	0	2307
T4	42743	2602	0	3
T5	87962	87529	0	3
T6	10997	10967	0	3
T7	1670	1377	0	3
T8	1722	1440	0	3
T24	1500	1343	0	3
T25	1055	949	0	3
T26	1739	1544	0	3
T27	1568	1325	0	3
T28	1068	916	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	105866	0	0
T1	0	53	0	0
T2	0	303	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T7	1670	274	0	0
T8	1722	223	0	0
T12	0	2631	0	0
T22	0	175	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	102	0	0
T30	1175	0	0	0
T35	0	24	0	0
T76	0	50	0	0
T77	0	291	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	57840125	0	0
T4	42743	2616	0	0
T5	87962	87539	0	0
T6	10997	10969	0	0
T7	1670	1495	0	0
T8	1722	1517	0	0
T24	1500	1345	0	0
T25	1055	951	0	0
T26	1739	1546	0	0
T27	1568	1327	0	0
T28	1068	923	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	60076	0	0
T1	0	50	0	0
T2	0	182	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T7	1670	158	0	0
T8	1722	148	0	0
T12	0	1535	0	0
T22	0	92	0	0
T24	1500	0	0	0
T25	1055	0	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	97	0	0
T30	1175	0	0	0
T35	0	19	0	0
T76	0	46	0	0
T77	0	174	0	0