Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1371848276	7240	0	0
TransStop_A	1371848276	3845	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1371848276	7240	0	0
T1	0	28	0	0
T2	0	103	0	0
T4	170976	0	0	0
T5	718052	10	0	0
T6	183296	0	0	0
T7	27852	0	0	0
T8	32792	0	0	0
T12	0	159	0	0
T20	0	25	0	0
T24	6056	0	0	0
T25	7480	0	0	0
T26	7168	7	0	0
T27	6276	3	0	0
T28	8720	0	0	0
T78	0	9	0	0
T88	0	23	0	0
T111	0	33	0	0
T112	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1371848276	3845	0	0
T1	0	22	0	0
T2	0	55	0	0
T4	170976	0	0	0
T5	718052	6	0	0
T6	183296	0	0	0
T7	27852	0	0	0
T8	32792	0	0	0
T12	0	81	0	0
T20	0	13	0	0
T24	6056	0	0	0
T25	7480	0	0	0
T26	7168	5	0	0
T27	6276	3	0	0
T28	8720	0	0	0
T78	0	9	0	0
T88	0	12	0	0
T111	0	19	0	0
T112	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	342962069	1780	0	0
TransStop_A	342962069	951	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342962069	1780	0	0
T1	0	7	0	0
T2	0	26	0	0
T4	42744	0	0	0
T5	179513	2	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8198	0	0	0
T12	0	39	0	0
T20	0	6	0	0
T24	1514	0	0	0
T25	1870	0	0	0
T26	1792	1	0	0
T27	1569	0	0	0
T28	2180	0	0	0
T78	0	2	0	0
T88	0	4	0	0
T111	0	8	0	0
T112	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342962069	951	0	0
T1	0	5	0	0
T2	0	15	0	0
T4	42744	0	0	0
T5	179513	1	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8198	0	0	0
T12	0	20	0	0
T20	0	3	0	0
T24	1514	0	0	0
T25	1870	0	0	0
T26	1792	1	0	0
T27	1569	0	0	0
T28	2180	0	0	0
T78	0	2	0	0
T88	0	3	0	0
T111	0	6	0	0
T112	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	342962069	1827	0	0
TransStop_A	342962069	964	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342962069	1827	0	0
T1	0	7	0	0
T2	0	23	0	0
T4	42744	0	0	0
T5	179513	3	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8198	0	0	0
T12	0	38	0	0
T20	0	5	0	0
T24	1514	0	0	0
T25	1870	0	0	0
T26	1792	3	0	0
T27	1569	1	0	0
T28	2180	0	0	0
T78	0	2	0	0
T88	0	5	0	0
T111	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342962069	964	0	0
T1	0	6	0	0
T2	0	10	0	0
T4	42744	0	0	0
T5	179513	2	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8198	0	0	0
T12	0	18	0	0
T20	0	4	0	0
T24	1514	0	0	0
T25	1870	0	0	0
T26	1792	2	0	0
T27	1569	1	0	0
T28	2180	0	0	0
T78	0	2	0	0
T88	0	3	0	0
T111	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	342962069	1789	0	0
TransStop_A	342962069	935	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342962069	1789	0	0
T1	0	6	0	0
T2	0	26	0	0
T4	42744	0	0	0
T5	179513	3	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8198	0	0	0
T12	0	40	0	0
T20	0	8	0	0
T24	1514	0	0	0
T25	1870	0	0	0
T26	1792	2	0	0
T27	1569	1	0	0
T28	2180	0	0	0
T78	0	3	0	0
T88	0	6	0	0
T111	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342962069	935	0	0
T1	0	5	0	0
T2	0	14	0	0
T4	42744	0	0	0
T5	179513	2	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8198	0	0	0
T12	0	22	0	0
T20	0	3	0	0
T24	1514	0	0	0
T25	1870	0	0	0
T26	1792	1	0	0
T27	1569	1	0	0
T28	2180	0	0	0
T78	0	3	0	0
T88	0	2	0	0
T111	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	342962069	1844	0	0
TransStop_A	342962069	995	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342962069	1844	0	0
T1	0	8	0	0
T2	0	28	0	0
T4	42744	0	0	0
T5	179513	2	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8198	0	0	0
T12	0	42	0	0
T20	0	6	0	0
T24	1514	0	0	0
T25	1870	0	0	0
T26	1792	1	0	0
T27	1569	1	0	0
T28	2180	0	0	0
T78	0	2	0	0
T88	0	8	0	0
T111	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342962069	995	0	0
T1	0	6	0	0
T2	0	16	0	0
T4	42744	0	0	0
T5	179513	1	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8198	0	0	0
T12	0	21	0	0
T20	0	3	0	0
T24	1514	0	0	0
T25	1870	0	0	0
T26	1792	1	0	0
T27	1569	1	0	0
T28	2180	0	0	0
T78	0	2	0	0
T88	0	4	0	0
T111	0	3	0	0