Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_en_sync	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_lc_byp_req

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1538	1538	0	0
OutputsKnown_A	120111340	115804608	0	0
gen_flops.OutputDelay_A	120111340	115791624	0	4614

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1538	1538	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T24	2	2	0	0
T25	2	2	0	0
T26	2	2	0	0
T27	2	2	0	0
T28	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120111340	115804608	0	0
T4	85486	5246	0	0
T5	175924	175088	0	0
T6	21994	21940	0	0
T7	3340	3308	0	0
T8	3444	3332	0	0
T24	3000	2692	0	0
T25	2110	1904	0	0
T26	3478	3094	0	0
T27	3136	2656	0	0
T28	2136	2042	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120111340	115791624	0	4614
T4	85486	5192	0	6
T5	175924	175058	0	6
T6	21994	21934	0	6
T7	3340	3302	0	6
T8	3444	3326	0	6
T24	3000	2686	0	6
T25	2110	1898	0	6
T26	3478	3088	0	6
T27	3136	2650	0	6
T28	2136	2036	0	6

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	769	769	0	0
OutputsKnown_A	60055670	57902304	0	0
gen_flops.OutputDelay_A	60055670	57895812	0	2307

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769	769	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	57902304	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	57895812	0	2307
T4	42743	2596	0	3
T5	87962	87529	0	3
T6	10997	10967	0	3
T7	1670	1651	0	3
T8	1722	1663	0	3
T24	1500	1343	0	3
T25	1055	949	0	3
T26	1739	1544	0	3
T27	1568	1325	0	3
T28	1068	1018	0	3

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	769	769	0	0
OutputsKnown_A	60055670	57902304	0	0
gen_flops.OutputDelay_A	60055670	57895812	0	2307

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	769	769	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	57902304	0	0
T4	42743	2623	0	0
T5	87962	87544	0	0
T6	10997	10970	0	0
T7	1670	1654	0	0
T8	1722	1666	0	0
T24	1500	1346	0	0
T25	1055	952	0	0
T26	1739	1547	0	0
T27	1568	1328	0	0
T28	1068	1021	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	57895812	0	2307
T4	42743	2596	0	3
T5	87962	87529	0	3
T6	10997	10967	0	3
T7	1670	1651	0	3
T8	1722	1663	0	3
T24	1500	1343	0	3
T25	1055	949	0	3
T26	1739	1544	0	3
T27	1568	1325	0	3
T28	1068	1018	0	3