Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	60995957	1249767	0	0
clk_enables_rd_A	60995957	20184	0	0
clk_hints_rd_A	60995957	19122	0	0
extclk_ctrl_rd_A	60995957	21004	0	0
extclk_ctrl_regwen_rd_A	60995957	16196	0	0
jitter_enable_rd_A	60995957	25732	0	0
jitter_regwen_rd_A	60995957	18289	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	1249767	0	0
T9	81856	0	0	0
T12	110965	38359	0	0
T13	76010	0	0	0
T15	0	152849	0	0
T23	749	0	0	0
T36	1155	0	0	0
T37	1684	0	0	0
T42	0	121530	0	0
T69	0	77998	0	0
T70	0	67443	0	0
T71	0	109459	0	0
T72	0	70357	0	0
T73	0	159055	0	0
T74	0	80690	0	0
T75	0	123297	0	0
T76	743	0	0	0
T77	1791	0	0	0
T78	1784	0	0	0
T79	2576	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	20184	0	0
T1	175320	11	0	0
T2	157374	0	0	0
T3	188233	0	0	0
T9	81856	0	0	0
T12	110965	0	0	0
T14	0	6	0	0
T15	0	5724	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	0	0	0
T23	749	0	0	0
T38	0	5	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	12	0	0
T135	0	2	0	0
T136	0	6	0	0
T137	0	1	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	19122	0	0
T1	175320	9	0	0
T2	157374	0	0	0
T3	188233	0	0	0
T9	81856	0	0	0
T12	110965	0	0	0
T14	0	6	0	0
T15	0	5285	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	0	0	0
T23	749	0	0	0
T38	0	8	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	10	0	0
T135	0	1	0	0
T136	0	3	0	0
T138	0	9	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	21004	0	0
T1	175320	15	0	0
T2	157374	0	0	0
T3	188233	0	0	0
T9	81856	0	0	0
T12	110965	0	0	0
T15	0	5982	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	20	0	0
T23	749	0	0	0
T76	0	5	0	0
T77	0	38	0	0
T80	0	54	0	0
T139	0	123	0	0
T140	0	15	0	0
T141	0	46	0	0
T142	0	42	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	16196	0	0
T15	519469	4659	0	0
T16	49391	0	0	0
T17	125828	0	0	0
T29	7702	0	0	0
T69	0	1403	0	0
T81	50217	0	0	0
T82	18346	0	0	0
T139	40369	47	0	0
T143	0	11	0	0
T144	0	45	0	0
T145	0	36	0	0
T146	0	6	0	0
T147	0	23	0	0
T148	0	72	0	0
T149	0	33	0	0
T150	1622	0	0	0
T151	963	0	0	0
T152	3495	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	25732	0	0
T1	175320	313	0	0
T2	157374	0	0	0
T3	188233	0	0	0
T9	81856	0	0	0
T12	110965	0	0	0
T14	0	149	0	0
T15	0	6255	0	0
T19	1202	0	0	0
T20	2798	0	0	0
T21	4913	0	0	0
T22	1496	0	0	0
T23	749	0	0	0
T38	0	221	0	0
T132	0	140	0	0
T133	0	45	0	0
T134	0	296	0	0
T138	0	87	0	0
T153	0	73	0	0
T154	0	131	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60995957	18289	0	0
T15	519469	5805	0	0
T16	49391	0	0	0
T17	125828	0	0	0
T29	7702	0	0	0
T56	0	97	0	0
T57	0	225	0	0
T59	0	112	0	0
T67	0	102	0	0
T69	0	1694	0	0
T75	0	4868	0	0
T81	50217	0	0	0
T82	18346	0	0	0
T83	0	17	0	0
T139	40369	0	0	0
T150	1622	0	0	0
T151	963	0	0	0
T152	3495	0	0	0
T155	0	2633	0	0
T156	0	21	0	0