Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	180167010	445	0	0
StatusRise_A	180167010	445	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180167010	445	0	0
T1	525960	0	0	0
T2	472122	0	0	0
T4	128229	0	0	0
T6	32991	0	0	0
T19	0	12	0	0
T25	3165	11	0	0
T26	5217	0	0	0
T27	4704	0	0	0
T28	3204	0	0	0
T30	3525	0	0	0
T35	3369	0	0	0
T41	0	12	0	0
T157	0	7	0	0
T158	0	6	0	0
T159	0	13	0	0
T160	0	14	0	0
T161	0	15	0	0
T162	0	8	0	0
T163	0	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180167010	445	0	0
T1	525960	0	0	0
T2	472122	0	0	0
T4	128229	0	0	0
T6	32991	0	0	0
T19	0	12	0	0
T25	3165	11	0	0
T26	5217	0	0	0
T27	4704	0	0	0
T28	3204	0	0	0
T30	3525	0	0	0
T35	3369	0	0	0
T41	0	12	0	0
T157	0	7	0	0
T158	0	6	0	0
T159	0	13	0	0
T160	0	14	0	0
T161	0	15	0	0
T162	0	8	0	0
T163	0	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	60055670	143	0	0
StatusRise_A	60055670	143	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	143	0	0
T1	175320	0	0	0
T2	157374	0	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T19	0	3	0	0
T25	1055	3	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0
T30	1175	0	0	0
T35	1123	0	0	0
T41	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	5	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	3	0	0
T163	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	143	0	0
T1	175320	0	0	0
T2	157374	0	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T19	0	3	0	0
T25	1055	3	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0
T30	1175	0	0	0
T35	1123	0	0	0
T41	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	5	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	3	0	0
T163	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	60055670	155	0	0
StatusRise_A	60055670	155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	155	0	0
T1	175320	0	0	0
T2	157374	0	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T19	0	4	0	0
T25	1055	4	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0
T30	1175	0	0	0
T35	1123	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	155	0	0
T1	175320	0	0	0
T2	157374	0	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T19	0	4	0	0
T25	1055	4	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0
T30	1175	0	0	0
T35	1123	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	60055670	147	0	0
StatusRise_A	60055670	147	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	147	0	0
T1	175320	0	0	0
T2	157374	0	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T19	0	5	0	0
T25	1055	4	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0
T30	1175	0	0	0
T35	1123	0	0	0
T41	0	5	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60055670	147	0	0
T1	175320	0	0	0
T2	157374	0	0	0
T4	42743	0	0	0
T6	10997	0	0	0
T19	0	5	0	0
T25	1055	4	0	0
T26	1739	0	0	0
T27	1568	0	0	0
T28	1068	0	0	0
T30	1175	0	0	0
T35	1123	0	0	0
T41	0	5	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	4	0	0