Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	27905	0	0
CgEnOn_A	2147483647	19493	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	27905	0	0
T1	1560708	7	0	0
T2	2403150	26	0	0
T4	415366	21	0	0
T5	1043547	63	0	0
T6	494820	3	0	0
T7	43416	3	0	0
T8	51061	3	0	0
T19	0	23	0	0
T24	9296	3	0	0
T25	19990	38	0	0
T26	19192	4	0	0
T27	16692	3	0	0
T28	23848	3	0	0
T30	9448	0	0	0
T35	24141	0	0	0
T41	0	15	0	0
T157	0	10	0	0
T158	0	5	0	0
T159	0	20	0	0
T160	0	25	0	0
T161	0	30	0	0
T162	0	10	0	0
T163	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19493	0	0
T1	1560708	19	0	0
T2	2403150	60	0	0
T4	415366	0	0	0
T5	1043547	48	0	0
T6	494820	0	0	0
T7	43416	0	0	0
T8	51061	0	0	0
T12	0	215	0	0
T19	0	35	0	0
T20	0	6	0	0
T23	0	14	0	0
T24	9296	0	0	0
T25	19990	35	0	0
T26	19192	1	0	0
T27	16692	0	0	0
T28	23848	0	0	0
T30	9448	29	0	0
T35	24141	0	0	0
T41	0	15	0	0
T78	0	2	0	0
T90	0	42	0	0
T157	0	10	0	0
T158	0	5	0	0
T159	0	20	0	0
T160	0	25	0	0
T161	0	30	0	0
T162	0	10	0	0
T163	0	20	0	0
T164	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	161627409	155	0	0
CgEnOn_A	161627409	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161627409	155	0	0
T1	154042	0	0	0
T2	578108	0	0	0
T4	8953	0	0	0
T6	21976	0	0	0
T19	0	4	0	0
T25	864	4	0	0
T26	821	0	0	0
T27	692	0	0	0
T28	1124	0	0	0
T30	943	0	0	0
T35	3708	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161627409	155	0	0
T1	154042	0	0	0
T2	578108	0	0	0
T4	8953	0	0	0
T6	21976	0	0	0
T19	0	4	0	0
T25	864	4	0	0
T26	821	0	0	0
T27	692	0	0	0
T28	1124	0	0	0
T30	943	0	0	0
T35	3708	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80813395	155	0	0
CgEnOn_A	80813395	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813395	155	0	0
T1	77022	0	0	0
T2	289056	0	0	0
T4	4476	0	0	0
T6	10988	0	0	0
T19	0	4	0	0
T25	432	4	0	0
T26	410	0	0	0
T27	346	0	0	0
T28	561	0	0	0
T30	471	0	0	0
T35	1854	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813395	155	0	0
T1	77022	0	0	0
T2	289056	0	0	0
T4	4476	0	0	0
T6	10988	0	0	0
T19	0	4	0	0
T25	432	4	0	0
T26	410	0	0	0
T27	346	0	0	0
T28	561	0	0	0
T30	471	0	0	0
T35	1854	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80813395	155	0	0
CgEnOn_A	80813395	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813395	155	0	0
T1	77022	0	0	0
T2	289056	0	0	0
T4	4476	0	0	0
T6	10988	0	0	0
T19	0	4	0	0
T25	432	4	0	0
T26	410	0	0	0
T27	346	0	0	0
T28	561	0	0	0
T30	471	0	0	0
T35	1854	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813395	155	0	0
T1	77022	0	0	0
T2	289056	0	0	0
T4	4476	0	0	0
T6	10988	0	0	0
T19	0	4	0	0
T25	432	4	0	0
T26	410	0	0	0
T27	346	0	0	0
T28	561	0	0	0
T30	471	0	0	0
T35	1854	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80813395	155	0	0
CgEnOn_A	80813395	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813395	155	0	0
T1	77022	0	0	0
T2	289056	0	0	0
T4	4476	0	0	0
T6	10988	0	0	0
T19	0	4	0	0
T25	432	4	0	0
T26	410	0	0	0
T27	346	0	0	0
T28	561	0	0	0
T30	471	0	0	0
T35	1854	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813395	155	0	0
T1	77022	0	0	0
T2	289056	0	0	0
T4	4476	0	0	0
T6	10988	0	0	0
T19	0	4	0	0
T25	432	4	0	0
T26	410	0	0	0
T27	346	0	0	0
T28	561	0	0	0
T30	471	0	0	0
T35	1854	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	324680234	155	0	0
CgEnOn_A	324680234	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324680234	155	0	0
T1	308910	0	0	0
T2	115526	0	0	0
T4	41032	0	0	0
T6	43990	0	0	0
T19	0	4	0	0
T25	1807	4	0	0
T26	1720	0	0	0
T27	1505	0	0	0
T28	2092	0	0	0
T30	1979	0	0	0
T35	4150	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324680234	155	0	0
T1	308910	0	0	0
T2	115526	0	0	0
T4	41032	0	0	0
T6	43990	0	0	0
T19	0	4	0	0
T25	1807	4	0	0
T26	1720	0	0	0
T27	1505	0	0	0
T28	2092	0	0	0
T30	1979	0	0	0
T35	4150	0	0	0
T41	0	3	0	0
T157	0	2	0	0
T158	0	1	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	6	0	0
T162	0	2	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	342961644	143	0	0
CgEnOn_A	342961644	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	143	0	0
T1	351793	0	0	0
T2	125144	0	0	0
T4	42743	0	0	0
T6	45824	0	0	0
T19	0	3	0	0
T25	1870	3	0	0
T26	1792	0	0	0
T27	1568	0	0	0
T28	2180	0	0	0
T30	2062	0	0	0
T35	4323	0	0	0
T41	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	5	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	3	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	143	0	0
T1	351793	0	0	0
T2	125144	0	0	0
T4	42743	0	0	0
T6	45824	0	0	0
T19	0	3	0	0
T25	1870	3	0	0
T26	1792	0	0	0
T27	1568	0	0	0
T28	2180	0	0	0
T30	2062	0	0	0
T35	4323	0	0	0
T41	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	5	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	3	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	342961644	143	0	0
CgEnOn_A	342961644	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	143	0	0
T1	351793	0	0	0
T2	125144	0	0	0
T4	42743	0	0	0
T6	45824	0	0	0
T19	0	3	0	0
T25	1870	3	0	0
T26	1792	0	0	0
T27	1568	0	0	0
T28	2180	0	0	0
T30	2062	0	0	0
T35	4323	0	0	0
T41	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	5	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	3	0	0
T163	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	143	0	0
T1	351793	0	0	0
T2	125144	0	0	0
T4	42743	0	0	0
T6	45824	0	0	0
T19	0	3	0	0
T25	1870	3	0	0
T26	1792	0	0	0
T27	1568	0	0	0
T28	2180	0	0	0
T30	2062	0	0	0
T35	4323	0	0	0
T41	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	5	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	3	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Unreachable
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	164649457	147	0	0
CgEnOn_A	164649457	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164649457	147	0	0
T1	163104	0	0	0
T2	592060	0	0	0
T4	20517	0	0	0
T6	21996	0	0	0
T19	0	5	0	0
T25	850	4	0	0
T26	859	0	0	0
T27	753	0	0	0
T28	1046	0	0	0
T30	989	0	0	0
T35	2075	0	0	0
T41	0	5	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164649457	147	0	0
T1	163104	0	0	0
T2	592060	0	0	0
T4	20517	0	0	0
T6	21996	0	0	0
T19	0	5	0	0
T25	850	4	0	0
T26	859	0	0	0
T27	753	0	0	0
T28	1046	0	0	0
T30	989	0	0	0
T35	2075	0	0	0
T41	0	5	0	0
T157	0	3	0	0
T158	0	3	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T19,T41
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80813395	4694	0	0
CgEnOn_A	80813395	2591	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813395	4694	0	0
T4	4476	7	0	0
T5	35773	21	0	0
T6	10988	1	0	0
T7	1846	1	0	0
T8	2156	1	0	0
T24	354	1	0	0
T25	432	5	0	0
T26	410	1	0	0
T27	346	1	0	0
T28	561	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80813395	2591	0	0
T1	0	4	0	0
T2	0	11	0	0
T4	4476	0	0	0
T5	35773	16	0	0
T6	10988	0	0	0
T7	1846	0	0	0
T8	2156	0	0	0
T12	0	56	0	0
T19	0	4	0	0
T23	0	5	0	0
T24	354	0	0	0
T25	432	4	0	0
T26	410	0	0	0
T27	346	0	0	0
T28	561	0	0	0
T30	0	9	0	0
T90	0	13	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T19,T41
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	161627409	4718	0	0
CgEnOn_A	161627409	2615	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161627409	4718	0	0
T4	8953	7	0	0
T5	71547	19	0	0
T6	21976	1	0	0
T7	3692	1	0	0
T8	4312	1	0	0
T24	707	1	0	0
T25	864	5	0	0
T26	821	1	0	0
T27	692	1	0	0
T28	1124	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161627409	2615	0	0
T1	0	4	0	0
T2	0	11	0	0
T4	8953	0	0	0
T5	71547	14	0	0
T6	21976	0	0	0
T7	3692	0	0	0
T8	4312	0	0	0
T12	0	61	0	0
T19	0	4	0	0
T23	0	5	0	0
T24	707	0	0	0
T25	864	4	0	0
T26	821	0	0	0
T27	692	0	0	0
T28	1124	0	0	0
T30	0	10	0	0
T90	0	14	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T19,T41
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	324680234	4756	0	0
CgEnOn_A	324680234	2653	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324680234	4756	0	0
T4	41032	7	0	0
T5	143527	21	0	0
T6	43990	1	0	0
T7	6684	1	0	0
T8	7870	1	0	0
T24	1453	1	0	0
T25	1807	5	0	0
T26	1720	1	0	0
T27	1505	1	0	0
T28	2092	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	324680234	2653	0	0
T1	0	4	0	0
T2	0	12	0	0
T4	41032	0	0	0
T5	143527	16	0	0
T6	43990	0	0	0
T7	6684	0	0	0
T8	7870	0	0	0
T12	0	59	0	0
T19	0	4	0	0
T23	0	4	0	0
T24	1453	0	0	0
T25	1807	4	0	0
T26	1720	0	0	0
T27	1505	0	0	0
T28	2092	0	0	0
T30	0	10	0	0
T90	0	15	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T25,T19,T41
1	0	Covered	T5,T7,T8
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	164649457	4717	0	0
CgEnOn_A	164649457	2614	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164649457	4717	0	0
T4	20517	7	0	0
T5	74648	23	0	0
T6	21996	1	0	0
T7	3342	1	0	0
T8	3935	1	0	0
T24	726	1	0	0
T25	850	5	0	0
T26	859	1	0	0
T27	753	1	0	0
T28	1046	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164649457	2614	0	0
T1	0	4	0	0
T2	0	11	0	0
T4	20517	0	0	0
T5	74648	18	0	0
T6	21996	0	0	0
T7	3342	0	0	0
T8	3935	0	0	0
T12	0	58	0	0
T19	0	5	0	0
T23	0	5	0	0
T24	726	0	0	0
T25	850	4	0	0
T26	859	0	0	0
T27	753	0	0	0
T28	1046	0	0	0
T30	0	11	0	0
T90	0	15	0	0
T164	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Covered	T5,T26,T1
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	342961644	1923	0	0
CgEnOn_A	342961644	1923	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	1923	0	0
T1	0	7	0	0
T2	0	26	0	0
T4	42743	0	0	0
T5	179513	2	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8197	0	0	0
T12	0	39	0	0
T19	0	3	0	0
T20	0	6	0	0
T24	1514	0	0	0
T25	1870	3	0	0
T26	1792	1	0	0
T27	1568	0	0	0
T28	2180	0	0	0
T78	0	2	0	0
T88	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	1923	0	0
T1	0	7	0	0
T2	0	26	0	0
T4	42743	0	0	0
T5	179513	2	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8197	0	0	0
T12	0	39	0	0
T19	0	3	0	0
T20	0	6	0	0
T24	1514	0	0	0
T25	1870	3	0	0
T26	1792	1	0	0
T27	1568	0	0	0
T28	2180	0	0	0
T78	0	2	0	0
T88	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Covered	T5,T26,T27
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	342961644	1970	0	0
CgEnOn_A	342961644	1970	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	1970	0	0
T1	0	7	0	0
T2	0	23	0	0
T4	42743	0	0	0
T5	179513	3	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8197	0	0	0
T12	0	38	0	0
T19	0	3	0	0
T20	0	5	0	0
T24	1514	0	0	0
T25	1870	3	0	0
T26	1792	3	0	0
T27	1568	1	0	0
T28	2180	0	0	0
T78	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	1970	0	0
T1	0	7	0	0
T2	0	23	0	0
T4	42743	0	0	0
T5	179513	3	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8197	0	0	0
T12	0	38	0	0
T19	0	3	0	0
T20	0	5	0	0
T24	1514	0	0	0
T25	1870	3	0	0
T26	1792	3	0	0
T27	1568	1	0	0
T28	2180	0	0	0
T78	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Covered	T5,T26,T27
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	342961644	1932	0	0
CgEnOn_A	342961644	1932	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	1932	0	0
T1	0	6	0	0
T2	0	26	0	0
T4	42743	0	0	0
T5	179513	3	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8197	0	0	0
T12	0	40	0	0
T19	0	3	0	0
T20	0	8	0	0
T24	1514	0	0	0
T25	1870	3	0	0
T26	1792	2	0	0
T27	1568	1	0	0
T28	2180	0	0	0
T78	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	1932	0	0
T1	0	6	0	0
T2	0	26	0	0
T4	42743	0	0	0
T5	179513	3	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8197	0	0	0
T12	0	40	0	0
T19	0	3	0	0
T20	0	8	0	0
T24	1514	0	0	0
T25	1870	3	0	0
T26	1792	2	0	0
T27	1568	1	0	0
T28	2180	0	0	0
T78	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T4
1	0	Covered	T5,T26,T27
1	1	Covered	T5,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	342961644	1987	0	0
CgEnOn_A	342961644	1987	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	1987	0	0
T1	0	8	0	0
T2	0	28	0	0
T4	42743	0	0	0
T5	179513	2	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8197	0	0	0
T12	0	42	0	0
T19	0	3	0	0
T20	0	6	0	0
T24	1514	0	0	0
T25	1870	3	0	0
T26	1792	1	0	0
T27	1568	1	0	0
T28	2180	0	0	0
T78	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342961644	1987	0	0
T1	0	8	0	0
T2	0	28	0	0
T4	42743	0	0	0
T5	179513	2	0	0
T6	45824	0	0	0
T7	6963	0	0	0
T8	8197	0	0	0
T12	0	42	0	0
T19	0	3	0	0
T20	0	6	0	0
T24	1514	0	0	0
T25	1870	3	0	0
T26	1792	1	0	0
T27	1568	1	0	0
T28	2180	0	0	0
T78	0	2	0	0