Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 129401468 1 T5 363172 T6 2396 T7 3864
auto[1] 238342 1 T6 198 T2 1722 T21 96


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 129368210 1 T5 363172 T6 2458 T7 3864
auto[1] 271600 1 T6 136 T4 1674 T2 1164


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 129287008 1 T5 363172 T6 2464 T7 3864
auto[1] 352802 1 T6 130 T2 1620 T21 272


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 121971082 1 T5 363172 T6 2276 T7 3864
auto[1] 7668728 1 T6 318 T2 1648 T21 2998


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 80878162 1 T5 363152 T6 2440 T7 3108
auto[1] 48761648 1 T5 20 T6 154 T7 756


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 74690420 1 T5 363152 T6 2044 T7 3108
auto[0] auto[0] auto[0] auto[0] auto[1] 47012450 1 T5 20 T6 86 T7 756
auto[0] auto[0] auto[0] auto[1] auto[0] 18032 1 T2 406 T22 90 T27 162
auto[0] auto[0] auto[0] auto[1] auto[1] 4798 1 T6 14 T29 56 T86 6
auto[0] auto[0] auto[1] auto[0] auto[0] 5783362 1 T6 228 T2 912 T21 2582
auto[0] auto[0] auto[1] auto[0] auto[1] 1682572 1 T21 212 T27 1034 T29 1538
auto[0] auto[0] auto[1] auto[1] auto[0] 26676 1 T6 22 T2 218 T27 116
auto[0] auto[0] auto[1] auto[1] auto[1] 6970 1 T21 16 T29 22 T83 28
auto[0] auto[1] auto[0] auto[0] auto[0] 28778 1 T6 8 T4 1674 T2 38
auto[0] auto[1] auto[0] auto[0] auto[1] 780 1 T13 8 T57 12 T26 44
auto[0] auto[1] auto[0] auto[1] auto[0] 7062 1 T6 62 T2 68 T3 66
auto[0] auto[1] auto[0] auto[1] auto[1] 1340 1 T92 66 T32 50 T192 76
auto[0] auto[1] auto[1] auto[0] auto[0] 6122 1 T2 44 T27 30 T29 46
auto[0] auto[1] auto[1] auto[0] auto[1] 1690 1 T27 40 T3 32 T188 6
auto[0] auto[1] auto[1] auto[1] auto[0] 12872 1 T2 98 T27 114 T29 46
auto[0] auto[1] auto[1] auto[1] auto[1] 3084 1 T3 58 T188 56 T13 64
auto[1] auto[0] auto[0] auto[0] auto[0] 59160 1 T2 192 T22 54 T27 30
auto[1] auto[0] auto[0] auto[0] auto[1] 2130 1 T6 2 T21 40 T193 18
auto[1] auto[0] auto[0] auto[1] auto[0] 19068 1 T2 428 T29 60 T83 134
auto[1] auto[0] auto[0] auto[1] auto[1] 4322 1 T6 52 T106 62 T13 62
auto[1] auto[0] auto[1] auto[0] auto[0] 16522 1 T6 10 T2 10 T21 20
auto[1] auto[0] auto[1] auto[0] auto[1] 4222 1 T21 10 T29 2 T83 2
auto[1] auto[0] auto[1] auto[1] auto[0] 29654 1 T2 74 T27 60 T29 114
auto[1] auto[0] auto[1] auto[1] auto[1] 7852 1 T21 80 T29 44 T83 44
auto[1] auto[1] auto[0] auto[0] auto[0] 79810 1 T6 8 T2 322 T21 44
auto[1] auto[1] auto[0] auto[0] auto[1] 3906 1 T2 46 T83 18 T3 46
auto[1] auto[1] auto[0] auto[1] auto[0] 30214 1 T2 256 T27 162 T29 106
auto[1] auto[1] auto[0] auto[1] auto[1] 8812 1 T83 56 T86 78 T90 68
auto[1] auto[1] auto[1] auto[0] auto[0] 23794 1 T6 10 T2 118 T21 58
auto[1] auto[1] auto[1] auto[0] auto[1] 5750 1 T21 20 T29 2 T83 24
auto[1] auto[1] auto[1] auto[1] auto[0] 46616 1 T6 48 T2 174 T27 198
auto[1] auto[1] auto[1] auto[1] auto[1] 10970 1 T29 44 T83 104 T3 56

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