---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	95984505	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	7883362	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	47991829	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	7883362	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	193519678	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	7883362	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	207185345	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	7883362	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	97171660	0	0	978
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	48585436	0	0	978
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	195988429	0	0	978
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	209757057	0	0	978
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	100761961	0	0	978
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	99527570	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	7883362	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	66299498	64073974	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	66299498	64073974	0	0
tb.dut.CgEnKnownO_A	0	0	66299498	64073974	0	0
tb.dut.ClocksKownO_A	0	0	66299498	64073974	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	66299498	37	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	66299498	35	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	66299498	38	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	66299498	39	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	66299498	80	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	66299498	64073974	0	0
tb.dut.JitterEnableKnownO_A	0	0	66299498	64073974	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	66299498	64073974	0	0
tb.dut.PwrMgrKnownO_A	0	0	66299498	64073974	0	0
tb.dut.TlAReadyKnownO_A	0	0	66299498	64073974	0	0
tb.dut.TlDValidKnownO_A	0	0	66299498	64073974	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	207185770	1797	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	207185770	950	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	773	773	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	95984505	155	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	95984505	155	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	95984505	5015	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	95984505	2911	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	47991829	155	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	47991829	155	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	47991829	5010	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	47991829	2906	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	47991829	155	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	47991829	155	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	47991829	155	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	47991829	155	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	193519678	155	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	193519678	150	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	193519678	5038	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	193519678	2929	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	207185345	1943	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	207185345	1943	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	207185345	1946	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	207185345	1946	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	207185345	146	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	207185345	146	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	207185345	1940	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	207185345	1940	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	207185345	1948	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	207185345	1948	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	207185345	146	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	207185345	146	0	0
tb.dut.clkmgr_cg_usb_infra.CgEnOff_A	0	0	99527570	150	0	0
tb.dut.clkmgr_cg_usb_infra.CgEnOn_A	0	0	99527570	148	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	99527570	5029	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	99527570	2920	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	67152137	1697970	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	67152137	11432	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	67152137	10049	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	67152137	15454	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	67152137	9638	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	67152137	15479	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	67152137	9997	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	193520106	2677	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	193520106	3258	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	95984895	2604	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	95984895	3035	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	66299498	2539	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	66299498	2539	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	66299498	1503	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	66299498	1503	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	66299498	3154	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	66299498	3154	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	207185770	1800	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	207185770	948	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	95984895	1917	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	95984895	3473	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	47992245	1810	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	47992245	3366	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	193520106	1918	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	193520106	3478	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	207185770	1794	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	207185770	960	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	66299498	4448	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	66299498	6066	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	66299498	9288	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	66299498	4377	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	66299498	5540079	0	57
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	66299498	6049	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	207185770	1802	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	207185770	951	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A	0	0	66299498	150	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A	0	0	66299498	150	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A	0	0	66299498	146	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A	0	0	66299498	146	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A	0	0	66299498	148	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A	0	0	66299498	148	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	66299498	63999175	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	66299498	72690	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	66299498	63948476	0	2319
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	66299498	119171	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	66299498	64004214	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	66299498	67651	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	99527977	1900	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	99527977	3460	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	67152137	6429505	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	67152137	64819905	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	67152137	64819905	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	67152137	6032730	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	67152137	64819905	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	67152137	64819905	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	978	978	0	0
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tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	67152712	201176	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	67152712	121721	0	0
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tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	67152712	6429505	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	67152712	6032730	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	67152712	6429505	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	67152712	6032730	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	67152712	6032730	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	67152712	6032730	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	67152137	547007	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	67152137	416841	0	0
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tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
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tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
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tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	207185345	203262678	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	207185345	203262678	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	207185345	203262678	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	207185345	203256298	0	2319
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	207185345	18244	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	207185345	203262678	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	207185345	203262678	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	207185345	203262678	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	66299498	64073974	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	66299498	12028	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	66299498	10599	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	66299498	64073974	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	66299498	1287	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	95984505	1287	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	773	773	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	95984505	1744020	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	773	773	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	95984505	44936	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	7848971	44529	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	95984505	95984505	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	95984505	95984505	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	66299498	64073974	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
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tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	66299498	1277	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	47991829	1277	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	773	773	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	47991829	1663755	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	773	773	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	47991829	44594	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	7848971	44188	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	47991829	47991829	0	0
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tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	193519678	1242	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	773	773	0	0
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tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
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tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	47991829	47519433	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	193519678	189775230	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	193519678	189775230	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	207185345	203262678	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	207185345	203262678	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	99527570	97651058	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	99527570	97651058	0	0
tb.dut.u_reg.en2addrHit	0	0	67152137	397834	0	0
tb.dut.u_reg.reAfterRv	0	0	67152137	397834	0	0
tb.dut.u_reg.rePulse	0	0	67152137	113108	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	978	978	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	67152137	63227	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	97171660	96179629	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	67152137	12348	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	97171660	459	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	67152137	12807	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	97171660	12348	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	97171660	12348	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	12348	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	67152137	90154	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	97171660	96179629	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	67152137	17859	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	67152137	17857	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	97171660	17865	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	97171660	17863	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	17888	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	97171660	96179629	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	67152137	45	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	97171660	45	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	97171660	96179629	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	67152137	38	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	97171660	38	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	67152137	101056	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	48585436	48089527	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	67152137	12348	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	48585436	459	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	67152137	12807	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	48585436	12316	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	48585436	12348	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	12348	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	67152137	144269	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	48585436	48089527	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	67152137	17855	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	67152137	17853	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	48585436	17864	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	48585436	17856	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	17897	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	48585436	48089527	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	67152137	27	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	48585436	27	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	48585436	48089527	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	67152137	26	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	48585436	26	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	67152137	44105	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	195988429	192055403	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	67152137	12348	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	195988429	459	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	67152137	12807	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	195988429	12348	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	195988429	12348	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	12348	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	67152137	62905	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	195988429	192055403	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	67152137	17785	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	67152137	17783	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	195988429	17799	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	195988429	17798	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	17811	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	195988429	192055403	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	67152137	32	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	195988429	32	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	195988429	192055403	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	67152137	29	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	195988429	29	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	67152137	43113	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	209757057	205637955	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	67152137	12348	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	209757057	459	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	67152137	12807	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	209757057	12348	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	209757057	12348	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	12348	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	67152137	62630	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	209757057	205637955	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	67152137	18001	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	67152137	17997	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	209757057	18015	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	209757057	18011	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	18029	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	209757057	205637955	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	67152137	26	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	209757057	26	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	209757057	205637955	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	67152137	26	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	209757057	26	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	978	978	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	978	978	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	978	978	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	978	978	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	978	978	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	978	978	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	978	978	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	67152137	60645	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	100761961	98791180	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	67152137	11848	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	100761961	459	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	67152137	12307	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	100761961	11745	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	100761961	11907	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	12348	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	67152137	89998	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	100761961	98791180	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	67152137	17723	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	67152137	64819905	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	67152137	17692	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	100761961	17868	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	100761961	17818	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	67152137	18005	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	100761961	98791180	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	67152137	33	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	100761961	33	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	978	978	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	100761961	98791180	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	67152137	34	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	100761961	34	0	0
tb.dut.u_reg.wePulse	0	0	67152137	284726	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	66299498	64073974	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	66299498	1111	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	99527570	1111	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	773	773	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	99527570	1746287	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	773	773	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	99527570	54686	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	7876929	54263	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	773	773	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	99527570	98598304	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	99527570	98598304	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	66299498	5540079	0	57
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	66299498	63948476	0	2319
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	207185345	203256298	0	2319
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	207185345	203256298	0	2319
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	207185345	203256298	0	2319
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	207185345	203256298	0	2319
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	193519678	189768903	0	2319
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	97171660	0	0	978
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	48585436	0	0	978
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	195988429	0	0	978
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	209757057	0	0	978
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	100761961	0	0	978
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	66299498	64067453	0	2319

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	67152712	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	67152712	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	67152712	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	67152712	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	67152712	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	67152712	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	67152712	8096	8096	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	67152712	3790	3790	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	67152712	15265	15265	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	67152712	94175	94175	755

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	67152712	8096	8096	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	67152712	3790	3790	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	67152712	15265	15265	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	67152712	94175	94175	755