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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.51 99.15 95.76 100.00 100.00 98.81 97.02 98.80


Total test records in report: 978
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T808 /workspace/coverage/default/11.clkmgr_frequency_timeout.2675012332 Aug 06 07:28:00 PM PDT 24 Aug 06 07:28:01 PM PDT 24 182491642 ps
T809 /workspace/coverage/default/32.clkmgr_frequency.683941844 Aug 06 07:29:51 PM PDT 24 Aug 06 07:30:11 PM PDT 24 2476578302 ps
T41 /workspace/coverage/default/4.clkmgr_sec_cm.699876916 Aug 06 07:27:30 PM PDT 24 Aug 06 07:27:32 PM PDT 24 319342894 ps
T810 /workspace/coverage/default/8.clkmgr_frequency_timeout.4059231121 Aug 06 07:27:43 PM PDT 24 Aug 06 07:27:52 PM PDT 24 2212314349 ps
T811 /workspace/coverage/default/45.clkmgr_regwen.618660283 Aug 06 07:31:06 PM PDT 24 Aug 06 07:31:11 PM PDT 24 784677014 ps
T812 /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2230679822 Aug 06 07:28:34 PM PDT 24 Aug 06 07:28:35 PM PDT 24 17816586 ps
T813 /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1454770651 Aug 06 07:31:03 PM PDT 24 Aug 06 07:31:04 PM PDT 24 114679282 ps
T814 /workspace/coverage/default/34.clkmgr_smoke.802199638 Aug 06 07:30:06 PM PDT 24 Aug 06 07:30:07 PM PDT 24 58039655 ps
T815 /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1860876843 Aug 06 07:28:44 PM PDT 24 Aug 06 07:28:46 PM PDT 24 22834070 ps
T816 /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.2334980806 Aug 06 07:28:31 PM PDT 24 Aug 06 07:28:33 PM PDT 24 352634229 ps
T817 /workspace/coverage/default/20.clkmgr_clk_status.1612058968 Aug 06 07:28:48 PM PDT 24 Aug 06 07:28:49 PM PDT 24 17147100 ps
T818 /workspace/coverage/default/13.clkmgr_div_intersig_mubi.2077398426 Aug 06 07:28:12 PM PDT 24 Aug 06 07:28:13 PM PDT 24 82614373 ps
T819 /workspace/coverage/default/28.clkmgr_smoke.2885141753 Aug 06 07:29:34 PM PDT 24 Aug 06 07:29:35 PM PDT 24 23003272 ps
T820 /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.2735574067 Aug 06 07:30:23 PM PDT 24 Aug 06 07:30:24 PM PDT 24 44764365 ps
T821 /workspace/coverage/default/28.clkmgr_peri.389589019 Aug 06 07:29:32 PM PDT 24 Aug 06 07:29:33 PM PDT 24 41933046 ps
T822 /workspace/coverage/default/25.clkmgr_smoke.2141723597 Aug 06 07:29:13 PM PDT 24 Aug 06 07:29:14 PM PDT 24 129029249 ps
T823 /workspace/coverage/default/2.clkmgr_trans.3673581016 Aug 06 07:27:11 PM PDT 24 Aug 06 07:27:12 PM PDT 24 21716886 ps
T824 /workspace/coverage/default/6.clkmgr_alert_test.1632656145 Aug 06 07:27:28 PM PDT 24 Aug 06 07:27:29 PM PDT 24 43003665 ps
T825 /workspace/coverage/default/19.clkmgr_peri.2226393251 Aug 06 07:28:44 PM PDT 24 Aug 06 07:28:45 PM PDT 24 73061764 ps
T826 /workspace/coverage/default/17.clkmgr_div_intersig_mubi.815082239 Aug 06 07:28:34 PM PDT 24 Aug 06 07:28:35 PM PDT 24 83422373 ps
T827 /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2967426343 Aug 06 07:28:00 PM PDT 24 Aug 06 07:28:02 PM PDT 24 76019508 ps
T828 /workspace/coverage/default/2.clkmgr_frequency.1297036642 Aug 06 07:26:54 PM PDT 24 Aug 06 07:27:03 PM PDT 24 1157046189 ps
T829 /workspace/coverage/default/36.clkmgr_div_intersig_mubi.1375822718 Aug 06 07:30:21 PM PDT 24 Aug 06 07:30:21 PM PDT 24 23512709 ps
T830 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.59360126 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:31 PM PDT 24 46701618 ps
T107 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.791412491 Aug 06 07:17:32 PM PDT 24 Aug 06 07:17:33 PM PDT 24 39882670 ps
T831 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.796920942 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:52 PM PDT 24 29388225 ps
T76 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2629614176 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:30 PM PDT 24 42271762 ps
T832 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.3845005697 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:46 PM PDT 24 20049074 ps
T77 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.909761138 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:06 PM PDT 24 17371407 ps
T78 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3688469995 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:30 PM PDT 24 235744759 ps
T100 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2717972314 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:33 PM PDT 24 244456828 ps
T60 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.739639046 Aug 06 07:17:26 PM PDT 24 Aug 06 07:17:28 PM PDT 24 109639307 ps
T833 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2621640671 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:28 PM PDT 24 31335177 ps
T834 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4115249105 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 11437727 ps
T61 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2510859934 Aug 06 07:17:07 PM PDT 24 Aug 06 07:17:09 PM PDT 24 59393596 ps
T835 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.4022680812 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:29 PM PDT 24 23535854 ps
T62 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2488960029 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:56 PM PDT 24 367169939 ps
T79 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3772009145 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:29 PM PDT 24 15382545 ps
T80 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.4205034979 Aug 06 07:17:25 PM PDT 24 Aug 06 07:17:26 PM PDT 24 31055951 ps
T171 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1544167050 Aug 06 07:16:50 PM PDT 24 Aug 06 07:16:51 PM PDT 24 50255183 ps
T836 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.297818816 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:53 PM PDT 24 14670981 ps
T837 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1638996055 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:29 PM PDT 24 114146784 ps
T838 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3409317375 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:53 PM PDT 24 42773939 ps
T839 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1536727133 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:18 PM PDT 24 24062343 ps
T172 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4104586988 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:54 PM PDT 24 115994382 ps
T840 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2501336703 Aug 06 07:17:08 PM PDT 24 Aug 06 07:17:09 PM PDT 24 27154711 ps
T81 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1072794587 Aug 06 07:16:55 PM PDT 24 Aug 06 07:16:57 PM PDT 24 62387879 ps
T841 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3072824876 Aug 06 07:17:08 PM PDT 24 Aug 06 07:17:10 PM PDT 24 73600716 ps
T82 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3003691135 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:07 PM PDT 24 19914126 ps
T842 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1952668466 Aug 06 07:16:54 PM PDT 24 Aug 06 07:16:55 PM PDT 24 44538642 ps
T173 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2507420122 Aug 06 07:17:07 PM PDT 24 Aug 06 07:17:08 PM PDT 24 41687328 ps
T843 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3150171463 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:31 PM PDT 24 12700482 ps
T844 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3954597607 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:07 PM PDT 24 59054383 ps
T101 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.852277388 Aug 06 07:17:25 PM PDT 24 Aug 06 07:17:27 PM PDT 24 67340165 ps
T845 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2185042569 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:06 PM PDT 24 27414162 ps
T102 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1151255682 Aug 06 07:16:55 PM PDT 24 Aug 06 07:16:57 PM PDT 24 107663629 ps
T846 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1875677170 Aug 06 07:16:58 PM PDT 24 Aug 06 07:17:00 PM PDT 24 120318106 ps
T847 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3631705240 Aug 06 07:17:31 PM PDT 24 Aug 06 07:17:32 PM PDT 24 21953236 ps
T848 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1221342130 Aug 06 07:17:49 PM PDT 24 Aug 06 07:17:50 PM PDT 24 20984986 ps
T849 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.821616047 Aug 06 07:17:25 PM PDT 24 Aug 06 07:17:29 PM PDT 24 104238414 ps
T174 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.933090730 Aug 06 07:16:56 PM PDT 24 Aug 06 07:16:57 PM PDT 24 34451010 ps
T104 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3504045355 Aug 06 07:17:04 PM PDT 24 Aug 06 07:17:07 PM PDT 24 186153566 ps
T850 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2913001077 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:30 PM PDT 24 14307711 ps
T63 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3798223698 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:30 PM PDT 24 93630128 ps
T851 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2541255905 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:56 PM PDT 24 345813510 ps
T852 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.62575605 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 18029925 ps
T65 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2511279611 Aug 06 07:16:55 PM PDT 24 Aug 06 07:16:57 PM PDT 24 163433506 ps
T64 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.4212439174 Aug 06 07:17:33 PM PDT 24 Aug 06 07:17:35 PM PDT 24 164251971 ps
T853 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.1560021315 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:30 PM PDT 24 26296103 ps
T854 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1014816120 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:52 PM PDT 24 46428896 ps
T855 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3086319352 Aug 06 07:17:26 PM PDT 24 Aug 06 07:17:27 PM PDT 24 51793714 ps
T856 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.4102639226 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:53 PM PDT 24 26753429 ps
T857 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.237645502 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:28 PM PDT 24 16079673 ps
T858 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2465427 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:34 PM PDT 24 703642851 ps
T859 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2165509193 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:30 PM PDT 24 126296323 ps
T860 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3157433986 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:28 PM PDT 24 27246454 ps
T861 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3116510105 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:54 PM PDT 24 48434004 ps
T862 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3205672670 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:30 PM PDT 24 12155911 ps
T863 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1997598464 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:53 PM PDT 24 120136081 ps
T864 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.236981144 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:08 PM PDT 24 88701416 ps
T865 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.713966828 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:29 PM PDT 24 55837078 ps
T866 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2890714880 Aug 06 07:16:54 PM PDT 24 Aug 06 07:16:55 PM PDT 24 74417435 ps
T867 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3148000479 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:09 PM PDT 24 313974693 ps
T67 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.230380056 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:07 PM PDT 24 109748733 ps
T66 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.300008146 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:31 PM PDT 24 185253170 ps
T191 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1126177017 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:30 PM PDT 24 194700610 ps
T868 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1953813527 Aug 06 07:17:04 PM PDT 24 Aug 06 07:17:05 PM PDT 24 66872111 ps
T869 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2590225362 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:29 PM PDT 24 31577297 ps
T870 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.3619137106 Aug 06 07:17:44 PM PDT 24 Aug 06 07:17:45 PM PDT 24 21235530 ps
T871 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1324849088 Aug 06 07:17:19 PM PDT 24 Aug 06 07:17:23 PM PDT 24 153376699 ps
T872 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1779081900 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:18 PM PDT 24 62819756 ps
T873 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3712310745 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:54 PM PDT 24 71450499 ps
T874 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3665750830 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:30 PM PDT 24 46181562 ps
T875 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1223303068 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:06 PM PDT 24 12575813 ps
T876 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.393986947 Aug 06 07:17:03 PM PDT 24 Aug 06 07:17:04 PM PDT 24 23239132 ps
T132 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.445747457 Aug 06 07:17:03 PM PDT 24 Aug 06 07:17:05 PM PDT 24 61612970 ps
T877 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3461229400 Aug 06 07:17:04 PM PDT 24 Aug 06 07:17:06 PM PDT 24 230902192 ps
T878 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1612724794 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 36469027 ps
T879 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3994844432 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:29 PM PDT 24 19980036 ps
T880 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3903261003 Aug 06 07:17:07 PM PDT 24 Aug 06 07:17:08 PM PDT 24 30374073 ps
T881 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1928202912 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:29 PM PDT 24 22170946 ps
T882 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.266098750 Aug 06 07:17:31 PM PDT 24 Aug 06 07:17:32 PM PDT 24 14905166 ps
T883 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3955528560 Aug 06 07:16:55 PM PDT 24 Aug 06 07:16:56 PM PDT 24 29874439 ps
T884 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.850563661 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:33 PM PDT 24 41913687 ps
T112 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2232258928 Aug 06 07:17:03 PM PDT 24 Aug 06 07:17:05 PM PDT 24 209273372 ps
T121 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2278189443 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:55 PM PDT 24 491870975 ps
T885 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1726909120 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:19 PM PDT 24 80664578 ps
T886 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.898457804 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:18 PM PDT 24 17798852 ps
T887 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2046054265 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:18 PM PDT 24 13392244 ps
T888 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1502026603 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:52 PM PDT 24 26362105 ps
T889 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2382268153 Aug 06 07:17:32 PM PDT 24 Aug 06 07:17:34 PM PDT 24 44470014 ps
T127 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3625925118 Aug 06 07:16:50 PM PDT 24 Aug 06 07:16:53 PM PDT 24 154293700 ps
T890 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.2953682406 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:53 PM PDT 24 65960418 ps
T891 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3613453223 Aug 06 07:17:49 PM PDT 24 Aug 06 07:17:50 PM PDT 24 37024149 ps
T133 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2666557138 Aug 06 07:16:58 PM PDT 24 Aug 06 07:17:00 PM PDT 24 150695936 ps
T892 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2628332452 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:54 PM PDT 24 78626287 ps
T893 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1048409135 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:58 PM PDT 24 707523266 ps
T894 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.493774727 Aug 06 07:17:24 PM PDT 24 Aug 06 07:17:24 PM PDT 24 17486972 ps
T895 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1907838607 Aug 06 07:16:55 PM PDT 24 Aug 06 07:16:56 PM PDT 24 69191852 ps
T896 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1601188250 Aug 06 07:17:26 PM PDT 24 Aug 06 07:17:27 PM PDT 24 33100106 ps
T897 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.26724271 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:57 PM PDT 24 116742811 ps
T898 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2911008915 Aug 06 07:16:51 PM PDT 24 Aug 06 07:17:04 PM PDT 24 2565040758 ps
T105 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.935334861 Aug 06 07:16:50 PM PDT 24 Aug 06 07:16:53 PM PDT 24 359470983 ps
T899 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3444910944 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:05 PM PDT 24 12167401 ps
T900 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1088382870 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:08 PM PDT 24 112367816 ps
T901 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2503384667 Aug 06 07:17:18 PM PDT 24 Aug 06 07:17:20 PM PDT 24 49673369 ps
T902 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.249305269 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 88338833 ps
T903 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2426752003 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:07 PM PDT 24 14001838 ps
T190 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3045774055 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:31 PM PDT 24 133111726 ps
T904 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.1877487073 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:29 PM PDT 24 123536157 ps
T128 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.254608671 Aug 06 07:16:54 PM PDT 24 Aug 06 07:16:56 PM PDT 24 246110993 ps
T905 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1876417995 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:19 PM PDT 24 74055749 ps
T906 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3042545445 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:06 PM PDT 24 24362475 ps
T907 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1111641551 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 13891371 ps
T908 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1513296677 Aug 06 07:17:01 PM PDT 24 Aug 06 07:17:02 PM PDT 24 102124896 ps
T122 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.656449311 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:07 PM PDT 24 105182685 ps
T909 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.272165293 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:31 PM PDT 24 62370877 ps
T910 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.620260082 Aug 06 07:16:49 PM PDT 24 Aug 06 07:16:50 PM PDT 24 218680703 ps
T911 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1763261541 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:07 PM PDT 24 70468985 ps
T912 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2234493484 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:30 PM PDT 24 34271885 ps
T123 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3461358878 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:54 PM PDT 24 263744554 ps
T913 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2099104610 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 28243003 ps
T914 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2353197794 Aug 06 07:17:26 PM PDT 24 Aug 06 07:17:27 PM PDT 24 19019059 ps
T124 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2952532375 Aug 06 07:17:31 PM PDT 24 Aug 06 07:17:32 PM PDT 24 120386430 ps
T915 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.297078362 Aug 06 07:16:59 PM PDT 24 Aug 06 07:17:00 PM PDT 24 21218331 ps
T916 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3116074161 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:30 PM PDT 24 58442662 ps
T917 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3603952466 Aug 06 07:16:50 PM PDT 24 Aug 06 07:16:52 PM PDT 24 189260088 ps
T918 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2331629939 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 13924385 ps
T919 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2692398268 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:29 PM PDT 24 75893852 ps
T920 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2461120358 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:29 PM PDT 24 14125923 ps
T134 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.914018451 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:08 PM PDT 24 92164466 ps
T125 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3246793830 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:29 PM PDT 24 110214646 ps
T921 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2946779187 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:53 PM PDT 24 57297715 ps
T922 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.46499263 Aug 06 07:17:47 PM PDT 24 Aug 06 07:17:48 PM PDT 24 30386053 ps
T923 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3429985443 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:06 PM PDT 24 15500240 ps
T108 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2044361243 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:08 PM PDT 24 133325538 ps
T924 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3200788742 Aug 06 07:17:47 PM PDT 24 Aug 06 07:17:48 PM PDT 24 13618663 ps
T925 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.529642792 Aug 06 07:16:55 PM PDT 24 Aug 06 07:16:57 PM PDT 24 86884693 ps
T926 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3760541355 Aug 06 07:17:47 PM PDT 24 Aug 06 07:17:48 PM PDT 24 72587720 ps
T109 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1103597729 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:33 PM PDT 24 365499699 ps
T113 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3267585030 Aug 06 07:17:08 PM PDT 24 Aug 06 07:17:11 PM PDT 24 148551698 ps
T927 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.873442551 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:31 PM PDT 24 96056310 ps
T928 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1597294992 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:28 PM PDT 24 12715011 ps
T929 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.327155370 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:32 PM PDT 24 118482074 ps
T129 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.4311987 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:54 PM PDT 24 488249692 ps
T930 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3810364812 Aug 06 07:17:25 PM PDT 24 Aug 06 07:17:28 PM PDT 24 797739335 ps
T931 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3188577359 Aug 06 07:17:16 PM PDT 24 Aug 06 07:17:17 PM PDT 24 17584663 ps
T932 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3892132468 Aug 06 07:17:33 PM PDT 24 Aug 06 07:17:34 PM PDT 24 37677844 ps
T933 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3297250932 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:54 PM PDT 24 116445803 ps
T934 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1186476674 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:55 PM PDT 24 62682606 ps
T935 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1241742520 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:56 PM PDT 24 479633539 ps
T936 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1960008259 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:18 PM PDT 24 38966798 ps
T126 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1088838911 Aug 06 07:17:26 PM PDT 24 Aug 06 07:17:29 PM PDT 24 236074217 ps
T139 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.739472037 Aug 06 07:17:24 PM PDT 24 Aug 06 07:17:27 PM PDT 24 147194350 ps
T937 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1179038596 Aug 06 07:17:26 PM PDT 24 Aug 06 07:17:27 PM PDT 24 33709695 ps
T938 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3993497832 Aug 06 07:16:50 PM PDT 24 Aug 06 07:16:51 PM PDT 24 14874272 ps
T939 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3264205165 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:20 PM PDT 24 119477418 ps
T940 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.268216892 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:30 PM PDT 24 436844861 ps
T941 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3643982377 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:56 PM PDT 24 122231184 ps
T130 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2683107140 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:31 PM PDT 24 54588019 ps
T942 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.476275336 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:46 PM PDT 24 18280094 ps
T943 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2748203649 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:30 PM PDT 24 11134520 ps
T944 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3383359451 Aug 06 07:16:54 PM PDT 24 Aug 06 07:16:55 PM PDT 24 65438948 ps
T140 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.480255909 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:08 PM PDT 24 155855767 ps
T135 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.234820566 Aug 06 07:17:27 PM PDT 24 Aug 06 07:17:32 PM PDT 24 1366074422 ps
T945 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1665691115 Aug 06 07:17:32 PM PDT 24 Aug 06 07:17:33 PM PDT 24 93523361 ps
T946 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1470363849 Aug 06 07:17:25 PM PDT 24 Aug 06 07:17:27 PM PDT 24 35076556 ps
T947 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3723147593 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:31 PM PDT 24 15700950 ps
T948 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1627206991 Aug 06 07:17:32 PM PDT 24 Aug 06 07:17:33 PM PDT 24 13811312 ps
T949 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2677114849 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:31 PM PDT 24 91197996 ps
T136 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.800785077 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:54 PM PDT 24 125523581 ps
T950 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3311563697 Aug 06 07:16:50 PM PDT 24 Aug 06 07:16:54 PM PDT 24 128796061 ps
T951 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.4080948658 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:56 PM PDT 24 627485011 ps
T131 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1741240383 Aug 06 07:17:07 PM PDT 24 Aug 06 07:17:09 PM PDT 24 100167631 ps
T952 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2830647365 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:54 PM PDT 24 270697383 ps
T953 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.301017238 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 14687577 ps
T142 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3733147025 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:19 PM PDT 24 78235066 ps
T954 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1207471790 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:19 PM PDT 24 116017681 ps
T955 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3613875616 Aug 06 07:17:48 PM PDT 24 Aug 06 07:17:48 PM PDT 24 13412975 ps
T956 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1503294082 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:18 PM PDT 24 36141427 ps
T141 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.220445607 Aug 06 07:17:04 PM PDT 24 Aug 06 07:17:06 PM PDT 24 201726203 ps
T957 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2588329118 Aug 06 07:17:45 PM PDT 24 Aug 06 07:17:46 PM PDT 24 15624721 ps
T958 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2133948555 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:30 PM PDT 24 86992542 ps
T110 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3690520631 Aug 06 07:17:04 PM PDT 24 Aug 06 07:17:06 PM PDT 24 60720603 ps
T959 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.770219563 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:56 PM PDT 24 357161537 ps
T960 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.479069575 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:31 PM PDT 24 39506476 ps
T143 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3116553822 Aug 06 07:17:17 PM PDT 24 Aug 06 07:17:20 PM PDT 24 301879154 ps
T961 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2019612801 Aug 06 07:17:29 PM PDT 24 Aug 06 07:17:31 PM PDT 24 92796174 ps
T137 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2598736667 Aug 06 07:17:26 PM PDT 24 Aug 06 07:17:28 PM PDT 24 161306421 ps
T962 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.46260406 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:30 PM PDT 24 156506322 ps
T138 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2671928315 Aug 06 07:17:05 PM PDT 24 Aug 06 07:17:06 PM PDT 24 52789900 ps
T963 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1025579493 Aug 06 07:17:04 PM PDT 24 Aug 06 07:17:05 PM PDT 24 18080230 ps
T964 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3275886895 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:09 PM PDT 24 124743908 ps
T965 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1290647799 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:54 PM PDT 24 94983496 ps
T966 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3278505042 Aug 06 07:17:30 PM PDT 24 Aug 06 07:17:31 PM PDT 24 116254525 ps
T967 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3253634098 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:08 PM PDT 24 41165657 ps
T968 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1200696914 Aug 06 07:17:16 PM PDT 24 Aug 06 07:17:19 PM PDT 24 343004707 ps
T969 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2127513548 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:07 PM PDT 24 32689388 ps
T970 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2744986342 Aug 06 07:16:52 PM PDT 24 Aug 06 07:16:53 PM PDT 24 49043266 ps
T971 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2475569990 Aug 06 07:16:51 PM PDT 24 Aug 06 07:16:52 PM PDT 24 15597159 ps
T972 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2808919132 Aug 06 07:16:58 PM PDT 24 Aug 06 07:17:02 PM PDT 24 313210775 ps
T973 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2452286143 Aug 06 07:17:46 PM PDT 24 Aug 06 07:17:47 PM PDT 24 38271250 ps
T974 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.96564018 Aug 06 07:17:26 PM PDT 24 Aug 06 07:17:28 PM PDT 24 275893455 ps
T975 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.3544101288 Aug 06 07:17:06 PM PDT 24 Aug 06 07:17:09 PM PDT 24 153714549 ps
T111 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1020683248 Aug 06 07:16:53 PM PDT 24 Aug 06 07:16:55 PM PDT 24 221549681 ps
T976 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2759236317 Aug 06 07:17:04 PM PDT 24 Aug 06 07:17:06 PM PDT 24 67685868 ps
T977 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1277458129 Aug 06 07:16:59 PM PDT 24 Aug 06 07:17:00 PM PDT 24 87721987 ps
T978 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.4113383879 Aug 06 07:17:28 PM PDT 24 Aug 06 07:17:29 PM PDT 24 16057878 ps

Test location /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.1070676054
Short name T2
Test name
Test status
Simulation time 19853536364 ps
CPU time 304.85 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:32:02 PM PDT 24
Peak memory 217892 kb
Host smart-547f5df5-f45e-4feb-af4e-000cccc4bf77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1070676054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.1070676054
Directory /workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.1497846055
Short name T23
Test name
Test status
Simulation time 1274280868 ps
CPU time 6.47 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:52 PM PDT 24
Peak memory 201304 kb
Host smart-6e2f4d16-23a1-4703-836b-368cdc4b88ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497846055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1497846055
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3625925118
Short name T127
Test name
Test status
Simulation time 154293700 ps
CPU time 2.05 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 209024 kb
Host smart-977edf00-b2a5-4d51-8d93-a60dfbb86271
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625925118 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.3625925118
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.3625435081
Short name T51
Test name
Test status
Simulation time 578307455 ps
CPU time 3.6 seconds
Started Aug 06 07:26:58 PM PDT 24
Finished Aug 06 07:27:02 PM PDT 24
Peak memory 217932 kb
Host smart-a12e891c-0b3c-4304-a452-64483980415d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625435081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.3625435081
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.1298300595
Short name T3
Test name
Test status
Simulation time 2817505049 ps
CPU time 13.23 seconds
Started Aug 06 07:30:56 PM PDT 24
Finished Aug 06 07:31:09 PM PDT 24
Peak memory 201468 kb
Host smart-7a021e0a-bd28-4fd7-8d68-ee4471062d3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298300595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.1298300595
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.1277742313
Short name T37
Test name
Test status
Simulation time 14448488 ps
CPU time 0.73 seconds
Started Aug 06 07:28:33 PM PDT 24
Finished Aug 06 07:28:33 PM PDT 24
Peak memory 200284 kb
Host smart-041588f8-9106-42e9-acf7-af394f223442
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277742313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1277742313
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2510859934
Short name T61
Test name
Test status
Simulation time 59393596 ps
CPU time 1.72 seconds
Started Aug 06 07:17:07 PM PDT 24
Finished Aug 06 07:17:09 PM PDT 24
Peak memory 210088 kb
Host smart-31c960bb-5a33-497f-8023-841bc84a1c9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510859934 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.2510859934
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1814249564
Short name T17
Test name
Test status
Simulation time 17365533 ps
CPU time 0.92 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:48 PM PDT 24
Peak memory 201092 kb
Host smart-22c8d73b-9fdd-4b30-85d6-e42a86a33326
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814249564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.1814249564
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.935334861
Short name T105
Test name
Test status
Simulation time 359470983 ps
CPU time 2.86 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 200560 kb
Host smart-e86ed361-8f5f-49d4-a399-b2b9ac77cb15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935334861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_tl_intg_err.935334861
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.3633874386
Short name T26
Test name
Test status
Simulation time 26676711109 ps
CPU time 239.1 seconds
Started Aug 06 07:29:32 PM PDT 24
Finished Aug 06 07:33:31 PM PDT 24
Peak memory 218024 kb
Host smart-a31a3154-8f80-4822-9101-4bb5809df772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3633874386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.3633874386
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.3040920919
Short name T13
Test name
Test status
Simulation time 44609985877 ps
CPU time 792.75 seconds
Started Aug 06 07:28:00 PM PDT 24
Finished Aug 06 07:41:13 PM PDT 24
Peak memory 209712 kb
Host smart-0e8fa5c1-3142-4352-b6c4-c100819ab7af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3040920919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3040920919
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.1083991743
Short name T32
Test name
Test status
Simulation time 88127970230 ps
CPU time 528.49 seconds
Started Aug 06 07:30:06 PM PDT 24
Finished Aug 06 07:38:54 PM PDT 24
Peak memory 212316 kb
Host smart-84c6aac9-dab2-4fba-9f4b-f583c77f86e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1083991743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.1083991743
Directory /workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.3123575161
Short name T16
Test name
Test status
Simulation time 45177784 ps
CPU time 0.94 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201088 kb
Host smart-9d70967b-659f-4356-b7b2-045e21867fcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123575161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.3123575161
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3116553822
Short name T143
Test name
Test status
Simulation time 301879154 ps
CPU time 2.25 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:20 PM PDT 24
Peak memory 208928 kb
Host smart-0435b5f9-1dd4-4be0-8380-c8753844537d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116553822 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.3116553822
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2691592184
Short name T83
Test name
Test status
Simulation time 285431738 ps
CPU time 1.68 seconds
Started Aug 06 07:29:50 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201092 kb
Host smart-c6937fb5-cd2f-4460-969d-3587d935c189
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691592184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.2691592184
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.3213998649
Short name T8
Test name
Test status
Simulation time 1060881295 ps
CPU time 6.04 seconds
Started Aug 06 07:28:08 PM PDT 24
Finished Aug 06 07:28:14 PM PDT 24
Peak memory 201260 kb
Host smart-1a291ed3-848a-4a9a-9d72-d4bef8330fc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213998649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3213998649
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.2836014772
Short name T38
Test name
Test status
Simulation time 332038516 ps
CPU time 3.36 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:59 PM PDT 24
Peak memory 217888 kb
Host smart-c84a5af1-e500-4dba-807f-a98118a169e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836014772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.2836014772
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2232258928
Short name T112
Test name
Test status
Simulation time 209273372 ps
CPU time 2.04 seconds
Started Aug 06 07:17:03 PM PDT 24
Finished Aug 06 07:17:05 PM PDT 24
Peak memory 200568 kb
Host smart-d0fa8282-71b6-451a-8897-cc4f2ec1c3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232258928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.2232258928
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.3564972085
Short name T195
Test name
Test status
Simulation time 219820538704 ps
CPU time 1127.47 seconds
Started Aug 06 07:30:42 PM PDT 24
Finished Aug 06 07:49:29 PM PDT 24
Peak memory 214680 kb
Host smart-376d31fc-1033-4bb3-9f9f-2e273761391c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3564972085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.3564972085
Directory /workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.800785077
Short name T136
Test name
Test status
Simulation time 125523581 ps
CPU time 2.09 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 200900 kb
Host smart-c26edd58-4372-41ee-ab91-5309e7b9ac67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800785077 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.clkmgr_shadow_reg_errors.800785077
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2598736667
Short name T137
Test name
Test status
Simulation time 161306421 ps
CPU time 1.54 seconds
Started Aug 06 07:17:26 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 200640 kb
Host smart-4f1cfe38-79c7-4e1b-9320-88886d1075ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598736667 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.2598736667
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1103597729
Short name T109
Test name
Test status
Simulation time 365499699 ps
CPU time 3.25 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:33 PM PDT 24
Peak memory 200592 kb
Host smart-af1786d5-4e3b-4f17-b407-ef05c5c334af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103597729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.1103597729
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1502026603
Short name T888
Test name
Test status
Simulation time 26362105 ps
CPU time 1.09 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:52 PM PDT 24
Peak memory 200332 kb
Host smart-7cc1c331-3c30-4670-83b8-b931eb44b62e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502026603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.1502026603
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1241742520
Short name T935
Test name
Test status
Simulation time 479633539 ps
CPU time 4.45 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 200592 kb
Host smart-4cdb5e20-4156-4152-ba41-f2bbe7900de2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241742520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.1241742520
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2946779187
Short name T921
Test name
Test status
Simulation time 57297715 ps
CPU time 0.84 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 200176 kb
Host smart-52f41006-942d-4110-a8da-f42631af6bfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946779187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.2946779187
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1952668466
Short name T842
Test name
Test status
Simulation time 44538642 ps
CPU time 1.4 seconds
Started Aug 06 07:16:54 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 200504 kb
Host smart-75e57231-e8aa-4806-85a6-ab2f001ebd69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952668466 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.1952668466
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3993497832
Short name T938
Test name
Test status
Simulation time 14874272 ps
CPU time 0.78 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:16:51 PM PDT 24
Peak memory 200332 kb
Host smart-7551b8eb-ca4e-4617-a6fa-2d1658cf8872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993497832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.3993497832
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.796920942
Short name T831
Test name
Test status
Simulation time 29388225 ps
CPU time 0.67 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:52 PM PDT 24
Peak memory 198960 kb
Host smart-9161554b-af25-4397-bbe7-e73270518c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796920942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm
gr_intr_test.796920942
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1513296677
Short name T908
Test name
Test status
Simulation time 102124896 ps
CPU time 1.46 seconds
Started Aug 06 07:17:01 PM PDT 24
Finished Aug 06 07:17:02 PM PDT 24
Peak memory 200480 kb
Host smart-94295f0d-e16b-49d0-b7c8-c07607cd8c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513296677 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.1513296677
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.770219563
Short name T959
Test name
Test status
Simulation time 357161537 ps
CPU time 2.59 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 200880 kb
Host smart-53bb69c1-40a5-4ffb-af48-4b015acc2ff6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770219563 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.clkmgr_shadow_reg_errors.770219563
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1290647799
Short name T965
Test name
Test status
Simulation time 94983496 ps
CPU time 2.41 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 201132 kb
Host smart-383ec444-55b6-4933-88df-6fd796703a91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290647799 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.1290647799
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4104586988
Short name T172
Test name
Test status
Simulation time 115994382 ps
CPU time 2.78 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 200540 kb
Host smart-7c295622-40d8-4b9e-bacd-a261d609f778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104586988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.4104586988
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1072794587
Short name T81
Test name
Test status
Simulation time 62387879 ps
CPU time 1.12 seconds
Started Aug 06 07:16:55 PM PDT 24
Finished Aug 06 07:16:57 PM PDT 24
Peak memory 200320 kb
Host smart-23ea54ab-26b2-4693-8529-9d2f039952db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072794587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.1072794587
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2911008915
Short name T898
Test name
Test status
Simulation time 2565040758 ps
CPU time 13.1 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:17:04 PM PDT 24
Peak memory 200652 kb
Host smart-b665dee7-e333-44ae-b1b7-d27896923250
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911008915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.2911008915
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2628332452
Short name T892
Test name
Test status
Simulation time 78626287 ps
CPU time 0.92 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 200416 kb
Host smart-70186484-8357-4e0d-8cb3-0cca381011c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628332452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2628332452
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.529642792
Short name T925
Test name
Test status
Simulation time 86884693 ps
CPU time 1.54 seconds
Started Aug 06 07:16:55 PM PDT 24
Finished Aug 06 07:16:57 PM PDT 24
Peak memory 200456 kb
Host smart-58488eae-2272-40e7-81af-7d388a9e7daa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529642792 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.529642792
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.297818816
Short name T836
Test name
Test status
Simulation time 14670981 ps
CPU time 0.74 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 200408 kb
Host smart-ce07e444-abf7-4cd8-a940-e01c46207994
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297818816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.c
lkmgr_csr_rw.297818816
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3409317375
Short name T838
Test name
Test status
Simulation time 42773939 ps
CPU time 0.69 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 198876 kb
Host smart-1aa76245-ca60-4316-b511-35dbd6e5da1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409317375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.3409317375
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.933090730
Short name T174
Test name
Test status
Simulation time 34451010 ps
CPU time 1.11 seconds
Started Aug 06 07:16:56 PM PDT 24
Finished Aug 06 07:16:57 PM PDT 24
Peak memory 200376 kb
Host smart-969f5b99-6592-436c-b375-c22f5a383293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933090730 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.clkmgr_same_csr_outstanding.933090730
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2278189443
Short name T121
Test name
Test status
Simulation time 491870975 ps
CPU time 3.81 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 209012 kb
Host smart-aac630d5-2803-4662-a185-f9af544b7fd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278189443 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.2278189443
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.26724271
Short name T897
Test name
Test status
Simulation time 116742811 ps
CPU time 3.23 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:57 PM PDT 24
Peak memory 200576 kb
Host smart-82fca101-1148-42f7-8c1e-73be9aa57cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26724271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmg
r_tl_errors.26724271
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1020683248
Short name T111
Test name
Test status
Simulation time 221549681 ps
CPU time 2.66 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 200568 kb
Host smart-75e5364c-2b01-4f02-98ec-9076e8db9439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020683248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.1020683248
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.3253634098
Short name T967
Test name
Test status
Simulation time 41165657 ps
CPU time 1.23 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:08 PM PDT 24
Peak memory 200528 kb
Host smart-e3355f8a-2b53-48b3-859c-3c3a807a573a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253634098 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.3253634098
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3429985443
Short name T923
Test name
Test status
Simulation time 15500240 ps
CPU time 0.8 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 200288 kb
Host smart-aafc666b-6de3-40a2-b8b8-fe1e0dc46041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429985443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3429985443
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1025579493
Short name T963
Test name
Test status
Simulation time 18080230 ps
CPU time 0.73 seconds
Started Aug 06 07:17:04 PM PDT 24
Finished Aug 06 07:17:05 PM PDT 24
Peak memory 199076 kb
Host smart-ec91afea-d6ae-4502-ae48-6331fa088c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025579493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1025579493
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.236981144
Short name T864
Test name
Test status
Simulation time 88701416 ps
CPU time 1.37 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:08 PM PDT 24
Peak memory 200560 kb
Host smart-869eb81e-6156-4c0b-a7fc-b633013766b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236981144 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.clkmgr_same_csr_outstanding.236981144
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.480255909
Short name T140
Test name
Test status
Simulation time 155855767 ps
CPU time 1.53 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:08 PM PDT 24
Peak memory 200644 kb
Host smart-cc180936-87db-4bb9-afd6-001ba81bf468
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480255909 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.clkmgr_shadow_reg_errors.480255909
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3733147025
Short name T142
Test name
Test status
Simulation time 78235066 ps
CPU time 1.77 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:19 PM PDT 24
Peak memory 200956 kb
Host smart-22bf77cc-5af5-4c31-a9a3-0ed531230e39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733147025 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3733147025
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1324849088
Short name T871
Test name
Test status
Simulation time 153376699 ps
CPU time 2.9 seconds
Started Aug 06 07:17:19 PM PDT 24
Finished Aug 06 07:17:23 PM PDT 24
Peak memory 200588 kb
Host smart-5430d0bf-0203-43bb-b731-b5e7f55cef0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324849088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.1324849088
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3267585030
Short name T113
Test name
Test status
Simulation time 148551698 ps
CPU time 3.03 seconds
Started Aug 06 07:17:08 PM PDT 24
Finished Aug 06 07:17:11 PM PDT 24
Peak memory 200612 kb
Host smart-0d0765de-c184-4ef7-9156-a9e60ea86875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267585030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.3267585030
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1088382870
Short name T900
Test name
Test status
Simulation time 112367816 ps
CPU time 1.94 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:08 PM PDT 24
Peak memory 200656 kb
Host smart-5d89f6a4-d9a3-4a3e-a90b-329b52f81ddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088382870 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1088382870
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.2426752003
Short name T903
Test name
Test status
Simulation time 14001838 ps
CPU time 0.74 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 200412 kb
Host smart-c14be9a3-1a70-4bb2-9fe0-d35497174fee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426752003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.2426752003
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3188577359
Short name T931
Test name
Test status
Simulation time 17584663 ps
CPU time 0.66 seconds
Started Aug 06 07:17:16 PM PDT 24
Finished Aug 06 07:17:17 PM PDT 24
Peak memory 198976 kb
Host smart-bb99b2cf-d383-4d6c-8cb8-2414d00f2c46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188577359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.3188577359
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1503294082
Short name T956
Test name
Test status
Simulation time 36141427 ps
CPU time 1.08 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:18 PM PDT 24
Peak memory 200420 kb
Host smart-63b0f710-c98e-47fa-83db-e091e13e03d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503294082 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.1503294082
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.3544101288
Short name T975
Test name
Test status
Simulation time 153714549 ps
CPU time 2.42 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:09 PM PDT 24
Peak memory 200872 kb
Host smart-8b2232bb-a725-42a9-80f1-67bc63134b9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544101288 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.3544101288
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2185042569
Short name T845
Test name
Test status
Simulation time 27414162 ps
CPU time 1.6 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 200568 kb
Host smart-d627357a-7ec4-4c82-9a47-fbde1e7ea153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185042569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.2185042569
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3275886895
Short name T964
Test name
Test status
Simulation time 124743908 ps
CPU time 2.55 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:09 PM PDT 24
Peak memory 200596 kb
Host smart-9bf76dc4-0e96-472e-8ec5-1bc60f2c183e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275886895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.3275886895
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3157433986
Short name T860
Test name
Test status
Simulation time 27246454 ps
CPU time 1.29 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 200616 kb
Host smart-a0c9ab44-3a53-49e1-8e75-e0670c211451
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157433986 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3157433986
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3772009145
Short name T79
Test name
Test status
Simulation time 15382545 ps
CPU time 0.83 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 200388 kb
Host smart-59766a80-9ea7-49c3-839b-ff0ed7f00297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772009145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.3772009145
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.237645502
Short name T857
Test name
Test status
Simulation time 16079673 ps
CPU time 0.65 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 198972 kb
Host smart-0b300a1b-c6d6-4fff-9f4f-2a4142d011b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237645502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_intr_test.237645502
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2692398268
Short name T919
Test name
Test status
Simulation time 75893852 ps
CPU time 1.39 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 200544 kb
Host smart-1fd4c227-7212-4bb4-8a64-2be1faeba6ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692398268 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.2692398268
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1200696914
Short name T968
Test name
Test status
Simulation time 343004707 ps
CPU time 2.55 seconds
Started Aug 06 07:17:16 PM PDT 24
Finished Aug 06 07:17:19 PM PDT 24
Peak memory 208968 kb
Host smart-3d571362-64f5-4ee4-8ffa-c848eba8cfdd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200696914 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.1200696914
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1207471790
Short name T954
Test name
Test status
Simulation time 116017681 ps
CPU time 1.72 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:19 PM PDT 24
Peak memory 217200 kb
Host smart-edea75f3-7125-42e5-86e1-c10615904e3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207471790 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1207471790
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2465427
Short name T858
Test name
Test status
Simulation time 703642851 ps
CPU time 5.39 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:34 PM PDT 24
Peak memory 200588 kb
Host smart-81358fd1-2d46-475a-bd69-0754edf36e12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=
clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmg
r_tl_errors.2465427
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.852277388
Short name T101
Test name
Test status
Simulation time 67340165 ps
CPU time 1.72 seconds
Started Aug 06 07:17:25 PM PDT 24
Finished Aug 06 07:17:27 PM PDT 24
Peak memory 200652 kb
Host smart-09ac8662-91d6-4765-92c6-7f04d69520a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852277388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.clkmgr_tl_intg_err.852277388
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1601188250
Short name T896
Test name
Test status
Simulation time 33100106 ps
CPU time 0.99 seconds
Started Aug 06 07:17:26 PM PDT 24
Finished Aug 06 07:17:27 PM PDT 24
Peak memory 200436 kb
Host smart-26a234c1-3349-422d-8efb-827189e38635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601188250 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.1601188250
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.713966828
Short name T865
Test name
Test status
Simulation time 55837078 ps
CPU time 0.94 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 200364 kb
Host smart-49499130-f08f-4128-bbc2-0e069d720258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713966828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
clkmgr_csr_rw.713966828
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2621640671
Short name T833
Test name
Test status
Simulation time 31335177 ps
CPU time 0.69 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 199076 kb
Host smart-38fa98d6-1d0a-4564-a6f2-b6e48ede8c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621640671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.2621640671
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2629614176
Short name T76
Test name
Test status
Simulation time 42271762 ps
CPU time 1.05 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 200440 kb
Host smart-70b16716-1d6c-43c1-b9c5-1b6586a3f8c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629614176 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.2629614176
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2677114849
Short name T949
Test name
Test status
Simulation time 91197996 ps
CPU time 1.76 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 217192 kb
Host smart-72bce7c6-0035-4b73-b577-768d52d3309a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677114849 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.2677114849
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.821616047
Short name T849
Test name
Test status
Simulation time 104238414 ps
CPU time 3.14 seconds
Started Aug 06 07:17:25 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 200524 kb
Host smart-b976d5bf-a655-42ff-812a-72f630530f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821616047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk
mgr_tl_errors.821616047
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.46260406
Short name T962
Test name
Test status
Simulation time 156506322 ps
CPU time 1.88 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 200640 kb
Host smart-49a12fd7-11a2-4d91-a444-d249bed237ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46260406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.clkmgr_tl_intg_err.46260406
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3116074161
Short name T916
Test name
Test status
Simulation time 58442662 ps
CPU time 1.09 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 200488 kb
Host smart-52a7f38e-59c3-44e1-9086-cbd16d821d35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116074161 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.3116074161
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2353197794
Short name T914
Test name
Test status
Simulation time 19019059 ps
CPU time 0.83 seconds
Started Aug 06 07:17:26 PM PDT 24
Finished Aug 06 07:17:27 PM PDT 24
Peak memory 200396 kb
Host smart-6b1784fa-8de1-4187-974c-5494936ddc4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353197794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.2353197794
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.493774727
Short name T894
Test name
Test status
Simulation time 17486972 ps
CPU time 0.64 seconds
Started Aug 06 07:17:24 PM PDT 24
Finished Aug 06 07:17:24 PM PDT 24
Peak memory 198992 kb
Host smart-1e5ef6a5-0e93-4cba-9311-16b636218316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493774727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk
mgr_intr_test.493774727
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3810364812
Short name T930
Test name
Test status
Simulation time 797739335 ps
CPU time 3 seconds
Started Aug 06 07:17:25 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 200628 kb
Host smart-e8e064d8-2eb7-4ce4-ae71-38ccdc78c9d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810364812 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.3810364812
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.4212439174
Short name T64
Test name
Test status
Simulation time 164251971 ps
CPU time 1.61 seconds
Started Aug 06 07:17:33 PM PDT 24
Finished Aug 06 07:17:35 PM PDT 24
Peak memory 200668 kb
Host smart-34a03b86-ba47-4055-b178-23725d845f01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212439174 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.4212439174
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1088838911
Short name T126
Test name
Test status
Simulation time 236074217 ps
CPU time 2.97 seconds
Started Aug 06 07:17:26 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 201032 kb
Host smart-97dfc48a-303b-4648-826e-74e2a3d002c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088838911 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.1088838911
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.59360126
Short name T830
Test name
Test status
Simulation time 46701618 ps
CPU time 2.72 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 200560 kb
Host smart-63189d10-3ff1-4900-adce-49d9d2201fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59360126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkm
gr_tl_errors.59360126
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.268216892
Short name T940
Test name
Test status
Simulation time 436844861 ps
CPU time 3.4 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 200624 kb
Host smart-9546bb63-c5ef-42cc-9f60-89c2bd4c9ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268216892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.clkmgr_tl_intg_err.268216892
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.1877487073
Short name T904
Test name
Test status
Simulation time 123536157 ps
CPU time 1.57 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 200536 kb
Host smart-3971bee1-483e-42ea-bb71-ea9dcccca50f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877487073 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.1877487073
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1179038596
Short name T937
Test name
Test status
Simulation time 33709695 ps
CPU time 0.89 seconds
Started Aug 06 07:17:26 PM PDT 24
Finished Aug 06 07:17:27 PM PDT 24
Peak memory 200296 kb
Host smart-b02de50b-3ba4-4cfd-9995-33bd6b11861e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179038596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.1179038596
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2913001077
Short name T850
Test name
Test status
Simulation time 14307711 ps
CPU time 0.68 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 199016 kb
Host smart-4e5abd43-186a-4c22-9b7d-abade5239538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913001077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2913001077
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.4205034979
Short name T80
Test name
Test status
Simulation time 31055951 ps
CPU time 0.95 seconds
Started Aug 06 07:17:25 PM PDT 24
Finished Aug 06 07:17:26 PM PDT 24
Peak memory 200348 kb
Host smart-89696916-6ed0-4a15-9680-5cc56ba0c343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205034979 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.4205034979
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.96564018
Short name T974
Test name
Test status
Simulation time 275893455 ps
CPU time 1.53 seconds
Started Aug 06 07:17:26 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 200672 kb
Host smart-0c6579c9-eb1a-4789-8162-4f2fb418c933
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96564018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.clkmgr_shadow_reg_errors.96564018
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.739472037
Short name T139
Test name
Test status
Simulation time 147194350 ps
CPU time 3.02 seconds
Started Aug 06 07:17:24 PM PDT 24
Finished Aug 06 07:17:27 PM PDT 24
Peak memory 201116 kb
Host smart-d56d3fd5-a753-4f2f-be4a-8c0fd5c9d1bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739472037 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.739472037
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2019612801
Short name T961
Test name
Test status
Simulation time 92796174 ps
CPU time 1.69 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 199944 kb
Host smart-56bdc166-dc54-4cc4-9777-51eb1d94ceb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019612801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.2019612801
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2717972314
Short name T100
Test name
Test status
Simulation time 244456828 ps
CPU time 2.62 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:33 PM PDT 24
Peak memory 200596 kb
Host smart-d3a7c203-e4e4-4f9e-834d-4cc3927f88b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717972314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.2717972314
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1638996055
Short name T837
Test name
Test status
Simulation time 114146784 ps
CPU time 1.12 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 199928 kb
Host smart-b7ea12a8-2509-404c-a0a6-90b98dce5a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638996055 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.1638996055
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3892132468
Short name T932
Test name
Test status
Simulation time 37677844 ps
CPU time 0.82 seconds
Started Aug 06 07:17:33 PM PDT 24
Finished Aug 06 07:17:34 PM PDT 24
Peak memory 200400 kb
Host smart-2e4cd328-1bb4-493a-9466-5f225d489e7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892132468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.3892132468
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1597294992
Short name T928
Test name
Test status
Simulation time 12715011 ps
CPU time 0.68 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 199004 kb
Host smart-78341611-c6fd-4d4d-9287-477df7097135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597294992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.1597294992
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3086319352
Short name T855
Test name
Test status
Simulation time 51793714 ps
CPU time 1.38 seconds
Started Aug 06 07:17:26 PM PDT 24
Finished Aug 06 07:17:27 PM PDT 24
Peak memory 200612 kb
Host smart-45ac7f7b-4ed7-4d1e-a8d8-312ee8284b52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086319352 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.3086319352
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.234820566
Short name T135
Test name
Test status
Simulation time 1366074422 ps
CPU time 4.75 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:32 PM PDT 24
Peak memory 217212 kb
Host smart-5d00cbb0-3809-46ed-be97-7f1e3a40fc6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234820566 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.clkmgr_shadow_reg_errors.234820566
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3798223698
Short name T63
Test name
Test status
Simulation time 93630128 ps
CPU time 2.42 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 209064 kb
Host smart-36d5aca4-38ba-4db5-aa17-d8aaf67d0611
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798223698 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.3798223698
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.850563661
Short name T884
Test name
Test status
Simulation time 41913687 ps
CPU time 2.51 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:33 PM PDT 24
Peak memory 200524 kb
Host smart-4225c03a-6699-4d04-aa6d-805a9360e5e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850563661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk
mgr_tl_errors.850563661
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3045774055
Short name T190
Test name
Test status
Simulation time 133111726 ps
CPU time 1.88 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 200612 kb
Host smart-ca8fc07a-5659-406b-b669-81f961f77378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045774055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.3045774055
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3665750830
Short name T874
Test name
Test status
Simulation time 46181562 ps
CPU time 1.54 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 200692 kb
Host smart-822f31ac-9bac-4f78-a37e-9ba8cee1e40f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665750830 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3665750830
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.4113383879
Short name T978
Test name
Test status
Simulation time 16057878 ps
CPU time 0.78 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 200268 kb
Host smart-650283e1-13ef-4e33-b131-5b2125024d35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113383879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.4113383879
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.272165293
Short name T909
Test name
Test status
Simulation time 62370877 ps
CPU time 0.78 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 199032 kb
Host smart-d12191f9-e445-4d04-b6ee-0b5f9de17e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272165293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk
mgr_intr_test.272165293
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2165509193
Short name T859
Test name
Test status
Simulation time 126296323 ps
CPU time 1.58 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 200544 kb
Host smart-6a35d118-b8c8-42ea-ba7a-7e1b3b54a90c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165509193 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.2165509193
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.300008146
Short name T66
Test name
Test status
Simulation time 185253170 ps
CPU time 2.02 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 216532 kb
Host smart-b475974a-3311-423e-994d-e7549da1475d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300008146 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.clkmgr_shadow_reg_errors.300008146
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.739639046
Short name T60
Test name
Test status
Simulation time 109639307 ps
CPU time 1.85 seconds
Started Aug 06 07:17:26 PM PDT 24
Finished Aug 06 07:17:28 PM PDT 24
Peak memory 217204 kb
Host smart-c3de9c0b-2f39-4a3f-bbd7-c6c31567cff9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739639046 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.739639046
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.873442551
Short name T927
Test name
Test status
Simulation time 96056310 ps
CPU time 2.97 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 200556 kb
Host smart-5f41b092-ddb1-4291-8470-b2d874da4e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873442551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk
mgr_tl_errors.873442551
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1126177017
Short name T191
Test name
Test status
Simulation time 194700610 ps
CPU time 2.67 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 200160 kb
Host smart-b2391c34-48b9-4bfc-bf93-a4754114ae0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126177017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.1126177017
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2382268153
Short name T889
Test name
Test status
Simulation time 44470014 ps
CPU time 1.49 seconds
Started Aug 06 07:17:32 PM PDT 24
Finished Aug 06 07:17:34 PM PDT 24
Peak memory 200524 kb
Host smart-2d37317e-e78d-4089-a8f3-982902df7bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382268153 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.2382268153
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.791412491
Short name T107
Test name
Test status
Simulation time 39882670 ps
CPU time 0.82 seconds
Started Aug 06 07:17:32 PM PDT 24
Finished Aug 06 07:17:33 PM PDT 24
Peak memory 200260 kb
Host smart-2d716fbe-7857-4d52-bc09-89642b710586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791412491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
clkmgr_csr_rw.791412491
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2234493484
Short name T912
Test name
Test status
Simulation time 34271885 ps
CPU time 0.72 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 199112 kb
Host smart-dcc17213-5844-479c-946b-1fee4736dca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234493484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.2234493484
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1665691115
Short name T945
Test name
Test status
Simulation time 93523361 ps
CPU time 1.18 seconds
Started Aug 06 07:17:32 PM PDT 24
Finished Aug 06 07:17:33 PM PDT 24
Peak memory 200292 kb
Host smart-dddd7770-6171-426e-a163-4575f456751a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665691115 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.1665691115
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3246793830
Short name T125
Test name
Test status
Simulation time 110214646 ps
CPU time 1.9 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 208976 kb
Host smart-112b7916-b4d2-400f-b4c5-84d267f09a18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246793830 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.3246793830
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2133948555
Short name T958
Test name
Test status
Simulation time 86992542 ps
CPU time 1.76 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 209076 kb
Host smart-778579eb-267f-4b8d-b22d-29d7b4472cb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133948555 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.2133948555
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1470363849
Short name T946
Test name
Test status
Simulation time 35076556 ps
CPU time 2.13 seconds
Started Aug 06 07:17:25 PM PDT 24
Finished Aug 06 07:17:27 PM PDT 24
Peak memory 200564 kb
Host smart-79193706-d8e3-4443-9ca2-e4db9e21c482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470363849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.1470363849
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3278505042
Short name T966
Test name
Test status
Simulation time 116254525 ps
CPU time 1.65 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 200600 kb
Host smart-8d243aa0-2275-4f11-b1d5-12ba08e060ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278505042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.3278505042
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.4022680812
Short name T835
Test name
Test status
Simulation time 23535854 ps
CPU time 0.96 seconds
Started Aug 06 07:17:27 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 200428 kb
Host smart-3bb846af-d55b-44ed-9b71-67fe3f921336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022680812 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.4022680812
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.479069575
Short name T960
Test name
Test status
Simulation time 39506476 ps
CPU time 0.84 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 200304 kb
Host smart-a2e0f1ec-40e0-4e3c-861d-25fb9a4773d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479069575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
clkmgr_csr_rw.479069575
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.1560021315
Short name T853
Test name
Test status
Simulation time 26296103 ps
CPU time 0.69 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 198996 kb
Host smart-2c852dbb-937c-45b5-b7dc-b209fc1b92d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560021315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.1560021315
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3688469995
Short name T78
Test name
Test status
Simulation time 235744759 ps
CPU time 1.58 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 200364 kb
Host smart-e04c1f0b-784c-4446-8a72-741cdd28001a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688469995 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.3688469995
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2952532375
Short name T124
Test name
Test status
Simulation time 120386430 ps
CPU time 1.74 seconds
Started Aug 06 07:17:31 PM PDT 24
Finished Aug 06 07:17:32 PM PDT 24
Peak memory 200864 kb
Host smart-ce52f7a3-cca7-4f35-9cce-dc3d76527a61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952532375 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.2952532375
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2683107140
Short name T130
Test name
Test status
Simulation time 54588019 ps
CPU time 1.56 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 200876 kb
Host smart-eb1159ce-dc92-47db-9824-1eff84ef8e85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683107140 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2683107140
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.327155370
Short name T929
Test name
Test status
Simulation time 118482074 ps
CPU time 2.89 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:32 PM PDT 24
Peak memory 200612 kb
Host smart-08200fdd-8000-4445-8e9b-44cdca4810ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327155370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_tl_errors.327155370
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1186476674
Short name T934
Test name
Test status
Simulation time 62682606 ps
CPU time 1.72 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 200628 kb
Host smart-711ac0e2-3999-49d7-94ba-a44ed45501e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186476674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.1186476674
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2541255905
Short name T851
Test name
Test status
Simulation time 345813510 ps
CPU time 3.99 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 200572 kb
Host smart-f09d4b07-b3a3-4826-ad7e-948a0ab68cf7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541255905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.2541255905
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3116510105
Short name T861
Test name
Test status
Simulation time 48434004 ps
CPU time 0.84 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 200368 kb
Host smart-99d4f846-9873-437d-836e-60e135fecc06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116510105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.3116510105
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3955528560
Short name T883
Test name
Test status
Simulation time 29874439 ps
CPU time 1.06 seconds
Started Aug 06 07:16:55 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 200448 kb
Host smart-c7f72f7c-ab06-4634-9ced-8206db13b0e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955528560 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.3955528560
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1014816120
Short name T854
Test name
Test status
Simulation time 46428896 ps
CPU time 0.84 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:52 PM PDT 24
Peak memory 200212 kb
Host smart-d783f440-5ab7-4fa0-bca4-be8104821ae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014816120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.1014816120
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.2953682406
Short name T890
Test name
Test status
Simulation time 65960418 ps
CPU time 0.79 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 199028 kb
Host smart-7ae0fc04-6935-47b2-b8ab-84af1c233faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953682406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.2953682406
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1997598464
Short name T863
Test name
Test status
Simulation time 120136081 ps
CPU time 1.29 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 200352 kb
Host smart-31637a59-5ba3-4024-92e6-063019dfa0c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997598464 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.1997598464
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2744986342
Short name T970
Test name
Test status
Simulation time 49043266 ps
CPU time 1.22 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 200636 kb
Host smart-8789cc0f-3a0a-44e5-bb33-7d0a1029a26c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744986342 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.2744986342
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2488960029
Short name T62
Test name
Test status
Simulation time 367169939 ps
CPU time 3.64 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 201156 kb
Host smart-52b68b83-4f62-48eb-8154-cd67fd2aa536
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488960029 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.2488960029
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3712310745
Short name T873
Test name
Test status
Simulation time 71450499 ps
CPU time 2.23 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 200512 kb
Host smart-09afd9a1-6b0f-4482-8bf6-808d7b08081d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712310745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.3712310745
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3643982377
Short name T941
Test name
Test status
Simulation time 122231184 ps
CPU time 2.72 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 200588 kb
Host smart-72b353d7-27dd-4090-8f95-b511783b9ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643982377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3643982377
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2590225362
Short name T869
Test name
Test status
Simulation time 31577297 ps
CPU time 0.69 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 198952 kb
Host smart-a45ce545-4e12-4394-b3e9-7f31c814cf3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590225362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.2590225362
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3150171463
Short name T843
Test name
Test status
Simulation time 12700482 ps
CPU time 0.64 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 198980 kb
Host smart-f1d6b085-43db-4c4c-be11-9f0872226060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150171463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.3150171463
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1928202912
Short name T881
Test name
Test status
Simulation time 22170946 ps
CPU time 0.69 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 198984 kb
Host smart-deb74d9c-d5cb-4ffe-b12f-852da472a211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928202912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.1928202912
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2748203649
Short name T943
Test name
Test status
Simulation time 11134520 ps
CPU time 0.69 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 198996 kb
Host smart-eda19e7e-60d9-4155-b62f-2e61f51ea070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748203649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.2748203649
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1627206991
Short name T948
Test name
Test status
Simulation time 13811312 ps
CPU time 0.73 seconds
Started Aug 06 07:17:32 PM PDT 24
Finished Aug 06 07:17:33 PM PDT 24
Peak memory 198920 kb
Host smart-3feade39-0284-494e-9d4f-339fc8e9c075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627206991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.1627206991
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2461120358
Short name T920
Test name
Test status
Simulation time 14125923 ps
CPU time 0.69 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 198900 kb
Host smart-30a7a2d6-5ebb-4ae7-9077-86f13efa90fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461120358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.2461120358
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3994844432
Short name T879
Test name
Test status
Simulation time 19980036 ps
CPU time 0.68 seconds
Started Aug 06 07:17:28 PM PDT 24
Finished Aug 06 07:17:29 PM PDT 24
Peak memory 198996 kb
Host smart-4f08163a-f859-47c3-8971-17b37c1f2ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994844432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.3994844432
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3205672670
Short name T862
Test name
Test status
Simulation time 12155911 ps
CPU time 0.67 seconds
Started Aug 06 07:17:29 PM PDT 24
Finished Aug 06 07:17:30 PM PDT 24
Peak memory 198900 kb
Host smart-c4187a5e-5635-40bd-ac8e-4998855413bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205672670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.3205672670
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.266098750
Short name T882
Test name
Test status
Simulation time 14905166 ps
CPU time 0.69 seconds
Started Aug 06 07:17:31 PM PDT 24
Finished Aug 06 07:17:32 PM PDT 24
Peak memory 198864 kb
Host smart-f8222f5a-fcd8-40d8-bd54-4a82dba92fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266098750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk
mgr_intr_test.266098750
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3723147593
Short name T947
Test name
Test status
Simulation time 15700950 ps
CPU time 0.69 seconds
Started Aug 06 07:17:30 PM PDT 24
Finished Aug 06 07:17:31 PM PDT 24
Peak memory 198984 kb
Host smart-14c7ba03-b91a-4015-a202-7e4e61aacc4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723147593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.3723147593
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3383359451
Short name T944
Test name
Test status
Simulation time 65438948 ps
CPU time 1.15 seconds
Started Aug 06 07:16:54 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 200352 kb
Host smart-ac541d6f-222b-43f9-af32-0926a8b9eb8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383359451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.3383359451
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2808919132
Short name T972
Test name
Test status
Simulation time 313210775 ps
CPU time 3.96 seconds
Started Aug 06 07:16:58 PM PDT 24
Finished Aug 06 07:17:02 PM PDT 24
Peak memory 200536 kb
Host smart-a8329869-f455-4d66-96b1-873a8cb2f7ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808919132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.2808919132
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2890714880
Short name T866
Test name
Test status
Simulation time 74417435 ps
CPU time 0.96 seconds
Started Aug 06 07:16:54 PM PDT 24
Finished Aug 06 07:16:55 PM PDT 24
Peak memory 200444 kb
Host smart-e016eae7-00b3-49b6-8834-cacb691341d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890714880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.2890714880
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1875677170
Short name T846
Test name
Test status
Simulation time 120318106 ps
CPU time 2.05 seconds
Started Aug 06 07:16:58 PM PDT 24
Finished Aug 06 07:17:00 PM PDT 24
Peak memory 208900 kb
Host smart-7625c163-3abf-4792-920f-159a9415eb83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875677170 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.1875677170
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.297078362
Short name T915
Test name
Test status
Simulation time 21218331 ps
CPU time 0.86 seconds
Started Aug 06 07:16:59 PM PDT 24
Finished Aug 06 07:17:00 PM PDT 24
Peak memory 200412 kb
Host smart-9e66cb00-4c52-4d29-9129-96b39fa5c0e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297078362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.c
lkmgr_csr_rw.297078362
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1907838607
Short name T895
Test name
Test status
Simulation time 69191852 ps
CPU time 0.79 seconds
Started Aug 06 07:16:55 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 199048 kb
Host smart-0fa168ef-7a83-4205-a676-4bbf740ca5bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907838607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.1907838607
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1277458129
Short name T977
Test name
Test status
Simulation time 87721987 ps
CPU time 1.15 seconds
Started Aug 06 07:16:59 PM PDT 24
Finished Aug 06 07:17:00 PM PDT 24
Peak memory 200404 kb
Host smart-8381ea1d-c412-4f05-bc68-e5a6b94f264b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277458129 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.1277458129
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3461358878
Short name T123
Test name
Test status
Simulation time 263744554 ps
CPU time 2.06 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 217132 kb
Host smart-97455046-9db2-4276-841d-9f27225e9f9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461358878 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.3461358878
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.4080948658
Short name T951
Test name
Test status
Simulation time 627485011 ps
CPU time 3.83 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 200592 kb
Host smart-089b7ff9-da17-4318-8bef-fd42dfa6283d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080948658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.4080948658
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1151255682
Short name T102
Test name
Test status
Simulation time 107663629 ps
CPU time 1.78 seconds
Started Aug 06 07:16:55 PM PDT 24
Finished Aug 06 07:16:57 PM PDT 24
Peak memory 200632 kb
Host smart-57ce4b41-cd6c-43a1-8120-e48910619ef3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151255682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.1151255682
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3631705240
Short name T847
Test name
Test status
Simulation time 21953236 ps
CPU time 0.7 seconds
Started Aug 06 07:17:31 PM PDT 24
Finished Aug 06 07:17:32 PM PDT 24
Peak memory 198852 kb
Host smart-be1828d2-fe21-4719-990d-36b5cb8cddb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631705240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.3631705240
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2331629939
Short name T918
Test name
Test status
Simulation time 13924385 ps
CPU time 0.74 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 199032 kb
Host smart-4de0ab8a-6600-4e62-a904-7b225eef9e69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331629939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.2331629939
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.476275336
Short name T942
Test name
Test status
Simulation time 18280094 ps
CPU time 0.67 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:46 PM PDT 24
Peak memory 198968 kb
Host smart-6a93be3f-3c55-4475-b571-a6e8f9ef304e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476275336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clk
mgr_intr_test.476275336
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1221342130
Short name T848
Test name
Test status
Simulation time 20984986 ps
CPU time 0.74 seconds
Started Aug 06 07:17:49 PM PDT 24
Finished Aug 06 07:17:50 PM PDT 24
Peak memory 199080 kb
Host smart-6a55b412-f92f-4eea-848f-ce792a7498e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221342130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.1221342130
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.249305269
Short name T902
Test name
Test status
Simulation time 88338833 ps
CPU time 0.84 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 198984 kb
Host smart-a7248517-b729-40a2-b667-e4e62c3a7800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249305269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk
mgr_intr_test.249305269
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3613875616
Short name T955
Test name
Test status
Simulation time 13412975 ps
CPU time 0.68 seconds
Started Aug 06 07:17:48 PM PDT 24
Finished Aug 06 07:17:48 PM PDT 24
Peak memory 199060 kb
Host smart-4e8dd3cc-4e2b-41b7-81be-37b0ae148399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613875616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.3613875616
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.2588329118
Short name T957
Test name
Test status
Simulation time 15624721 ps
CPU time 0.71 seconds
Started Aug 06 07:17:45 PM PDT 24
Finished Aug 06 07:17:46 PM PDT 24
Peak memory 199028 kb
Host smart-48706459-4807-4bc3-8452-1b7ff3c8e944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588329118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.2588329118
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.62575605
Short name T852
Test name
Test status
Simulation time 18029925 ps
CPU time 0.69 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 199072 kb
Host smart-4da9ed83-12ae-4c3e-bd87-93ec39c19347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62575605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkm
gr_intr_test.62575605
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2452286143
Short name T973
Test name
Test status
Simulation time 38271250 ps
CPU time 0.71 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 199040 kb
Host smart-c13fb33e-6ede-4edb-8db1-c3ad9c94590b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452286143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.2452286143
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3613453223
Short name T891
Test name
Test status
Simulation time 37024149 ps
CPU time 0.74 seconds
Started Aug 06 07:17:49 PM PDT 24
Finished Aug 06 07:17:50 PM PDT 24
Peak memory 199060 kb
Host smart-937dcad6-a60e-4e8d-bc98-f434a47efaf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613453223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.3613453223
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1544167050
Short name T171
Test name
Test status
Simulation time 50255183 ps
CPU time 1.32 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:16:51 PM PDT 24
Peak memory 200320 kb
Host smart-71cabccf-f3a1-4381-947f-4f6d9adab00f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544167050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.1544167050
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1048409135
Short name T893
Test name
Test status
Simulation time 707523266 ps
CPU time 7.31 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:58 PM PDT 24
Peak memory 200440 kb
Host smart-21dac096-2c56-47dd-8001-769107da87f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048409135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.1048409135
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.620260082
Short name T910
Test name
Test status
Simulation time 218680703 ps
CPU time 1.32 seconds
Started Aug 06 07:16:49 PM PDT 24
Finished Aug 06 07:16:50 PM PDT 24
Peak memory 200392 kb
Host smart-8cc3d583-1046-46dc-9b2f-ddaab8c6f501
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620260082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_hw_reset.620260082
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.4102639226
Short name T856
Test name
Test status
Simulation time 26753429 ps
CPU time 1.37 seconds
Started Aug 06 07:16:52 PM PDT 24
Finished Aug 06 07:16:53 PM PDT 24
Peak memory 200560 kb
Host smart-f2f31777-29a3-41b3-ba97-1d690bf61454
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102639226 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.4102639226
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3297250932
Short name T933
Test name
Test status
Simulation time 116445803 ps
CPU time 1.01 seconds
Started Aug 06 07:16:53 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 200280 kb
Host smart-6c79756f-04d9-4a89-8ea5-b1c87ed24639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297250932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3297250932
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2475569990
Short name T971
Test name
Test status
Simulation time 15597159 ps
CPU time 0.76 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:52 PM PDT 24
Peak memory 198992 kb
Host smart-ccd9dd60-5eb7-4518-ac62-0fbe29f9bf37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475569990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.2475569990
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3603952466
Short name T917
Test name
Test status
Simulation time 189260088 ps
CPU time 1.85 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:16:52 PM PDT 24
Peak memory 200504 kb
Host smart-97d04403-4002-461e-a1aa-4380bd1746bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603952466 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.3603952466
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2511279611
Short name T65
Test name
Test status
Simulation time 163433506 ps
CPU time 1.65 seconds
Started Aug 06 07:16:55 PM PDT 24
Finished Aug 06 07:16:57 PM PDT 24
Peak memory 200644 kb
Host smart-d70cc854-57bc-4a25-95a7-06b7c6494fa7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511279611 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.2511279611
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2666557138
Short name T133
Test name
Test status
Simulation time 150695936 ps
CPU time 1.77 seconds
Started Aug 06 07:16:58 PM PDT 24
Finished Aug 06 07:17:00 PM PDT 24
Peak memory 209084 kb
Host smart-7d9ceb34-30b2-4e45-9e24-197ae97b30c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666557138 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.2666557138
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2830647365
Short name T952
Test name
Test status
Simulation time 270697383 ps
CPU time 2.8 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 200580 kb
Host smart-cd22a62d-4068-42bf-84f4-809c1dbc2f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830647365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.2830647365
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3311563697
Short name T950
Test name
Test status
Simulation time 128796061 ps
CPU time 3.01 seconds
Started Aug 06 07:16:50 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 200624 kb
Host smart-b4eb65e4-bd3f-4205-98a0-0327dc0b05ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311563697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.3311563697
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1111641551
Short name T907
Test name
Test status
Simulation time 13891371 ps
CPU time 0.7 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 199008 kb
Host smart-19df3b9c-8419-4252-a347-fa484d42faa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111641551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.1111641551
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.3619137106
Short name T870
Test name
Test status
Simulation time 21235530 ps
CPU time 0.68 seconds
Started Aug 06 07:17:44 PM PDT 24
Finished Aug 06 07:17:45 PM PDT 24
Peak memory 198956 kb
Host smart-86d65d37-fdc0-47b3-b9dd-973020ade619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619137106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.3619137106
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1612724794
Short name T878
Test name
Test status
Simulation time 36469027 ps
CPU time 0.74 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 199036 kb
Host smart-c1d6a8e8-b942-426e-9194-7268675f8bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612724794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.1612724794
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3760541355
Short name T926
Test name
Test status
Simulation time 72587720 ps
CPU time 0.8 seconds
Started Aug 06 07:17:47 PM PDT 24
Finished Aug 06 07:17:48 PM PDT 24
Peak memory 198976 kb
Host smart-61177501-11ed-4db8-98f4-61bb958cc18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760541355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.3760541355
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2099104610
Short name T913
Test name
Test status
Simulation time 28243003 ps
CPU time 0.7 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 198980 kb
Host smart-b6dea7f9-4d5b-48fa-8592-7f59341bef90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099104610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.2099104610
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4115249105
Short name T834
Test name
Test status
Simulation time 11437727 ps
CPU time 0.67 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 198964 kb
Host smart-e52b9d8a-7f6b-4bdd-96b3-22a0061a65e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115249105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.4115249105
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.46499263
Short name T922
Test name
Test status
Simulation time 30386053 ps
CPU time 0.7 seconds
Started Aug 06 07:17:47 PM PDT 24
Finished Aug 06 07:17:48 PM PDT 24
Peak memory 198992 kb
Host smart-ed6661e2-7b64-4f3d-90f7-cfbd977c5ce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46499263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkm
gr_intr_test.46499263
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3200788742
Short name T924
Test name
Test status
Simulation time 13618663 ps
CPU time 0.75 seconds
Started Aug 06 07:17:47 PM PDT 24
Finished Aug 06 07:17:48 PM PDT 24
Peak memory 198996 kb
Host smart-f7233d0b-a897-4a2c-b244-8d229c5cfda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200788742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.3200788742
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.301017238
Short name T953
Test name
Test status
Simulation time 14687577 ps
CPU time 0.69 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:47 PM PDT 24
Peak memory 198988 kb
Host smart-74a14d3a-bb2f-455a-b07e-a61cad413f0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301017238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clk
mgr_intr_test.301017238
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.3845005697
Short name T832
Test name
Test status
Simulation time 20049074 ps
CPU time 0.69 seconds
Started Aug 06 07:17:46 PM PDT 24
Finished Aug 06 07:17:46 PM PDT 24
Peak memory 198976 kb
Host smart-601d9045-f4c4-47de-a41f-0da7b87571d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845005697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.3845005697
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1779081900
Short name T872
Test name
Test status
Simulation time 62819756 ps
CPU time 1.17 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:18 PM PDT 24
Peak memory 200484 kb
Host smart-f40955d8-ca38-4145-9ed8-202d7a0c4f2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779081900 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1779081900
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3954597607
Short name T844
Test name
Test status
Simulation time 59054383 ps
CPU time 0.91 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 200372 kb
Host smart-01e29419-6fac-4fae-b220-7fee5221bb61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954597607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.3954597607
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2501336703
Short name T840
Test name
Test status
Simulation time 27154711 ps
CPU time 0.66 seconds
Started Aug 06 07:17:08 PM PDT 24
Finished Aug 06 07:17:09 PM PDT 24
Peak memory 199040 kb
Host smart-8274c8fb-c966-4361-a69a-22781cac1eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501336703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.2501336703
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1953813527
Short name T868
Test name
Test status
Simulation time 66872111 ps
CPU time 1.18 seconds
Started Aug 06 07:17:04 PM PDT 24
Finished Aug 06 07:17:05 PM PDT 24
Peak memory 200388 kb
Host smart-fce406c1-f1fb-49a1-a69b-641aaf36e093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953813527 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.1953813527
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.4311987
Short name T129
Test name
Test status
Simulation time 488249692 ps
CPU time 2.76 seconds
Started Aug 06 07:16:51 PM PDT 24
Finished Aug 06 07:16:54 PM PDT 24
Peak memory 209088 kb
Host smart-097e2b1f-26ae-403a-91a8-fdf1b1345545
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4311987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_t
est +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.clkmgr_shadow_reg_errors.4311987
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.254608671
Short name T128
Test name
Test status
Simulation time 246110993 ps
CPU time 2.43 seconds
Started Aug 06 07:16:54 PM PDT 24
Finished Aug 06 07:16:56 PM PDT 24
Peak memory 209108 kb
Host smart-7a6da278-cd5a-4009-aeb3-e8ca597c44fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254608671 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.254608671
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3042545445
Short name T906
Test name
Test status
Simulation time 24362475 ps
CPU time 1.58 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 200548 kb
Host smart-53c73193-d47a-400a-b843-f718fb5d17e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042545445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.3042545445
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2759236317
Short name T976
Test name
Test status
Simulation time 67685868 ps
CPU time 1.03 seconds
Started Aug 06 07:17:04 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 200392 kb
Host smart-5c10ee3e-8dc6-4122-830f-b0be38ad04b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759236317 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2759236317
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.898457804
Short name T886
Test name
Test status
Simulation time 17798852 ps
CPU time 0.77 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:18 PM PDT 24
Peak memory 200316 kb
Host smart-fbeb6383-c031-4931-8849-a76eacfee286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898457804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.c
lkmgr_csr_rw.898457804
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3444910944
Short name T899
Test name
Test status
Simulation time 12167401 ps
CPU time 0.7 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:05 PM PDT 24
Peak memory 199008 kb
Host smart-c067367b-9259-4c15-b8bc-c00aea85c653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444910944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3444910944
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1763261541
Short name T911
Test name
Test status
Simulation time 70468985 ps
CPU time 1.29 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 200852 kb
Host smart-16d2a678-8a53-4a86-8b75-43065dabbb06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763261541 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.1763261541
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.220445607
Short name T141
Test name
Test status
Simulation time 201726203 ps
CPU time 1.73 seconds
Started Aug 06 07:17:04 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 200560 kb
Host smart-17b06534-f7f8-4f3e-95c9-3f4a9d8c4de1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220445607 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.clkmgr_shadow_reg_errors.220445607
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.656449311
Short name T122
Test name
Test status
Simulation time 105182685 ps
CPU time 1.67 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 216952 kb
Host smart-b3448447-c0a9-4c68-834e-d58bbaafc2cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656449311 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.656449311
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3072824876
Short name T841
Test name
Test status
Simulation time 73600716 ps
CPU time 2.57 seconds
Started Aug 06 07:17:08 PM PDT 24
Finished Aug 06 07:17:10 PM PDT 24
Peak memory 200572 kb
Host smart-10f48bd4-63ba-4a5f-960f-db936e488a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072824876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.3072824876
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3504045355
Short name T104
Test name
Test status
Simulation time 186153566 ps
CPU time 2.86 seconds
Started Aug 06 07:17:04 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 200596 kb
Host smart-349999e0-275c-4aff-9b47-6265b2a66ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504045355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.3504045355
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1960008259
Short name T936
Test name
Test status
Simulation time 38966798 ps
CPU time 1.28 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:18 PM PDT 24
Peak memory 200488 kb
Host smart-88df4bd0-ad2a-41ba-92c8-f59e3c815ff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960008259 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1960008259
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.909761138
Short name T77
Test name
Test status
Simulation time 17371407 ps
CPU time 0.82 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 199576 kb
Host smart-0f94bb96-7e9b-4cbb-a3c1-1cfa2f05044e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909761138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.c
lkmgr_csr_rw.909761138
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1223303068
Short name T875
Test name
Test status
Simulation time 12575813 ps
CPU time 0.7 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 198992 kb
Host smart-d320c86a-5e50-4ef8-946b-b148c747a108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223303068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.1223303068
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3148000479
Short name T867
Test name
Test status
Simulation time 313974693 ps
CPU time 1.98 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:09 PM PDT 24
Peak memory 200552 kb
Host smart-bfbb30d9-c07b-471a-9233-081eb1a7a472
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148000479 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.3148000479
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2671928315
Short name T138
Test name
Test status
Simulation time 52789900 ps
CPU time 1.2 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 199808 kb
Host smart-4e75e1c7-803d-43b2-8119-1b783f88788d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671928315 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.2671928315
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.445747457
Short name T132
Test name
Test status
Simulation time 61612970 ps
CPU time 1.67 seconds
Started Aug 06 07:17:03 PM PDT 24
Finished Aug 06 07:17:05 PM PDT 24
Peak memory 200800 kb
Host smart-5a2e0ca7-da28-4ace-bd9b-1488ccb52b74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445747457 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.445747457
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.2507420122
Short name T173
Test name
Test status
Simulation time 41687328 ps
CPU time 1.39 seconds
Started Aug 06 07:17:07 PM PDT 24
Finished Aug 06 07:17:08 PM PDT 24
Peak memory 200416 kb
Host smart-4da1f558-92ee-4209-afaa-afd64a021d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507420122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.2507420122
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3690520631
Short name T110
Test name
Test status
Simulation time 60720603 ps
CPU time 1.55 seconds
Started Aug 06 07:17:04 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 200652 kb
Host smart-a31d80e3-9c4b-47bd-a35b-e99a3ec63a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690520631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.3690520631
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.393986947
Short name T876
Test name
Test status
Simulation time 23239132 ps
CPU time 1.3 seconds
Started Aug 06 07:17:03 PM PDT 24
Finished Aug 06 07:17:04 PM PDT 24
Peak memory 200460 kb
Host smart-edccc117-408b-4182-9745-d4ef19586482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393986947 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.393986947
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3903261003
Short name T880
Test name
Test status
Simulation time 30374073 ps
CPU time 0.92 seconds
Started Aug 06 07:17:07 PM PDT 24
Finished Aug 06 07:17:08 PM PDT 24
Peak memory 200408 kb
Host smart-7eed5bb8-db13-47f7-8485-34a63fbfff79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903261003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.3903261003
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2046054265
Short name T887
Test name
Test status
Simulation time 13392244 ps
CPU time 0.68 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:18 PM PDT 24
Peak memory 198876 kb
Host smart-c29bfec4-ee67-4f01-a58d-34dbea3682e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046054265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.2046054265
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2127513548
Short name T969
Test name
Test status
Simulation time 32689388 ps
CPU time 1.02 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 200456 kb
Host smart-bfea3e4c-b54f-42fa-8990-8efe7f526211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127513548 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.2127513548
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1741240383
Short name T131
Test name
Test status
Simulation time 100167631 ps
CPU time 1.92 seconds
Started Aug 06 07:17:07 PM PDT 24
Finished Aug 06 07:17:09 PM PDT 24
Peak memory 209076 kb
Host smart-b042d04c-1e0e-4761-9abb-8864e8f320f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741240383 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.1741240383
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.914018451
Short name T134
Test name
Test status
Simulation time 92164466 ps
CPU time 2.48 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:08 PM PDT 24
Peak memory 217296 kb
Host smart-b89a8844-6730-45d4-930e-a5771a93bc69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914018451 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.914018451
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3461229400
Short name T877
Test name
Test status
Simulation time 230902192 ps
CPU time 2.22 seconds
Started Aug 06 07:17:04 PM PDT 24
Finished Aug 06 07:17:06 PM PDT 24
Peak memory 200600 kb
Host smart-6b8c32a4-c88c-43c3-9964-e43379f69bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461229400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.3461229400
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1876417995
Short name T905
Test name
Test status
Simulation time 74055749 ps
CPU time 1.66 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:19 PM PDT 24
Peak memory 200584 kb
Host smart-7e71d0d3-ad0d-4089-ac4d-43e7b222f03c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876417995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.1876417995
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1536727133
Short name T839
Test name
Test status
Simulation time 24062343 ps
CPU time 1.21 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:18 PM PDT 24
Peak memory 200448 kb
Host smart-bf3c2f1e-13f0-42f7-b8da-4d1e4479f096
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536727133 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.1536727133
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3003691135
Short name T82
Test name
Test status
Simulation time 19914126 ps
CPU time 0.76 seconds
Started Aug 06 07:17:06 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 200416 kb
Host smart-bd6d61cc-194e-4b9b-8f48-3b58509372b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003691135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3003691135
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1726909120
Short name T885
Test name
Test status
Simulation time 80664578 ps
CPU time 0.81 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:19 PM PDT 24
Peak memory 199048 kb
Host smart-5485b89b-acec-4774-9090-d5a8f79b2acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726909120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.1726909120
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2503384667
Short name T901
Test name
Test status
Simulation time 49673369 ps
CPU time 1.28 seconds
Started Aug 06 07:17:18 PM PDT 24
Finished Aug 06 07:17:20 PM PDT 24
Peak memory 200388 kb
Host smart-1cd1e729-714f-4d10-b061-5280fd947d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503384667 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.2503384667
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.230380056
Short name T67
Test name
Test status
Simulation time 109748733 ps
CPU time 1.59 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:07 PM PDT 24
Peak memory 209052 kb
Host smart-56c75435-4c1a-45c2-a37f-7850a80942aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230380056 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.230380056
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3264205165
Short name T939
Test name
Test status
Simulation time 119477418 ps
CPU time 3.21 seconds
Started Aug 06 07:17:17 PM PDT 24
Finished Aug 06 07:17:20 PM PDT 24
Peak memory 200508 kb
Host smart-b17c2528-cbbf-4684-8e83-a65a08cf29c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264205165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.3264205165
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2044361243
Short name T108
Test name
Test status
Simulation time 133325538 ps
CPU time 2.89 seconds
Started Aug 06 07:17:05 PM PDT 24
Finished Aug 06 07:17:08 PM PDT 24
Peak memory 200568 kb
Host smart-e4129e10-405d-4254-babe-d1f33812acd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044361243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.2044361243
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.490059890
Short name T752
Test name
Test status
Simulation time 38626554 ps
CPU time 0.81 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 201152 kb
Host smart-1d30a7ab-6143-4994-ade2-efe5e51238b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490059890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_alert_test.490059890
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.105854539
Short name T711
Test name
Test status
Simulation time 19739227 ps
CPU time 0.87 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 201068 kb
Host smart-810be4fd-e0b4-4786-b425-bae9e961b14c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105854539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.105854539
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.2793701712
Short name T611
Test name
Test status
Simulation time 33951727 ps
CPU time 0.75 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 200316 kb
Host smart-ea72d03f-f3a9-4c73-a075-0c181412435e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793701712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2793701712
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.3655197777
Short name T243
Test name
Test status
Simulation time 22454787 ps
CPU time 0.82 seconds
Started Aug 06 07:26:54 PM PDT 24
Finished Aug 06 07:26:55 PM PDT 24
Peak memory 201100 kb
Host smart-90bc61bf-d40b-4bd9-8c28-12a4dbabd8af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655197777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.3655197777
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.1643198356
Short name T294
Test name
Test status
Simulation time 41010371 ps
CPU time 0.94 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 201108 kb
Host smart-6643f325-a12e-488c-ba07-bfaa7055724e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643198356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.1643198356
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.1134179771
Short name T293
Test name
Test status
Simulation time 2257653793 ps
CPU time 10.14 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:27:07 PM PDT 24
Peak memory 201412 kb
Host smart-df6beb9e-d7ce-4868-8515-86a8994a4d20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134179771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1134179771
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.4090782410
Short name T407
Test name
Test status
Simulation time 495551326 ps
CPU time 4.25 seconds
Started Aug 06 07:26:54 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 201188 kb
Host smart-42a777b4-4107-48e6-bdbf-898204c5df41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090782410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.4090782410
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.87269536
Short name T85
Test name
Test status
Simulation time 29863319 ps
CPU time 1 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 201000 kb
Host smart-ad3a9366-96b2-4b8a-a2f5-3cebe263f364
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87269536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
clkmgr_idle_intersig_mubi.87269536
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.3270353682
Short name T503
Test name
Test status
Simulation time 22628446 ps
CPU time 0.88 seconds
Started Aug 06 07:27:00 PM PDT 24
Finished Aug 06 07:27:01 PM PDT 24
Peak memory 201116 kb
Host smart-5069b982-07de-40c6-979a-08d16b0bee3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270353682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.3270353682
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.4271053047
Short name T783
Test name
Test status
Simulation time 20111647 ps
CPU time 0.78 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 201324 kb
Host smart-163a7bf0-2afd-4b1f-95f3-cb48c9593c7b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271053047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.4271053047
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.3800023804
Short name T605
Test name
Test status
Simulation time 53179401 ps
CPU time 0.87 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 201136 kb
Host smart-996996dd-8518-4149-91a5-c23ed6dc6cdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800023804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.3800023804
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.1461284147
Short name T799
Test name
Test status
Simulation time 1099421360 ps
CPU time 6.57 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:27:03 PM PDT 24
Peak memory 201320 kb
Host smart-e1b3a060-09be-4b81-accd-3446f0b95287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461284147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1461284147
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.338097415
Short name T288
Test name
Test status
Simulation time 18682197 ps
CPU time 0.85 seconds
Started Aug 06 07:26:59 PM PDT 24
Finished Aug 06 07:27:00 PM PDT 24
Peak memory 201100 kb
Host smart-22b782ca-3d23-4e50-af62-0117f387b5a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338097415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.338097415
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.2669750679
Short name T273
Test name
Test status
Simulation time 5224757748 ps
CPU time 28.14 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:27:25 PM PDT 24
Peak memory 201500 kb
Host smart-6bc105ab-0511-4e36-b9fc-f710a0309a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669750679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.2669750679
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.3786118754
Short name T59
Test name
Test status
Simulation time 13911363 ps
CPU time 0.79 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 201140 kb
Host smart-f17520a8-cc14-4aab-b920-f58eddb3f702
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786118754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.3786118754
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.1768896312
Short name T207
Test name
Test status
Simulation time 27762371 ps
CPU time 0.78 seconds
Started Aug 06 07:26:54 PM PDT 24
Finished Aug 06 07:26:55 PM PDT 24
Peak memory 201088 kb
Host smart-1b45c729-0c75-4eab-ac49-5b7fda159709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768896312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.1768896312
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.1469042098
Short name T155
Test name
Test status
Simulation time 18144158 ps
CPU time 0.83 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 201136 kb
Host smart-ed2d1d36-cc5e-40c3-b50f-d077d2c00b20
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469042098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.1469042098
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.1160776414
Short name T529
Test name
Test status
Simulation time 53028802 ps
CPU time 0.78 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 200336 kb
Host smart-daa4a7ed-3964-4f5f-841b-0db276091784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160776414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.1160776414
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3580560173
Short name T368
Test name
Test status
Simulation time 31484808 ps
CPU time 0.99 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 201112 kb
Host smart-78772c7f-ed5c-4ff5-b760-6de251cf506b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580560173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.3580560173
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.2021631053
Short name T396
Test name
Test status
Simulation time 25442260 ps
CPU time 0.86 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 201124 kb
Host smart-5b8feb46-dfe7-497f-bf31-7180dce6cbbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021631053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.2021631053
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.262114404
Short name T24
Test name
Test status
Simulation time 318967905 ps
CPU time 3.03 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:59 PM PDT 24
Peak memory 201104 kb
Host smart-f1861877-f7ce-4d41-bcf2-87f443298f9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262114404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.262114404
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.2766978296
Short name T479
Test name
Test status
Simulation time 2066115487 ps
CPU time 11.21 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:27:08 PM PDT 24
Peak memory 201308 kb
Host smart-e7d9e206-0b38-4bc2-9927-14419c5edf68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766978296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.2766978296
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.1994174184
Short name T659
Test name
Test status
Simulation time 19812266 ps
CPU time 0.82 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 201036 kb
Host smart-22caf727-ba76-46a9-b519-f7de97241f5f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994174184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.1994174184
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.497616117
Short name T664
Test name
Test status
Simulation time 31773762 ps
CPU time 0.89 seconds
Started Aug 06 07:27:00 PM PDT 24
Finished Aug 06 07:27:01 PM PDT 24
Peak memory 201112 kb
Host smart-44f076d0-915a-4e9c-bb8f-d1a5668169f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497616117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_lc_clk_byp_req_intersig_mubi.497616117
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.499563150
Short name T771
Test name
Test status
Simulation time 40644155 ps
CPU time 0.94 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 201096 kb
Host smart-2c25e2fa-b6ee-4ea5-9b1f-2c02c2f74279
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499563150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_lc_ctrl_intersig_mubi.499563150
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.33420636
Short name T423
Test name
Test status
Simulation time 31273910 ps
CPU time 0.83 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 201092 kb
Host smart-1505230e-af70-4128-89ba-67ece354e5b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33420636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.33420636
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.310645719
Short name T434
Test name
Test status
Simulation time 310883830 ps
CPU time 2.26 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 201060 kb
Host smart-82297759-31bc-4cdd-ba07-50ada0a72182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310645719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.310645719
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.3402037909
Short name T806
Test name
Test status
Simulation time 50296429 ps
CPU time 0.96 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 201044 kb
Host smart-42ee0231-b73e-4580-b560-e672b2b9d87f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402037909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.3402037909
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.3518765346
Short name T521
Test name
Test status
Simulation time 8367715264 ps
CPU time 67.72 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:28:03 PM PDT 24
Peak memory 201512 kb
Host smart-7fd09dda-0c1a-4309-ad9a-d5c56627c2f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518765346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.3518765346
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.3499192560
Short name T502
Test name
Test status
Simulation time 15403855 ps
CPU time 0.74 seconds
Started Aug 06 07:26:54 PM PDT 24
Finished Aug 06 07:26:55 PM PDT 24
Peak memory 201120 kb
Host smart-1bbaaaa5-285f-4456-96d6-6be59ee7350f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499192560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3499192560
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.3017125714
Short name T671
Test name
Test status
Simulation time 39428919 ps
CPU time 0.85 seconds
Started Aug 06 07:27:59 PM PDT 24
Finished Aug 06 07:28:00 PM PDT 24
Peak memory 201004 kb
Host smart-74b6708d-b2c1-4abf-9381-45a33bfaf7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017125714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.3017125714
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1183085523
Short name T261
Test name
Test status
Simulation time 27114674 ps
CPU time 0.83 seconds
Started Aug 06 07:27:59 PM PDT 24
Finished Aug 06 07:28:00 PM PDT 24
Peak memory 201148 kb
Host smart-1cd2bff2-8094-40cf-bd33-504f057e1dd1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183085523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.1183085523
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.2196668348
Short name T614
Test name
Test status
Simulation time 33643632 ps
CPU time 0.75 seconds
Started Aug 06 07:27:57 PM PDT 24
Finished Aug 06 07:27:58 PM PDT 24
Peak memory 200236 kb
Host smart-3af3961d-08a8-459a-b30e-f411d2c784e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196668348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2196668348
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1977872937
Short name T622
Test name
Test status
Simulation time 150515477 ps
CPU time 1.15 seconds
Started Aug 06 07:27:57 PM PDT 24
Finished Aug 06 07:27:58 PM PDT 24
Peak memory 201124 kb
Host smart-33dc235e-415e-4b62-acef-eef22108dc8c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977872937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.1977872937
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.2346647116
Short name T485
Test name
Test status
Simulation time 14842819 ps
CPU time 0.74 seconds
Started Aug 06 07:27:48 PM PDT 24
Finished Aug 06 07:27:49 PM PDT 24
Peak memory 201104 kb
Host smart-06bac3d3-bc03-4c14-8c13-125329ed480b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346647116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2346647116
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.3715477350
Short name T120
Test name
Test status
Simulation time 927109482 ps
CPU time 5.49 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:52 PM PDT 24
Peak memory 201156 kb
Host smart-053e2c20-9675-429d-9841-e109ab20ae4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715477350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3715477350
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.182880718
Short name T697
Test name
Test status
Simulation time 979487205 ps
CPU time 7.44 seconds
Started Aug 06 07:27:47 PM PDT 24
Finished Aug 06 07:27:55 PM PDT 24
Peak memory 201188 kb
Host smart-711ff4f5-3dca-41d2-8ac9-2768c6bf3bc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182880718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_ti
meout.182880718
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.507914726
Short name T318
Test name
Test status
Simulation time 342679135 ps
CPU time 1.88 seconds
Started Aug 06 07:27:59 PM PDT 24
Finished Aug 06 07:28:01 PM PDT 24
Peak memory 201072 kb
Host smart-0d49aa44-87cc-430f-b571-fdc98d7f0689
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507914726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_idle_intersig_mubi.507914726
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.2204402496
Short name T336
Test name
Test status
Simulation time 23691260 ps
CPU time 0.81 seconds
Started Aug 06 07:27:58 PM PDT 24
Finished Aug 06 07:27:59 PM PDT 24
Peak memory 201104 kb
Host smart-6004dd61-dc0c-4209-952b-bc57710fe9ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204402496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.2204402496
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.1267296474
Short name T403
Test name
Test status
Simulation time 27878304 ps
CPU time 0.81 seconds
Started Aug 06 07:27:59 PM PDT 24
Finished Aug 06 07:28:00 PM PDT 24
Peak memory 201072 kb
Host smart-3dc3f34a-9642-4a8a-a4da-415eb28c15c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267296474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.1267296474
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.3452132953
Short name T595
Test name
Test status
Simulation time 46643573 ps
CPU time 0.86 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 201088 kb
Host smart-5ee6f146-8210-4bf1-b91e-1c350739289b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452132953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3452132953
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.645699550
Short name T688
Test name
Test status
Simulation time 351442534 ps
CPU time 1.87 seconds
Started Aug 06 07:28:00 PM PDT 24
Finished Aug 06 07:28:02 PM PDT 24
Peak memory 201112 kb
Host smart-e3ec5da1-40ee-4ec0-849e-3f7b4b4586b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645699550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.645699550
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.2765580794
Short name T387
Test name
Test status
Simulation time 309685011 ps
CPU time 1.74 seconds
Started Aug 06 07:27:51 PM PDT 24
Finished Aug 06 07:27:53 PM PDT 24
Peak memory 201088 kb
Host smart-7ffe7d54-3ffe-45dd-bf95-d071d12e576b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765580794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.2765580794
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.699092395
Short name T549
Test name
Test status
Simulation time 5487912229 ps
CPU time 41.91 seconds
Started Aug 06 07:28:01 PM PDT 24
Finished Aug 06 07:28:43 PM PDT 24
Peak memory 201492 kb
Host smart-98d3ace1-b441-4663-91bc-f5d084f66b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699092395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.699092395
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.1549948824
Short name T555
Test name
Test status
Simulation time 41611446 ps
CPU time 1.04 seconds
Started Aug 06 07:27:48 PM PDT 24
Finished Aug 06 07:27:49 PM PDT 24
Peak memory 201136 kb
Host smart-ca9425e5-7ffc-4ac3-9475-d3779f0ab0eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549948824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.1549948824
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.963068137
Short name T727
Test name
Test status
Simulation time 13657207 ps
CPU time 0.78 seconds
Started Aug 06 07:28:02 PM PDT 24
Finished Aug 06 07:28:03 PM PDT 24
Peak memory 201104 kb
Host smart-c723f4e1-b209-4836-8462-83de7eabe2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963068137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkm
gr_alert_test.963068137
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.4260401210
Short name T93
Test name
Test status
Simulation time 92399959 ps
CPU time 1.22 seconds
Started Aug 06 07:28:02 PM PDT 24
Finished Aug 06 07:28:03 PM PDT 24
Peak memory 201108 kb
Host smart-782172cf-9a46-4df9-bd80-85b3ad197c11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260401210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.4260401210
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.3432730131
Short name T400
Test name
Test status
Simulation time 43951093 ps
CPU time 0.8 seconds
Started Aug 06 07:27:59 PM PDT 24
Finished Aug 06 07:28:00 PM PDT 24
Peak memory 201000 kb
Host smart-58d11dae-106c-4ce3-a7d1-98f8389ff777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432730131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3432730131
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.489858979
Short name T575
Test name
Test status
Simulation time 12694661 ps
CPU time 0.72 seconds
Started Aug 06 07:28:02 PM PDT 24
Finished Aug 06 07:28:02 PM PDT 24
Peak memory 201080 kb
Host smart-590ce680-318d-479c-b0b1-bc6eebda113d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489858979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.clkmgr_div_intersig_mubi.489858979
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.4005281904
Short name T405
Test name
Test status
Simulation time 38810220 ps
CPU time 0.91 seconds
Started Aug 06 07:28:00 PM PDT 24
Finished Aug 06 07:28:01 PM PDT 24
Peak memory 201040 kb
Host smart-7d0d9a87-ab6d-43ae-a372-35c5f4dd6197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005281904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.4005281904
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.371474903
Short name T25
Test name
Test status
Simulation time 730004691 ps
CPU time 3.77 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:07 PM PDT 24
Peak memory 201216 kb
Host smart-fc5cde8f-2f18-4ccf-a3c0-23be3082e05e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371474903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.371474903
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.2675012332
Short name T808
Test name
Test status
Simulation time 182491642 ps
CPU time 1.22 seconds
Started Aug 06 07:28:00 PM PDT 24
Finished Aug 06 07:28:01 PM PDT 24
Peak memory 201136 kb
Host smart-6e2a7590-12f1-4218-999b-5e7979258798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675012332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.2675012332
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2967426343
Short name T827
Test name
Test status
Simulation time 76019508 ps
CPU time 1.07 seconds
Started Aug 06 07:28:00 PM PDT 24
Finished Aug 06 07:28:02 PM PDT 24
Peak memory 201088 kb
Host smart-04058f4e-5d75-4f5c-a26b-d8325aefc8fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967426343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.2967426343
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1466608095
Short name T716
Test name
Test status
Simulation time 65452299 ps
CPU time 1 seconds
Started Aug 06 07:28:00 PM PDT 24
Finished Aug 06 07:28:01 PM PDT 24
Peak memory 201012 kb
Host smart-6743fca4-26e2-4029-a6c2-fdc796f2d11f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466608095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1466608095
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1227173415
Short name T53
Test name
Test status
Simulation time 20823273 ps
CPU time 0.83 seconds
Started Aug 06 07:28:01 PM PDT 24
Finished Aug 06 07:28:02 PM PDT 24
Peak memory 201088 kb
Host smart-aa94d6ff-254e-4b49-be21-5bf03b819fdb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227173415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.1227173415
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.505582817
Short name T200
Test name
Test status
Simulation time 57492452 ps
CPU time 0.86 seconds
Started Aug 06 07:28:00 PM PDT 24
Finished Aug 06 07:28:01 PM PDT 24
Peak memory 201048 kb
Host smart-516ac808-6d09-405f-ab09-bd2dee5dd835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505582817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.505582817
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.1310336314
Short name T410
Test name
Test status
Simulation time 1266879224 ps
CPU time 5.23 seconds
Started Aug 06 07:28:01 PM PDT 24
Finished Aug 06 07:28:07 PM PDT 24
Peak memory 201268 kb
Host smart-fe16000c-1596-4c69-af2c-0bc3b5aeedde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310336314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1310336314
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.1778899829
Short name T148
Test name
Test status
Simulation time 26363366 ps
CPU time 0.94 seconds
Started Aug 06 07:27:58 PM PDT 24
Finished Aug 06 07:27:59 PM PDT 24
Peak memory 201096 kb
Host smart-24e3831c-19ee-4b41-a6fe-1946e459f949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778899829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.1778899829
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.2879401608
Short name T792
Test name
Test status
Simulation time 1134738462 ps
CPU time 5.61 seconds
Started Aug 06 07:28:02 PM PDT 24
Finished Aug 06 07:28:07 PM PDT 24
Peak memory 201140 kb
Host smart-9b0eb935-62cc-472f-b5e7-c4e050c4e44e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879401608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.2879401608
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.1508992940
Short name T292
Test name
Test status
Simulation time 39673108 ps
CPU time 1.11 seconds
Started Aug 06 07:27:59 PM PDT 24
Finished Aug 06 07:28:00 PM PDT 24
Peak memory 201040 kb
Host smart-a4baa261-ba57-4115-b831-fec97badfdff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508992940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1508992940
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.2254151932
Short name T252
Test name
Test status
Simulation time 52553939 ps
CPU time 0.84 seconds
Started Aug 06 07:28:08 PM PDT 24
Finished Aug 06 07:28:08 PM PDT 24
Peak memory 201096 kb
Host smart-301787cc-4fa9-4635-b8b5-104fbde93b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254151932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.2254151932
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3757357979
Short name T723
Test name
Test status
Simulation time 44123405 ps
CPU time 0.98 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:04 PM PDT 24
Peak memory 201088 kb
Host smart-48b3c060-512a-44ff-b7e7-16914da88009
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757357979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3757357979
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.1084893020
Short name T508
Test name
Test status
Simulation time 15526433 ps
CPU time 0.74 seconds
Started Aug 06 07:28:01 PM PDT 24
Finished Aug 06 07:28:02 PM PDT 24
Peak memory 200916 kb
Host smart-5dd2b403-6b5b-401a-afc2-2d1a86ccd391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084893020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.1084893020
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.3959610015
Short name T504
Test name
Test status
Simulation time 23487484 ps
CPU time 0.77 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:03 PM PDT 24
Peak memory 200868 kb
Host smart-68918578-2137-42ce-aa80-59fbb6628245
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959610015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.3959610015
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.3125344491
Short name T628
Test name
Test status
Simulation time 37637459 ps
CPU time 0.78 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:04 PM PDT 24
Peak memory 201068 kb
Host smart-cb7567a5-0f40-4979-a74a-13a3fc675f11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125344491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.3125344491
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.3058167058
Short name T742
Test name
Test status
Simulation time 1519871795 ps
CPU time 9.34 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:12 PM PDT 24
Peak memory 201168 kb
Host smart-d907590f-b7be-42a5-989b-bba435ffd38b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058167058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3058167058
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.3707090150
Short name T187
Test name
Test status
Simulation time 738381069 ps
CPU time 5.89 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:19 PM PDT 24
Peak memory 201292 kb
Host smart-de4c98bf-7f3b-4993-95bb-96bf00817e43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707090150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.3707090150
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.672939386
Short name T709
Test name
Test status
Simulation time 39902064 ps
CPU time 0.81 seconds
Started Aug 06 07:28:01 PM PDT 24
Finished Aug 06 07:28:02 PM PDT 24
Peak memory 200992 kb
Host smart-dd23ea2f-a5af-4fa9-99a7-4f405a709c73
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672939386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.clkmgr_idle_intersig_mubi.672939386
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2676457653
Short name T646
Test name
Test status
Simulation time 84780398 ps
CPU time 1.11 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:04 PM PDT 24
Peak memory 200912 kb
Host smart-dfed9e67-43d3-4c28-a4c4-96f3ece612c3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676457653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.2676457653
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2047098373
Short name T606
Test name
Test status
Simulation time 42486214 ps
CPU time 0.97 seconds
Started Aug 06 07:28:02 PM PDT 24
Finished Aug 06 07:28:03 PM PDT 24
Peak memory 201172 kb
Host smart-57627815-4d86-4d2d-be36-7d3369e27e57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047098373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.2047098373
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.3677103859
Short name T757
Test name
Test status
Simulation time 18559099 ps
CPU time 0.8 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:04 PM PDT 24
Peak memory 201148 kb
Host smart-49e78a74-0f42-4ad9-9d40-83c5ab7b34ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677103859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3677103859
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.3375286412
Short name T625
Test name
Test status
Simulation time 17859798 ps
CPU time 0.84 seconds
Started Aug 06 07:28:01 PM PDT 24
Finished Aug 06 07:28:02 PM PDT 24
Peak memory 201004 kb
Host smart-1e04c0f9-3b7b-4ffc-aaf4-a8c9a0422ef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375286412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.3375286412
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.3451968092
Short name T149
Test name
Test status
Simulation time 7961918677 ps
CPU time 31.66 seconds
Started Aug 06 07:28:08 PM PDT 24
Finished Aug 06 07:28:40 PM PDT 24
Peak memory 201448 kb
Host smart-c061356a-5054-42eb-a081-c701f31590b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451968092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.3451968092
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.483055149
Short name T68
Test name
Test status
Simulation time 58839672696 ps
CPU time 360.12 seconds
Started Aug 06 07:28:07 PM PDT 24
Finished Aug 06 07:34:08 PM PDT 24
Peak memory 209780 kb
Host smart-08a4cce9-c0a1-463a-88d5-5896965e9925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=483055149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.483055149
Directory /workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.clkmgr_trans.2076780532
Short name T430
Test name
Test status
Simulation time 14270715 ps
CPU time 0.71 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:04 PM PDT 24
Peak memory 201104 kb
Host smart-5f8ece2c-930a-4ef5-a8e3-4ecaaf555f61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076780532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2076780532
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.2282274115
Short name T685
Test name
Test status
Simulation time 35875647 ps
CPU time 0.79 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:13 PM PDT 24
Peak memory 201320 kb
Host smart-b60d2316-62ca-4469-9b38-532c00f29e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282274115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.2282274115
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1523289784
Short name T97
Test name
Test status
Simulation time 23757263 ps
CPU time 0.87 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:14 PM PDT 24
Peak memory 201104 kb
Host smart-589dff76-50e4-40e2-81b8-430c24b287af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523289784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.1523289784
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.3206817846
Short name T782
Test name
Test status
Simulation time 16197595 ps
CPU time 0.72 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:28:15 PM PDT 24
Peak memory 201024 kb
Host smart-7a49f84c-3bcd-4bf1-900d-a1322cb58703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206817846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3206817846
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.2077398426
Short name T818
Test name
Test status
Simulation time 82614373 ps
CPU time 0.97 seconds
Started Aug 06 07:28:12 PM PDT 24
Finished Aug 06 07:28:13 PM PDT 24
Peak memory 201080 kb
Host smart-51a9067e-1ea3-44c7-bf2a-cd95ed5bec7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077398426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.2077398426
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.1133304296
Short name T748
Test name
Test status
Simulation time 36384505 ps
CPU time 1.01 seconds
Started Aug 06 07:28:02 PM PDT 24
Finished Aug 06 07:28:03 PM PDT 24
Peak memory 201116 kb
Host smart-b33f2b94-df6b-4840-ade3-777aee31a210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133304296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.1133304296
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.3353605380
Short name T49
Test name
Test status
Simulation time 1419829110 ps
CPU time 6.59 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:09 PM PDT 24
Peak memory 201200 kb
Host smart-765e7de9-51c1-497c-a5f3-348a72c830cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353605380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3353605380
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.3407098431
Short name T298
Test name
Test status
Simulation time 1696581528 ps
CPU time 12.73 seconds
Started Aug 06 07:28:03 PM PDT 24
Finished Aug 06 07:28:16 PM PDT 24
Peak memory 201256 kb
Host smart-dce599a7-15ce-4967-941c-c710a984333a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407098431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.3407098431
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3092426152
Short name T301
Test name
Test status
Simulation time 47707289 ps
CPU time 1 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:28:15 PM PDT 24
Peak memory 201064 kb
Host smart-8a3ca435-da60-4ec7-a3f7-4ba962dbeaf0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092426152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.3092426152
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2167165823
Short name T538
Test name
Test status
Simulation time 20981018 ps
CPU time 0.85 seconds
Started Aug 06 07:28:12 PM PDT 24
Finished Aug 06 07:28:13 PM PDT 24
Peak memory 201044 kb
Host smart-b320d9f2-ab70-4d76-a607-594e82423437
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167165823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.2167165823
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.3275070237
Short name T584
Test name
Test status
Simulation time 38677565 ps
CPU time 0.88 seconds
Started Aug 06 07:28:12 PM PDT 24
Finished Aug 06 07:28:13 PM PDT 24
Peak memory 201112 kb
Host smart-4532a3d6-ac6a-4288-99e5-82ec42bf5f89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275070237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.3275070237
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.3932077840
Short name T281
Test name
Test status
Simulation time 13252963 ps
CPU time 0.7 seconds
Started Aug 06 07:28:12 PM PDT 24
Finished Aug 06 07:28:12 PM PDT 24
Peak memory 201036 kb
Host smart-72c8d412-dc24-4969-bbca-c447fbfb586d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932077840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.3932077840
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.709263967
Short name T699
Test name
Test status
Simulation time 1168334800 ps
CPU time 6.38 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:28:20 PM PDT 24
Peak memory 201292 kb
Host smart-5cffdd6d-487f-4712-8d33-d28e9f130282
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709263967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.709263967
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.1206008994
Short name T384
Test name
Test status
Simulation time 44647636 ps
CPU time 0.93 seconds
Started Aug 06 07:28:08 PM PDT 24
Finished Aug 06 07:28:09 PM PDT 24
Peak memory 201092 kb
Host smart-140437ac-d1de-4319-8ced-555c8f1efdd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206008994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1206008994
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.2448468318
Short name T421
Test name
Test status
Simulation time 7569049528 ps
CPU time 31.32 seconds
Started Aug 06 07:28:12 PM PDT 24
Finished Aug 06 07:28:43 PM PDT 24
Peak memory 201484 kb
Host smart-0957cfac-3c00-4f6a-b795-61b644f236a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448468318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.2448468318
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.1835773202
Short name T616
Test name
Test status
Simulation time 32140681090 ps
CPU time 228.53 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:32:03 PM PDT 24
Peak memory 209816 kb
Host smart-f7beb176-d794-49b9-8237-e3497f91c9b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1835773202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.1835773202
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.clkmgr_trans.2571273460
Short name T507
Test name
Test status
Simulation time 22255299 ps
CPU time 0.93 seconds
Started Aug 06 07:28:12 PM PDT 24
Finished Aug 06 07:28:13 PM PDT 24
Peak memory 201144 kb
Host smart-56464f6d-154f-4c58-bf37-14b45d38a5c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571273460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2571273460
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.1541870682
Short name T233
Test name
Test status
Simulation time 59652966 ps
CPU time 0.93 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:28:15 PM PDT 24
Peak memory 201100 kb
Host smart-742cf740-bd71-413d-a8ac-e51f6cc0e9dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541870682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.1541870682
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2938025184
Short name T786
Test name
Test status
Simulation time 25692388 ps
CPU time 0.92 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:28:15 PM PDT 24
Peak memory 201052 kb
Host smart-e7b1e396-5ed8-4f22-893e-da48b4a65e3c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938025184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.2938025184
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.2766961378
Short name T681
Test name
Test status
Simulation time 16581696 ps
CPU time 0.76 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:28:14 PM PDT 24
Peak memory 200284 kb
Host smart-5668a2a4-735e-4c42-80c1-6267f1d14381
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766961378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.2766961378
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.2442128691
Short name T326
Test name
Test status
Simulation time 59187322 ps
CPU time 0.87 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:14 PM PDT 24
Peak memory 201060 kb
Host smart-7c9a8270-5039-4d67-b1fe-76de7219d4ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442128691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.2442128691
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.3986896369
Short name T249
Test name
Test status
Simulation time 95523854 ps
CPU time 1.07 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:14 PM PDT 24
Peak memory 201064 kb
Host smart-80247501-f335-466b-a4fe-7a81350f1f67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986896369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3986896369
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.4034521461
Short name T762
Test name
Test status
Simulation time 948525686 ps
CPU time 5.87 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:19 PM PDT 24
Peak memory 201244 kb
Host smart-cbd36c71-4345-498d-a0a0-62fbc5f9c702
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034521461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.4034521461
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.543537227
Short name T488
Test name
Test status
Simulation time 980393649 ps
CPU time 6.65 seconds
Started Aug 06 07:28:15 PM PDT 24
Finished Aug 06 07:28:22 PM PDT 24
Peak memory 201224 kb
Host smart-11c445c8-89a6-4f31-ac3a-fa95742d77b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543537227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_ti
meout.543537227
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2974504524
Short name T364
Test name
Test status
Simulation time 78686323 ps
CPU time 1.06 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:14 PM PDT 24
Peak memory 201092 kb
Host smart-9f985ec3-98ec-4a68-8f56-9841a804f2d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974504524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.2974504524
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.132389367
Short name T57
Test name
Test status
Simulation time 20967147 ps
CPU time 0.86 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:14 PM PDT 24
Peak memory 201088 kb
Host smart-96b62fe0-ce47-4165-9166-11e87747f227
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132389367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_clk_byp_req_intersig_mubi.132389367
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.2987895391
Short name T536
Test name
Test status
Simulation time 16886401 ps
CPU time 0.78 seconds
Started Aug 06 07:28:13 PM PDT 24
Finished Aug 06 07:28:14 PM PDT 24
Peak memory 201108 kb
Host smart-615cfa4e-fa67-4edf-b4df-38e699f2646e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987895391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.2987895391
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.1192938997
Short name T186
Test name
Test status
Simulation time 48167189 ps
CPU time 0.87 seconds
Started Aug 06 07:28:12 PM PDT 24
Finished Aug 06 07:28:13 PM PDT 24
Peak memory 200956 kb
Host smart-e48da3d9-da33-480e-bce7-1e14cb17f5bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192938997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.1192938997
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.2873275942
Short name T601
Test name
Test status
Simulation time 985110161 ps
CPU time 3.74 seconds
Started Aug 06 07:28:15 PM PDT 24
Finished Aug 06 07:28:19 PM PDT 24
Peak memory 201284 kb
Host smart-c5199587-56bd-405e-be4f-55006fd893e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873275942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2873275942
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.227629225
Short name T489
Test name
Test status
Simulation time 114016916 ps
CPU time 1.12 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:28:15 PM PDT 24
Peak memory 200940 kb
Host smart-34add45d-a193-4485-ba19-4c96aa920038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227629225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.227629225
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.2141731758
Short name T212
Test name
Test status
Simulation time 79874936 ps
CPU time 1.5 seconds
Started Aug 06 07:28:16 PM PDT 24
Finished Aug 06 07:28:18 PM PDT 24
Peak memory 201100 kb
Host smart-c1bca8ab-0aa4-4829-a36d-d049293d56bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141731758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.2141731758
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.220084351
Short name T710
Test name
Test status
Simulation time 114731792193 ps
CPU time 688.56 seconds
Started Aug 06 07:28:15 PM PDT 24
Finished Aug 06 07:39:44 PM PDT 24
Peak memory 217944 kb
Host smart-9032604d-8ca1-4e18-ad45-9b59f3e3d0c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=220084351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.220084351
Directory /workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_trans.1322366688
Short name T259
Test name
Test status
Simulation time 35879631 ps
CPU time 0.76 seconds
Started Aug 06 07:28:14 PM PDT 24
Finished Aug 06 07:28:15 PM PDT 24
Peak memory 201080 kb
Host smart-29f53d6b-1f20-4094-8b56-62ea5dc17bfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322366688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.1322366688
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.3655644033
Short name T290
Test name
Test status
Simulation time 34666703 ps
CPU time 0.78 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:32 PM PDT 24
Peak memory 201100 kb
Host smart-1f9e49c3-1c0b-4ac2-8711-68cc77b08dce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655644033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.3655644033
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.4063763710
Short name T607
Test name
Test status
Simulation time 20987708 ps
CPU time 0.82 seconds
Started Aug 06 07:28:32 PM PDT 24
Finished Aug 06 07:28:33 PM PDT 24
Peak memory 201148 kb
Host smart-a1189ac6-bdb6-4da3-a732-838f75dba3ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063763710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.4063763710
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.284113723
Short name T313
Test name
Test status
Simulation time 16592055 ps
CPU time 0.74 seconds
Started Aug 06 07:28:30 PM PDT 24
Finished Aug 06 07:28:31 PM PDT 24
Peak memory 200204 kb
Host smart-d375e9e9-95a3-4959-ab61-38ad42d4f0a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284113723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.284113723
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.129065919
Short name T460
Test name
Test status
Simulation time 76650989 ps
CPU time 1.01 seconds
Started Aug 06 07:28:30 PM PDT 24
Finished Aug 06 07:28:31 PM PDT 24
Peak memory 201072 kb
Host smart-e2f21538-5b38-4249-9957-c5df233b153e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129065919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_div_intersig_mubi.129065919
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.3528079972
Short name T332
Test name
Test status
Simulation time 23135091 ps
CPU time 0.84 seconds
Started Aug 06 07:28:17 PM PDT 24
Finished Aug 06 07:28:18 PM PDT 24
Peak memory 201024 kb
Host smart-50ac5dd7-f6da-4efd-a075-95307f860ee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528079972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3528079972
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.949578281
Short name T612
Test name
Test status
Simulation time 931744745 ps
CPU time 5.64 seconds
Started Aug 06 07:28:15 PM PDT 24
Finished Aug 06 07:28:21 PM PDT 24
Peak memory 201104 kb
Host smart-50a1ca1b-086e-426b-aec1-e78034167d1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949578281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.949578281
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.2886810872
Short name T426
Test name
Test status
Simulation time 1244841094 ps
CPU time 5.43 seconds
Started Aug 06 07:28:32 PM PDT 24
Finished Aug 06 07:28:38 PM PDT 24
Peak memory 201228 kb
Host smart-cc7c39de-8073-4f5e-9683-c595f5983a78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886810872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.2886810872
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.2334980806
Short name T816
Test name
Test status
Simulation time 352634229 ps
CPU time 1.83 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:33 PM PDT 24
Peak memory 201076 kb
Host smart-6ec51e27-06b2-4601-baf0-9441c9e2d85f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334980806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.2334980806
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.1410225174
Short name T279
Test name
Test status
Simulation time 63014607 ps
CPU time 0.95 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:32 PM PDT 24
Peak memory 201036 kb
Host smart-23c513e8-f85a-43c5-8da8-10da9211673c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410225174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.1410225174
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.4116225055
Short name T260
Test name
Test status
Simulation time 41654854 ps
CPU time 0.84 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:31 PM PDT 24
Peak memory 201120 kb
Host smart-9d9020c3-6280-4145-ab49-ab7b6fcb7241
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116225055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.4116225055
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.2050572802
Short name T562
Test name
Test status
Simulation time 37959105 ps
CPU time 0.81 seconds
Started Aug 06 07:28:32 PM PDT 24
Finished Aug 06 07:28:32 PM PDT 24
Peak memory 201044 kb
Host smart-43593537-81c2-420c-9cf6-0290731777f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050572802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.2050572802
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.2697316296
Short name T670
Test name
Test status
Simulation time 444070754 ps
CPU time 1.95 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:33 PM PDT 24
Peak memory 201112 kb
Host smart-a9e303b3-5e4f-4da8-bd33-10a42dc5cacc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697316296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.2697316296
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.484574634
Short name T325
Test name
Test status
Simulation time 54139349 ps
CPU time 0.94 seconds
Started Aug 06 07:28:15 PM PDT 24
Finished Aug 06 07:28:16 PM PDT 24
Peak memory 201008 kb
Host smart-b920f5de-e07f-408c-bdc5-02215a363380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484574634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.484574634
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.2366638133
Short name T654
Test name
Test status
Simulation time 3253074057 ps
CPU time 14.65 seconds
Started Aug 06 07:28:30 PM PDT 24
Finished Aug 06 07:28:45 PM PDT 24
Peak memory 201424 kb
Host smart-ef1a1a54-ac9f-4440-9993-a512bcbf9371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366638133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.2366638133
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.4171842702
Short name T167
Test name
Test status
Simulation time 50337366 ps
CPU time 0.95 seconds
Started Aug 06 07:28:30 PM PDT 24
Finished Aug 06 07:28:31 PM PDT 24
Peak memory 201096 kb
Host smart-0ee00f64-545c-46ea-9a60-52940990b6b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171842702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.4171842702
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.821590211
Short name T797
Test name
Test status
Simulation time 18484954 ps
CPU time 0.71 seconds
Started Aug 06 07:28:33 PM PDT 24
Finished Aug 06 07:28:34 PM PDT 24
Peak memory 201072 kb
Host smart-81efb8fd-09ff-472e-b891-4c831490e3b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821590211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkm
gr_alert_test.821590211
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.390534733
Short name T94
Test name
Test status
Simulation time 17961440 ps
CPU time 0.81 seconds
Started Aug 06 07:28:33 PM PDT 24
Finished Aug 06 07:28:33 PM PDT 24
Peak memory 201128 kb
Host smart-7599e5e7-3947-40b8-9dc9-edbd15733eef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390534733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.390534733
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.432292111
Short name T801
Test name
Test status
Simulation time 19136523 ps
CPU time 0.73 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:32 PM PDT 24
Peak memory 200980 kb
Host smart-9f57f7fa-fb50-4fc6-a201-62eb470db3ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432292111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.432292111
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.3490237291
Short name T702
Test name
Test status
Simulation time 18507489 ps
CPU time 0.8 seconds
Started Aug 06 07:28:33 PM PDT 24
Finished Aug 06 07:28:34 PM PDT 24
Peak memory 201112 kb
Host smart-355e3745-06e5-4d96-95ed-675ddf7ab92d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490237291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.3490237291
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.2840368547
Short name T389
Test name
Test status
Simulation time 45091589 ps
CPU time 0.85 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:32 PM PDT 24
Peak memory 201320 kb
Host smart-6a7ec65a-b476-4660-9d9b-fb8809fe29ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840368547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2840368547
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.3853153749
Short name T574
Test name
Test status
Simulation time 434805175 ps
CPU time 3.92 seconds
Started Aug 06 07:28:32 PM PDT 24
Finished Aug 06 07:28:36 PM PDT 24
Peak memory 201172 kb
Host smart-59091c72-0dc8-44e3-a284-26c037af21fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853153749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.3853153749
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.3713235422
Short name T391
Test name
Test status
Simulation time 1549559433 ps
CPU time 6.12 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:38 PM PDT 24
Peak memory 201208 kb
Host smart-15511187-5f22-434b-974e-c649525ec3d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713235422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.3713235422
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.839090443
Short name T491
Test name
Test status
Simulation time 143488421 ps
CPU time 1.34 seconds
Started Aug 06 07:28:32 PM PDT 24
Finished Aug 06 07:28:33 PM PDT 24
Peak memory 201072 kb
Host smart-abf64d87-8b02-44d5-a4d9-6cd0367f306c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839090443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.clkmgr_idle_intersig_mubi.839090443
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1077845373
Short name T546
Test name
Test status
Simulation time 98311887 ps
CPU time 1.08 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:35 PM PDT 24
Peak memory 201072 kb
Host smart-2e109cce-4fcf-4c77-9e0c-052e9c36b479
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077845373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1077845373
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3264683879
Short name T763
Test name
Test status
Simulation time 61665640 ps
CPU time 0.94 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:35 PM PDT 24
Peak memory 201164 kb
Host smart-46a6a522-0379-4660-a3e5-6a83c9e875d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264683879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.3264683879
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.2678055403
Short name T382
Test name
Test status
Simulation time 25907891 ps
CPU time 0.74 seconds
Started Aug 06 07:28:30 PM PDT 24
Finished Aug 06 07:28:31 PM PDT 24
Peak memory 201124 kb
Host smart-cffe41cf-5d9a-4c9c-b291-f40a12156628
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678055403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.2678055403
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.1062980387
Short name T526
Test name
Test status
Simulation time 1173196791 ps
CPU time 6.79 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:41 PM PDT 24
Peak memory 201272 kb
Host smart-2d219a01-f2b7-4e28-b6d0-49d4d8e992e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062980387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1062980387
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.2783740309
Short name T621
Test name
Test status
Simulation time 23969489 ps
CPU time 0.86 seconds
Started Aug 06 07:28:31 PM PDT 24
Finished Aug 06 07:28:32 PM PDT 24
Peak memory 201028 kb
Host smart-39ea6176-f7c6-489b-9dc9-6307232ec8df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783740309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2783740309
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.844020463
Short name T645
Test name
Test status
Simulation time 8017379749 ps
CPU time 35.05 seconds
Started Aug 06 07:28:33 PM PDT 24
Finished Aug 06 07:29:08 PM PDT 24
Peak memory 201516 kb
Host smart-61cfc446-47e0-48b9-8fe3-f898a83e0775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844020463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.844020463
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3912143959
Short name T642
Test name
Test status
Simulation time 72396337 ps
CPU time 0.87 seconds
Started Aug 06 07:28:32 PM PDT 24
Finished Aug 06 07:28:33 PM PDT 24
Peak memory 201104 kb
Host smart-a34c8eb6-1855-4ff2-bde9-02a9799fe0ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912143959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3912143959
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.2155378475
Short name T255
Test name
Test status
Simulation time 12666817 ps
CPU time 0.73 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201084 kb
Host smart-c15202d3-b485-4081-bc1c-ccec24bf131c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155378475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.2155378475
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.4178739316
Short name T152
Test name
Test status
Simulation time 88883629 ps
CPU time 0.97 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:35 PM PDT 24
Peak memory 201068 kb
Host smart-8f27624e-90f1-4a2c-94dc-0efc8fc90a11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178739316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.4178739316
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.815082239
Short name T826
Test name
Test status
Simulation time 83422373 ps
CPU time 1.07 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:35 PM PDT 24
Peak memory 201128 kb
Host smart-ea918f3c-7a4e-4c60-b371-7a678aa0584c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815082239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.clkmgr_div_intersig_mubi.815082239
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.4254616708
Short name T548
Test name
Test status
Simulation time 16895691 ps
CPU time 0.72 seconds
Started Aug 06 07:28:33 PM PDT 24
Finished Aug 06 07:28:34 PM PDT 24
Peak memory 201120 kb
Host smart-ae70a6d4-25a7-426f-9c62-8301bcdec583
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254616708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.4254616708
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.1280517178
Short name T263
Test name
Test status
Simulation time 1877084062 ps
CPU time 13.75 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:48 PM PDT 24
Peak memory 201364 kb
Host smart-669c48ce-26cb-4d04-8146-c18ab793393f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280517178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1280517178
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.2644666505
Short name T247
Test name
Test status
Simulation time 1122303232 ps
CPU time 4.9 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:39 PM PDT 24
Peak memory 201160 kb
Host smart-5e27d238-282f-4ca4-ab2d-9dc920ea8283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644666505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.2644666505
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2230679822
Short name T812
Test name
Test status
Simulation time 17816586 ps
CPU time 0.77 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:35 PM PDT 24
Peak memory 201088 kb
Host smart-624e336f-07cd-4b37-9be9-b6b71d71a46f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230679822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2230679822
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2813463796
Short name T761
Test name
Test status
Simulation time 27522295 ps
CPU time 0.93 seconds
Started Aug 06 07:28:35 PM PDT 24
Finished Aug 06 07:28:37 PM PDT 24
Peak memory 201080 kb
Host smart-5cf3d949-ca59-4b56-b104-0b8a19e90341
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813463796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.2813463796
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.1482991115
Short name T698
Test name
Test status
Simulation time 125085310 ps
CPU time 1.15 seconds
Started Aug 06 07:28:35 PM PDT 24
Finished Aug 06 07:28:37 PM PDT 24
Peak memory 201008 kb
Host smart-55cdaccb-3f61-4d8d-a8dc-0670911ded7d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482991115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.1482991115
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.1432676962
Short name T760
Test name
Test status
Simulation time 27134327 ps
CPU time 0.8 seconds
Started Aug 06 07:28:33 PM PDT 24
Finished Aug 06 07:28:34 PM PDT 24
Peak memory 201132 kb
Host smart-a596178f-e922-4f6d-813e-3024ad56d7d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432676962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1432676962
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.1754098037
Short name T161
Test name
Test status
Simulation time 931212097 ps
CPU time 3.84 seconds
Started Aug 06 07:28:35 PM PDT 24
Finished Aug 06 07:28:39 PM PDT 24
Peak memory 201168 kb
Host smart-81a689f6-f148-4812-a827-a275dca675bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754098037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1754098037
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.3549687388
Short name T785
Test name
Test status
Simulation time 15245097 ps
CPU time 0.83 seconds
Started Aug 06 07:28:33 PM PDT 24
Finished Aug 06 07:28:34 PM PDT 24
Peak memory 201072 kb
Host smart-2240dd31-19fc-40ec-9019-8321ed73ac04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549687388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3549687388
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.105333741
Short name T446
Test name
Test status
Simulation time 6110599062 ps
CPU time 24.01 seconds
Started Aug 06 07:28:49 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201424 kb
Host smart-b92590b6-d8a6-40d6-889f-c08db8a45097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105333741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.105333741
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.900762362
Short name T244
Test name
Test status
Simulation time 33434571 ps
CPU time 0.88 seconds
Started Aug 06 07:28:34 PM PDT 24
Finished Aug 06 07:28:35 PM PDT 24
Peak memory 201140 kb
Host smart-f073a514-2e43-4bec-9907-f5b83e24e1b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900762362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.900762362
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.2974469757
Short name T33
Test name
Test status
Simulation time 21438327 ps
CPU time 0.81 seconds
Started Aug 06 07:28:49 PM PDT 24
Finished Aug 06 07:28:50 PM PDT 24
Peak memory 201092 kb
Host smart-2ecafa6f-108d-488d-81de-d836d1cfdaa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974469757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.2974469757
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.4236309962
Short name T92
Test name
Test status
Simulation time 30080433 ps
CPU time 1.03 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:48 PM PDT 24
Peak memory 201104 kb
Host smart-86d1642d-f222-46cd-84ec-cc979496b5d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236309962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.4236309962
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.587069747
Short name T175
Test name
Test status
Simulation time 13390194 ps
CPU time 0.72 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 200256 kb
Host smart-97ba3b2c-6ade-47d4-a3e1-f931434238d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587069747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.587069747
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.665715447
Short name T431
Test name
Test status
Simulation time 45872327 ps
CPU time 0.94 seconds
Started Aug 06 07:28:46 PM PDT 24
Finished Aug 06 07:28:47 PM PDT 24
Peak memory 201008 kb
Host smart-4150617d-e1c1-4b73-a9c5-a41b5e3d0e98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665715447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.clkmgr_div_intersig_mubi.665715447
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.3619416655
Short name T539
Test name
Test status
Simulation time 53963555 ps
CPU time 1.03 seconds
Started Aug 06 07:28:44 PM PDT 24
Finished Aug 06 07:28:45 PM PDT 24
Peak memory 201100 kb
Host smart-ce6f9f56-2e80-4f99-99f5-7e0228632c27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619416655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.3619416655
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.255810659
Short name T599
Test name
Test status
Simulation time 2361168166 ps
CPU time 18.98 seconds
Started Aug 06 07:28:48 PM PDT 24
Finished Aug 06 07:29:07 PM PDT 24
Peak memory 201368 kb
Host smart-c64a1ea3-dff5-4486-86d6-e897c31566d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255810659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.255810659
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.152923912
Short name T578
Test name
Test status
Simulation time 1361039138 ps
CPU time 5.48 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:51 PM PDT 24
Peak memory 201176 kb
Host smart-dbf0d178-37b0-43ff-b3b4-0fcea77dc507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152923912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_ti
meout.152923912
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3583205866
Short name T404
Test name
Test status
Simulation time 45237673 ps
CPU time 0.97 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201100 kb
Host smart-2a4c4855-2715-4987-b31e-f94a8f7d10dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583205866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3583205866
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.1413719541
Short name T579
Test name
Test status
Simulation time 26684553 ps
CPU time 0.86 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:48 PM PDT 24
Peak memory 201072 kb
Host smart-fb5a15c8-fade-4a65-a141-21d3962c99dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413719541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.1413719541
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.11068597
Short name T585
Test name
Test status
Simulation time 50112981 ps
CPU time 0.9 seconds
Started Aug 06 07:28:43 PM PDT 24
Finished Aug 06 07:28:44 PM PDT 24
Peak memory 201096 kb
Host smart-d70b9522-6a6f-42c6-b37c-1747280116d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.11068597
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.3506981219
Short name T453
Test name
Test status
Simulation time 836656809 ps
CPU time 3.61 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:49 PM PDT 24
Peak memory 201260 kb
Host smart-bf1a4123-2bf2-41e5-bd6d-0ed18d7cc884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506981219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3506981219
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.2082270074
Short name T310
Test name
Test status
Simulation time 47611563 ps
CPU time 0.93 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201084 kb
Host smart-b152895c-430b-41a0-ac08-e7e83ad3a137
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082270074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2082270074
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.1167740578
Short name T422
Test name
Test status
Simulation time 4943677661 ps
CPU time 21.96 seconds
Started Aug 06 07:28:43 PM PDT 24
Finished Aug 06 07:29:05 PM PDT 24
Peak memory 201344 kb
Host smart-2736f899-5afb-4b0d-afdf-3921a4bb8591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167740578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.1167740578
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.3919581932
Short name T547
Test name
Test status
Simulation time 50256973 ps
CPU time 0.96 seconds
Started Aug 06 07:28:46 PM PDT 24
Finished Aug 06 07:28:47 PM PDT 24
Peak memory 201132 kb
Host smart-5d185d8c-e096-4bf6-b5ad-078bd6d01025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919581932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3919581932
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.714573163
Short name T46
Test name
Test status
Simulation time 16966582 ps
CPU time 0.82 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201152 kb
Host smart-3447eeb0-5c94-4912-8b87-4d1e9e047133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714573163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkm
gr_alert_test.714573163
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.2100976011
Short name T787
Test name
Test status
Simulation time 50584838 ps
CPU time 0.91 seconds
Started Aug 06 07:28:44 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201152 kb
Host smart-5e78b086-fc87-4f0b-b5b7-c595b76f33b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100976011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.2100976011
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.1495308962
Short name T267
Test name
Test status
Simulation time 38820578 ps
CPU time 0.77 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 200280 kb
Host smart-1e3bd226-d356-419b-9405-a1302cc9f1f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495308962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1495308962
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.605018107
Short name T248
Test name
Test status
Simulation time 88625196 ps
CPU time 1.13 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:49 PM PDT 24
Peak memory 201072 kb
Host smart-511e1c8a-f45c-4e97-898a-56c961f4755e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605018107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.clkmgr_div_intersig_mubi.605018107
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.671653906
Short name T337
Test name
Test status
Simulation time 30908827 ps
CPU time 0.86 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201020 kb
Host smart-30090faf-136d-4b30-ad7f-93072bdea02e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671653906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.671653906
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.459237813
Short name T770
Test name
Test status
Simulation time 801087413 ps
CPU time 6.35 seconds
Started Aug 06 07:28:44 PM PDT 24
Finished Aug 06 07:28:51 PM PDT 24
Peak memory 201104 kb
Host smart-0b76fc40-4243-4bcb-921f-bb709bd19be1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459237813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.459237813
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.78871375
Short name T561
Test name
Test status
Simulation time 1119108177 ps
CPU time 5.05 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:50 PM PDT 24
Peak memory 201164 kb
Host smart-d80549a2-c28b-424e-a45d-853fc6cce320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78871375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_tim
eout.78871375
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.4003070355
Short name T256
Test name
Test status
Simulation time 29997510 ps
CPU time 0.95 seconds
Started Aug 06 07:28:44 PM PDT 24
Finished Aug 06 07:28:45 PM PDT 24
Peak memory 201088 kb
Host smart-f8204cd4-cf80-4d6d-bd5a-0cbc5d9d2bd5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003070355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.4003070355
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2637384750
Short name T58
Test name
Test status
Simulation time 23818982 ps
CPU time 0.86 seconds
Started Aug 06 07:28:46 PM PDT 24
Finished Aug 06 07:28:47 PM PDT 24
Peak memory 200992 kb
Host smart-48628679-517e-400b-b97a-d7a3db1d22b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637384750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2637384750
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.944298319
Short name T582
Test name
Test status
Simulation time 32051356 ps
CPU time 0.84 seconds
Started Aug 06 07:28:49 PM PDT 24
Finished Aug 06 07:28:50 PM PDT 24
Peak memory 201040 kb
Host smart-032c62d5-d47b-4c90-9f53-e0791977b5fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944298319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.clkmgr_lc_ctrl_intersig_mubi.944298319
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.2226393251
Short name T825
Test name
Test status
Simulation time 73061764 ps
CPU time 0.85 seconds
Started Aug 06 07:28:44 PM PDT 24
Finished Aug 06 07:28:45 PM PDT 24
Peak memory 201096 kb
Host smart-472f954b-802d-4e6d-8736-5c93be78bff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226393251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.2226393251
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.1055790801
Short name T103
Test name
Test status
Simulation time 784038182 ps
CPU time 3.95 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:49 PM PDT 24
Peak memory 201232 kb
Host smart-d6073fd7-b40d-44f4-be82-a4ed812d80f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055790801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1055790801
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.3496699532
Short name T572
Test name
Test status
Simulation time 69951030 ps
CPU time 1 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:48 PM PDT 24
Peak memory 201112 kb
Host smart-0713565e-1350-4835-9a87-27b784db55ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496699532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.3496699532
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.1025280005
Short name T114
Test name
Test status
Simulation time 16447714376 ps
CPU time 55.15 seconds
Started Aug 06 07:28:48 PM PDT 24
Finished Aug 06 07:29:44 PM PDT 24
Peak memory 201436 kb
Host smart-73809c9e-2263-449b-a048-13a7094e5eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025280005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.1025280005
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.3268521033
Short name T691
Test name
Test status
Simulation time 22975588 ps
CPU time 0.82 seconds
Started Aug 06 07:28:43 PM PDT 24
Finished Aug 06 07:28:44 PM PDT 24
Peak memory 201084 kb
Host smart-de85dd10-60dc-4662-902f-3690869e3587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268521033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3268521033
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.4167712110
Short name T424
Test name
Test status
Simulation time 23923035 ps
CPU time 0.8 seconds
Started Aug 06 07:27:16 PM PDT 24
Finished Aug 06 07:27:17 PM PDT 24
Peak memory 200772 kb
Host smart-5bded099-b6f7-45ec-9d4c-fe5ce669a4bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167712110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.4167712110
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.3860755700
Short name T378
Test name
Test status
Simulation time 26894236 ps
CPU time 0.97 seconds
Started Aug 06 07:27:15 PM PDT 24
Finished Aug 06 07:27:16 PM PDT 24
Peak memory 201016 kb
Host smart-fb4ea0c5-2182-44b2-aae3-2d29b213e41c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860755700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.3860755700
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.1577397340
Short name T36
Test name
Test status
Simulation time 15951993 ps
CPU time 0.72 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:14 PM PDT 24
Peak memory 200328 kb
Host smart-9da114ee-0ddc-4b9b-8830-b92a9038ccb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577397340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1577397340
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.2609662863
Short name T324
Test name
Test status
Simulation time 43409654 ps
CPU time 0.83 seconds
Started Aug 06 07:27:11 PM PDT 24
Finished Aug 06 07:27:12 PM PDT 24
Peak memory 201088 kb
Host smart-f9a6b604-4e64-4fcd-829b-02e7e23e7edd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609662863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.2609662863
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.369893964
Short name T452
Test name
Test status
Simulation time 56649680 ps
CPU time 0.95 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 201120 kb
Host smart-17e13ac0-9b61-45f1-90b3-e76bb08b4ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369893964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.369893964
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.1297036642
Short name T828
Test name
Test status
Simulation time 1157046189 ps
CPU time 9.17 seconds
Started Aug 06 07:26:54 PM PDT 24
Finished Aug 06 07:27:03 PM PDT 24
Peak memory 201176 kb
Host smart-c373fdf6-4109-4549-8146-f0596d1dcf61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297036642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1297036642
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.1504551591
Short name T350
Test name
Test status
Simulation time 258913158 ps
CPU time 2.43 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:27:00 PM PDT 24
Peak memory 201164 kb
Host smart-e518cc97-bfd5-4f75-aa9c-8c24fe52e303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504551591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.1504551591
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.3078935494
Short name T478
Test name
Test status
Simulation time 35519456 ps
CPU time 0.85 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:14 PM PDT 24
Peak memory 201088 kb
Host smart-2c9e64ba-53b2-4452-959a-d965ccfbb281
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078935494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.3078935494
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2641169508
Short name T331
Test name
Test status
Simulation time 19613314 ps
CPU time 0.74 seconds
Started Aug 06 07:27:11 PM PDT 24
Finished Aug 06 07:27:11 PM PDT 24
Peak memory 200992 kb
Host smart-0893ea02-fc75-413d-a981-f8123319b759
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641169508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.2641169508
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.557463745
Short name T552
Test name
Test status
Simulation time 68102996 ps
CPU time 0.98 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:14 PM PDT 24
Peak memory 201160 kb
Host smart-db379432-24fd-430a-9d6c-6e9ea2236dbb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557463745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.clkmgr_lc_ctrl_intersig_mubi.557463745
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.3478689996
Short name T696
Test name
Test status
Simulation time 58610632 ps
CPU time 0.87 seconds
Started Aug 06 07:26:58 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 201004 kb
Host smart-cfb1d0fb-e087-411b-a279-9ec9515fbaff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478689996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.3478689996
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.4225681233
Short name T780
Test name
Test status
Simulation time 699384348 ps
CPU time 3.27 seconds
Started Aug 06 07:27:16 PM PDT 24
Finished Aug 06 07:27:20 PM PDT 24
Peak memory 201304 kb
Host smart-ecf4ffae-dac5-4440-a22b-687b3ca4eaa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225681233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.4225681233
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.1530114149
Short name T40
Test name
Test status
Simulation time 165000230 ps
CPU time 2.09 seconds
Started Aug 06 07:27:16 PM PDT 24
Finished Aug 06 07:27:18 PM PDT 24
Peak memory 216540 kb
Host smart-dd94d3b0-93e8-4b4f-9145-b786d5ef935a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530114149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.1530114149
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.1904970663
Short name T144
Test name
Test status
Simulation time 78251588 ps
CPU time 1.05 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 201064 kb
Host smart-9ea596c7-6475-4cf7-9cdf-b15c5a72647b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904970663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.1904970663
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.2562534357
Short name T620
Test name
Test status
Simulation time 8677438631 ps
CPU time 67.69 seconds
Started Aug 06 07:27:11 PM PDT 24
Finished Aug 06 07:28:19 PM PDT 24
Peak memory 201704 kb
Host smart-9849ec1e-01df-4f15-9b4e-c4305670b7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562534357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.2562534357
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.3673581016
Short name T823
Test name
Test status
Simulation time 21716886 ps
CPU time 0.78 seconds
Started Aug 06 07:27:11 PM PDT 24
Finished Aug 06 07:27:12 PM PDT 24
Peak memory 201124 kb
Host smart-5d0bf3f2-fde1-4a77-9e26-60e717589ac7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673581016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.3673581016
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.1020384897
Short name T510
Test name
Test status
Simulation time 16591525 ps
CPU time 0.81 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:48 PM PDT 24
Peak memory 201040 kb
Host smart-5fc2af0d-75b6-40ea-bc7c-84c7661c75c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020384897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.1020384897
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.1109512431
Short name T98
Test name
Test status
Simulation time 24383695 ps
CPU time 0.92 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:48 PM PDT 24
Peak memory 201096 kb
Host smart-d458b090-f661-44d7-91e8-20352c2f1382
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109512431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.1109512431
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.1612058968
Short name T817
Test name
Test status
Simulation time 17147100 ps
CPU time 0.75 seconds
Started Aug 06 07:28:48 PM PDT 24
Finished Aug 06 07:28:49 PM PDT 24
Peak memory 200272 kb
Host smart-16af5772-5510-4e56-b019-485cebbe412f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612058968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1612058968
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.4177271099
Short name T283
Test name
Test status
Simulation time 20975293 ps
CPU time 0.85 seconds
Started Aug 06 07:28:50 PM PDT 24
Finished Aug 06 07:28:51 PM PDT 24
Peak memory 201084 kb
Host smart-066caf29-1ec7-4a51-9326-6d004fd1815f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177271099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.4177271099
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.61468143
Short name T286
Test name
Test status
Simulation time 61086449 ps
CPU time 0.94 seconds
Started Aug 06 07:28:50 PM PDT 24
Finished Aug 06 07:28:51 PM PDT 24
Peak memory 201036 kb
Host smart-1bb65393-71c8-4931-a477-d541a01a3d05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61468143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.61468143
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.814364674
Short name T10
Test name
Test status
Simulation time 1397817744 ps
CPU time 10.9 seconds
Started Aug 06 07:28:44 PM PDT 24
Finished Aug 06 07:28:56 PM PDT 24
Peak memory 201192 kb
Host smart-79c1b97d-d3fe-49e6-8cb8-a5408ead8e52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814364674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.814364674
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.1073130080
Short name T377
Test name
Test status
Simulation time 493638997 ps
CPU time 4.39 seconds
Started Aug 06 07:28:46 PM PDT 24
Finished Aug 06 07:28:51 PM PDT 24
Peak memory 201268 kb
Host smart-22663fc8-22b2-4398-9f77-7bfca29828d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073130080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.1073130080
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.3043121924
Short name T535
Test name
Test status
Simulation time 46436232 ps
CPU time 0.96 seconds
Started Aug 06 07:28:43 PM PDT 24
Finished Aug 06 07:28:44 PM PDT 24
Peak memory 201144 kb
Host smart-0393c1a2-a2d3-4829-a337-82a5220096a1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043121924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.3043121924
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2478965491
Short name T781
Test name
Test status
Simulation time 68443163 ps
CPU time 1 seconds
Started Aug 06 07:28:44 PM PDT 24
Finished Aug 06 07:28:45 PM PDT 24
Peak memory 200948 kb
Host smart-b0f61402-4697-43ff-8660-bbeda124c15f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478965491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2478965491
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1860876843
Short name T815
Test name
Test status
Simulation time 22834070 ps
CPU time 0.88 seconds
Started Aug 06 07:28:44 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201112 kb
Host smart-a78cb0c2-23c6-427d-9a7e-793b7929a3fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860876843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.1860876843
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.301775271
Short name T463
Test name
Test status
Simulation time 20686286 ps
CPU time 0.74 seconds
Started Aug 06 07:28:46 PM PDT 24
Finished Aug 06 07:28:47 PM PDT 24
Peak memory 201084 kb
Host smart-76331268-ed79-477c-93be-cc0738323212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301775271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.301775271
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.706659005
Short name T604
Test name
Test status
Simulation time 176270223 ps
CPU time 1.65 seconds
Started Aug 06 07:28:49 PM PDT 24
Finished Aug 06 07:28:51 PM PDT 24
Peak memory 201088 kb
Host smart-8bf2b4c6-ed3b-432d-83b8-f87b4dadfaed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706659005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.706659005
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.3515212537
Short name T466
Test name
Test status
Simulation time 21876102 ps
CPU time 0.87 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201084 kb
Host smart-ce1f4afc-b7da-4e63-834c-cae7b9589743
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515212537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3515212537
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.1165851840
Short name T44
Test name
Test status
Simulation time 378372631 ps
CPU time 2.51 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:49 PM PDT 24
Peak memory 201192 kb
Host smart-f7a66a1b-082e-4b8d-b319-241da04cb121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165851840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.1165851840
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.1675564094
Short name T373
Test name
Test status
Simulation time 27011002 ps
CPU time 0.94 seconds
Started Aug 06 07:28:46 PM PDT 24
Finished Aug 06 07:28:47 PM PDT 24
Peak memory 201064 kb
Host smart-d6405bde-7072-4481-acab-b34c3a1c0cfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675564094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.1675564094
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.1855062506
Short name T272
Test name
Test status
Simulation time 23292194 ps
CPU time 0.76 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201092 kb
Host smart-15627c3d-30a5-421a-8947-34e8936da06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855062506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.1855062506
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2754448218
Short name T513
Test name
Test status
Simulation time 75437567 ps
CPU time 1.02 seconds
Started Aug 06 07:29:13 PM PDT 24
Finished Aug 06 07:29:14 PM PDT 24
Peak memory 201092 kb
Host smart-85c6371e-bc3f-46cb-b5af-37c3735e7819
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754448218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.2754448218
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.173906906
Short name T498
Test name
Test status
Simulation time 30969269 ps
CPU time 0.74 seconds
Started Aug 06 07:28:50 PM PDT 24
Finished Aug 06 07:28:51 PM PDT 24
Peak memory 200300 kb
Host smart-3dcf4316-3162-4f56-84e7-e55f8af1aacf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173906906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.173906906
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.2045163268
Short name T303
Test name
Test status
Simulation time 21262087 ps
CPU time 0.88 seconds
Started Aug 06 07:29:08 PM PDT 24
Finished Aug 06 07:29:09 PM PDT 24
Peak memory 201052 kb
Host smart-14111bce-335f-49b1-b31b-7fc269b7187b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045163268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.2045163268
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.1356165850
Short name T470
Test name
Test status
Simulation time 17795430 ps
CPU time 0.8 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201048 kb
Host smart-87b7510b-9821-4d7a-ac5c-a10831d49847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356165850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1356165850
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.2116740531
Short name T768
Test name
Test status
Simulation time 584759158 ps
CPU time 3.3 seconds
Started Aug 06 07:28:43 PM PDT 24
Finished Aug 06 07:28:47 PM PDT 24
Peak memory 201188 kb
Host smart-a16409fa-47a8-46e2-9584-68880d15a6c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116740531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2116740531
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.1514998096
Short name T323
Test name
Test status
Simulation time 164943626 ps
CPU time 1.24 seconds
Started Aug 06 07:28:49 PM PDT 24
Finished Aug 06 07:28:50 PM PDT 24
Peak memory 201176 kb
Host smart-7923518c-73d4-4097-884d-01026f16c406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514998096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.1514998096
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.112768576
Short name T319
Test name
Test status
Simulation time 19860261 ps
CPU time 0.82 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 200928 kb
Host smart-754207ed-c4a3-43d4-89cb-d97a0e807cf4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112768576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_idle_intersig_mubi.112768576
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.3904464313
Short name T193
Test name
Test status
Simulation time 109501760 ps
CPU time 1.06 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 201092 kb
Host smart-0af0c328-1ad0-42fb-b614-ff45ea24019d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904464313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.3904464313
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.2913239908
Short name T493
Test name
Test status
Simulation time 46111064 ps
CPU time 0.83 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 201044 kb
Host smart-306a0559-0eba-4dfc-abad-90e4d1e7e725
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913239908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.2913239908
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.2073960827
Short name T268
Test name
Test status
Simulation time 18160074 ps
CPU time 0.79 seconds
Started Aug 06 07:28:50 PM PDT 24
Finished Aug 06 07:28:51 PM PDT 24
Peak memory 201080 kb
Host smart-86223107-8f77-4792-908b-0cb6799601d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073960827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.2073960827
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.353186220
Short name T159
Test name
Test status
Simulation time 1272611596 ps
CPU time 7.11 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:17 PM PDT 24
Peak memory 201272 kb
Host smart-b05d0c04-074c-49fe-9508-799cab0fd20d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353186220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.353186220
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.3863581352
Short name T713
Test name
Test status
Simulation time 117621513 ps
CPU time 1.17 seconds
Started Aug 06 07:28:45 PM PDT 24
Finished Aug 06 07:28:46 PM PDT 24
Peak memory 200892 kb
Host smart-15e3e0a7-edf2-400b-b72d-c9780782a9e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863581352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.3863581352
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.3013088934
Short name T524
Test name
Test status
Simulation time 1258587563 ps
CPU time 5.37 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:17 PM PDT 24
Peak memory 201424 kb
Host smart-69e2db4d-3de3-4344-90ab-ad4338599715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013088934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.3013088934
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.3868724243
Short name T71
Test name
Test status
Simulation time 94710189681 ps
CPU time 566.05 seconds
Started Aug 06 07:29:09 PM PDT 24
Finished Aug 06 07:38:35 PM PDT 24
Peak memory 209760 kb
Host smart-74db7184-5b4f-4d81-888a-67000693b07f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3868724243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.3868724243
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.clkmgr_trans.444638541
Short name T415
Test name
Test status
Simulation time 47518745 ps
CPU time 0.84 seconds
Started Aug 06 07:28:47 PM PDT 24
Finished Aug 06 07:28:48 PM PDT 24
Peak memory 201080 kb
Host smart-28b67fcd-4d9e-4091-aa84-056fd65cd2df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444638541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.444638541
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.247586765
Short name T563
Test name
Test status
Simulation time 13649670 ps
CPU time 0.76 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201160 kb
Host smart-1cb93afa-4e5d-4bdb-90db-7335ac0d5ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247586765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkm
gr_alert_test.247586765
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.1740621361
Short name T168
Test name
Test status
Simulation time 20828681 ps
CPU time 0.82 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201112 kb
Host smart-8c05987e-0b9e-4bb1-86c8-cc75f2fb606b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740621361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.1740621361
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.3665877594
Short name T744
Test name
Test status
Simulation time 39869613 ps
CPU time 0.75 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 200272 kb
Host smart-e2cb36ab-0d7f-4482-a94a-ac3316e82498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665877594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3665877594
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.1159669511
Short name T603
Test name
Test status
Simulation time 20669234 ps
CPU time 0.83 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201120 kb
Host smart-54543fa6-8583-4bce-a44b-00e81f15f4a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159669511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.1159669511
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.4069056780
Short name T715
Test name
Test status
Simulation time 21612334 ps
CPU time 0.74 seconds
Started Aug 06 07:29:09 PM PDT 24
Finished Aug 06 07:29:10 PM PDT 24
Peak memory 201040 kb
Host smart-fb38a0cf-3a0d-409e-ac3a-e869c410b4d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069056780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.4069056780
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.198132086
Short name T617
Test name
Test status
Simulation time 2242533976 ps
CPU time 17.16 seconds
Started Aug 06 07:29:15 PM PDT 24
Finished Aug 06 07:29:32 PM PDT 24
Peak memory 201396 kb
Host smart-1619371c-d02b-4d5b-87b0-e512b918e0f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198132086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.198132086
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.1224653840
Short name T686
Test name
Test status
Simulation time 182469594 ps
CPU time 1.23 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 201468 kb
Host smart-4b2b6669-ac91-4cae-8784-b7affea841aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224653840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.1224653840
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.3149565965
Short name T116
Test name
Test status
Simulation time 66908688 ps
CPU time 1.13 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 201084 kb
Host smart-e23b0f5e-1f0e-447d-8984-c949c9fdd2f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149565965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.3149565965
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2206256193
Short name T777
Test name
Test status
Simulation time 90351980 ps
CPU time 1.09 seconds
Started Aug 06 07:29:13 PM PDT 24
Finished Aug 06 07:29:14 PM PDT 24
Peak memory 200992 kb
Host smart-587e969f-189c-43c3-a306-14882b2ecd30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206256193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2206256193
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.398962205
Short name T154
Test name
Test status
Simulation time 94722150 ps
CPU time 1.08 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201000 kb
Host smart-9426816e-adc5-4ac7-805c-11e9ef8f3271
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398962205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.clkmgr_lc_ctrl_intersig_mubi.398962205
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.3197829621
Short name T254
Test name
Test status
Simulation time 16010732 ps
CPU time 0.77 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 201060 kb
Host smart-4067f5a5-5757-41ba-a733-31fdfbec4639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197829621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3197829621
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.3149087417
Short name T312
Test name
Test status
Simulation time 1281414485 ps
CPU time 5.57 seconds
Started Aug 06 07:29:09 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 201320 kb
Host smart-844a28ee-48ed-433b-bd67-b322f005fb2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149087417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.3149087417
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.631106853
Short name T369
Test name
Test status
Simulation time 72473779 ps
CPU time 1 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201092 kb
Host smart-254d13fb-8ce0-4954-ac20-ee6bc1cb4f4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631106853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.631106853
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.2907379894
Short name T352
Test name
Test status
Simulation time 2160035970 ps
CPU time 17.74 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:32 PM PDT 24
Peak memory 201656 kb
Host smart-14b3b1f4-5244-4341-becf-8882e2d1d114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907379894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.2907379894
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.1024532070
Short name T282
Test name
Test status
Simulation time 31770278 ps
CPU time 1.01 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201132 kb
Host smart-cc00f992-0508-438f-9cb6-0775e30c4735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024532070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1024532070
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.3463915726
Short name T393
Test name
Test status
Simulation time 91354876 ps
CPU time 0.98 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201104 kb
Host smart-d9a273b0-6328-44a4-9973-4e4302fa180b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463915726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.3463915726
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2133452207
Short name T55
Test name
Test status
Simulation time 14192766 ps
CPU time 0.75 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 201052 kb
Host smart-1f76bade-f48f-4a1f-a872-c2a615df2af9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133452207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.2133452207
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.1211246313
Short name T417
Test name
Test status
Simulation time 48982628 ps
CPU time 0.79 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 200924 kb
Host smart-ae12a658-0c20-4cd6-ba9c-1e59ebf68944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211246313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1211246313
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.342804367
Short name T630
Test name
Test status
Simulation time 38714382 ps
CPU time 0.94 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 201048 kb
Host smart-1fd45d0d-60a7-4ea8-b28e-04ce4aa2ba29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342804367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.clkmgr_div_intersig_mubi.342804367
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.2527076199
Short name T525
Test name
Test status
Simulation time 22613883 ps
CPU time 0.76 seconds
Started Aug 06 07:29:08 PM PDT 24
Finished Aug 06 07:29:09 PM PDT 24
Peak memory 200984 kb
Host smart-1b3d3dbd-7ee5-456d-9ee9-d5d9d166b977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527076199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.2527076199
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.19018520
Short name T745
Test name
Test status
Simulation time 1876965991 ps
CPU time 14.3 seconds
Started Aug 06 07:29:08 PM PDT 24
Finished Aug 06 07:29:23 PM PDT 24
Peak memory 201300 kb
Host smart-b10300f6-d5e3-4d50-8a6b-66c5805c4bb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19018520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.19018520
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.3292627586
Short name T678
Test name
Test status
Simulation time 260818102 ps
CPU time 2.04 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:14 PM PDT 24
Peak memory 201260 kb
Host smart-3fff7a8e-5a00-4833-b49e-9f811b6e99e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292627586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.3292627586
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2167248980
Short name T747
Test name
Test status
Simulation time 30178537 ps
CPU time 1.02 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 200988 kb
Host smart-4033b3ec-e4ec-465b-ae54-f885d4a55e73
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167248980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.2167248980
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3258623995
Short name T542
Test name
Test status
Simulation time 16552147 ps
CPU time 0.78 seconds
Started Aug 06 07:29:13 PM PDT 24
Finished Aug 06 07:29:14 PM PDT 24
Peak memory 201064 kb
Host smart-2ee4ae93-9356-4b5f-9ed1-8bc3b5bbb880
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258623995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3258623995
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3421962886
Short name T765
Test name
Test status
Simulation time 27967563 ps
CPU time 0.83 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201100 kb
Host smart-601ca56f-c971-4c81-ba0d-d19a6b50bb76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421962886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.3421962886
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.1591118543
Short name T474
Test name
Test status
Simulation time 18871800 ps
CPU time 0.73 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201120 kb
Host smart-e695bc02-0628-401b-a8e6-aed644c8ed8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591118543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1591118543
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.1168370070
Short name T674
Test name
Test status
Simulation time 1416360573 ps
CPU time 5.45 seconds
Started Aug 06 07:29:09 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 201280 kb
Host smart-beabd208-40c7-4e35-8434-becd472251b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168370070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.1168370070
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.1940005994
Short name T456
Test name
Test status
Simulation time 17617859 ps
CPU time 0.82 seconds
Started Aug 06 07:29:13 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201032 kb
Host smart-c2301d6c-1813-4417-b29b-b03cfe484cb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940005994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1940005994
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.1981713996
Short name T316
Test name
Test status
Simulation time 615653426 ps
CPU time 3.96 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:18 PM PDT 24
Peak memory 201484 kb
Host smart-42398a5c-2e8f-45aa-b090-d3c5947a0be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981713996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.1981713996
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_trans.4132166629
Short name T271
Test name
Test status
Simulation time 32452160 ps
CPU time 0.93 seconds
Started Aug 06 07:29:08 PM PDT 24
Finished Aug 06 07:29:09 PM PDT 24
Peak memory 201036 kb
Host smart-4947992c-8cb5-4a5a-a52d-bfe3f9e9a336
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132166629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.4132166629
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.2521273704
Short name T721
Test name
Test status
Simulation time 50519987 ps
CPU time 0.84 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201060 kb
Host smart-8018531d-2eff-46cc-874c-dd5a8b607451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521273704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.2521273704
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3510421274
Short name T234
Test name
Test status
Simulation time 75056873 ps
CPU time 1.01 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201124 kb
Host smart-481a61b7-5fe8-4aa2-958f-943c8fe001fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510421274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3510421274
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.3287874547
Short name T772
Test name
Test status
Simulation time 17109177 ps
CPU time 0.75 seconds
Started Aug 06 07:29:09 PM PDT 24
Finished Aug 06 07:29:10 PM PDT 24
Peak memory 200996 kb
Host smart-242c3587-c3d6-484f-8d40-48dd302b0ae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287874547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3287874547
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1290374383
Short name T704
Test name
Test status
Simulation time 307473527 ps
CPU time 1.69 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201140 kb
Host smart-738391d8-8357-4d35-94bb-46a6505bfc2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290374383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.1290374383
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2321531011
Short name T794
Test name
Test status
Simulation time 55715388 ps
CPU time 0.92 seconds
Started Aug 06 07:29:09 PM PDT 24
Finished Aug 06 07:29:10 PM PDT 24
Peak memory 201044 kb
Host smart-7badd715-83ed-45aa-9764-e85e8be07e65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321531011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2321531011
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.1966376489
Short name T496
Test name
Test status
Simulation time 1719673259 ps
CPU time 8.14 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:18 PM PDT 24
Peak memory 201208 kb
Host smart-4bc35d55-418d-4cca-8b9c-a256452d3033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966376489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1966376489
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.1287895020
Short name T450
Test name
Test status
Simulation time 743341784 ps
CPU time 5.58 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:20 PM PDT 24
Peak memory 201180 kb
Host smart-b380f6e2-f6ef-44dc-a62c-f898f426fa00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287895020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.1287895020
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3358457363
Short name T356
Test name
Test status
Simulation time 32584767 ps
CPU time 0.95 seconds
Started Aug 06 07:29:08 PM PDT 24
Finished Aug 06 07:29:09 PM PDT 24
Peak memory 201048 kb
Host smart-e64c2c00-c9d9-402a-bbfa-8d7520b5c89e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358457363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3358457363
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2280178718
Short name T707
Test name
Test status
Simulation time 18917125 ps
CPU time 0.77 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:10 PM PDT 24
Peak memory 201056 kb
Host smart-5f7dd996-cb2d-4290-8d28-2e25cf07660a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280178718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.2280178718
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.4101390651
Short name T528
Test name
Test status
Simulation time 75435658 ps
CPU time 0.93 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 201136 kb
Host smart-1c92c9a8-da36-497c-b0e2-d3628b5e3452
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101390651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.4101390651
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.795491788
Short name T250
Test name
Test status
Simulation time 25449408 ps
CPU time 0.79 seconds
Started Aug 06 07:29:09 PM PDT 24
Finished Aug 06 07:29:10 PM PDT 24
Peak memory 201040 kb
Host smart-4d609e3d-1d14-4a1e-bb66-3ae9a4a23ba3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795491788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.795491788
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.1115764710
Short name T800
Test name
Test status
Simulation time 516354352 ps
CPU time 3.46 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 201312 kb
Host smart-4acaec6c-58df-49d0-899e-ffd831bdc492
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115764710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.1115764710
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.843136336
Short name T730
Test name
Test status
Simulation time 16618157 ps
CPU time 0.8 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201100 kb
Host smart-6819697f-a508-431e-a7a8-afc54afd84e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843136336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.843136336
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.2930218225
Short name T746
Test name
Test status
Simulation time 3465422268 ps
CPU time 19.59 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:34 PM PDT 24
Peak memory 201696 kb
Host smart-921cf56a-7ec3-4344-949d-f1babb238d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930218225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.2930218225
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2513263628
Short name T551
Test name
Test status
Simulation time 22501838 ps
CPU time 0.87 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 201096 kb
Host smart-07b03328-192f-4d58-ba75-dc5e49fdfbe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513263628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2513263628
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.583918639
Short name T519
Test name
Test status
Simulation time 79468139 ps
CPU time 0.94 seconds
Started Aug 06 07:29:26 PM PDT 24
Finished Aug 06 07:29:27 PM PDT 24
Peak memory 201032 kb
Host smart-ad2c5906-f0ce-47be-a4a0-553738d42471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583918639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkm
gr_alert_test.583918639
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1202316249
Short name T637
Test name
Test status
Simulation time 18202449 ps
CPU time 0.79 seconds
Started Aug 06 07:29:26 PM PDT 24
Finished Aug 06 07:29:27 PM PDT 24
Peak memory 201104 kb
Host smart-30aad323-d7e9-436a-969c-30d0558c8b36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202316249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.1202316249
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.4278989335
Short name T302
Test name
Test status
Simulation time 28992960 ps
CPU time 0.8 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 200224 kb
Host smart-fce2f506-97dc-48e4-b8de-179305a6a30f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278989335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.4278989335
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.1649711015
Short name T527
Test name
Test status
Simulation time 25967243 ps
CPU time 0.8 seconds
Started Aug 06 07:29:28 PM PDT 24
Finished Aug 06 07:29:29 PM PDT 24
Peak memory 201032 kb
Host smart-014ef41d-8670-4dc2-91be-9c7fd7559242
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649711015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.1649711015
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.2822908610
Short name T392
Test name
Test status
Simulation time 171849989 ps
CPU time 1.32 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 200988 kb
Host smart-d652b6b0-e829-47e6-b453-5adc14a075d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822908610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.2822908610
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.2113866879
Short name T567
Test name
Test status
Simulation time 2242929774 ps
CPU time 17.93 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:28 PM PDT 24
Peak memory 201400 kb
Host smart-9065189b-b9ae-4d68-a1c6-2fa818083c53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113866879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.2113866879
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.2247820133
Short name T205
Test name
Test status
Simulation time 140887925 ps
CPU time 1.67 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 201232 kb
Host smart-aa916a3a-82ed-4b18-b50f-6b0078a43d9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247820133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.2247820133
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3956379188
Short name T299
Test name
Test status
Simulation time 47397644 ps
CPU time 0.88 seconds
Started Aug 06 07:29:14 PM PDT 24
Finished Aug 06 07:29:15 PM PDT 24
Peak memory 201132 kb
Host smart-0fe4b57a-2e5a-48a9-a7f5-12e78fcc5a03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956379188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3956379188
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1197063574
Short name T695
Test name
Test status
Simulation time 18464789 ps
CPU time 0.81 seconds
Started Aug 06 07:29:13 PM PDT 24
Finished Aug 06 07:29:14 PM PDT 24
Peak memory 201048 kb
Host smart-05c8e5b3-a975-49f5-8d57-26eb958be442
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197063574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1197063574
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2837990569
Short name T464
Test name
Test status
Simulation time 21161492 ps
CPU time 0.85 seconds
Started Aug 06 07:29:10 PM PDT 24
Finished Aug 06 07:29:11 PM PDT 24
Peak memory 201104 kb
Host smart-f1897630-9643-40a0-be29-34f4aadaf5c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837990569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.2837990569
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.4234146694
Short name T20
Test name
Test status
Simulation time 16343659 ps
CPU time 0.8 seconds
Started Aug 06 07:29:12 PM PDT 24
Finished Aug 06 07:29:13 PM PDT 24
Peak memory 201048 kb
Host smart-14092c30-397d-4ad8-9a84-424d12329b25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234146694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.4234146694
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.1573151456
Short name T115
Test name
Test status
Simulation time 188270449 ps
CPU time 1.64 seconds
Started Aug 06 07:29:27 PM PDT 24
Finished Aug 06 07:29:29 PM PDT 24
Peak memory 201048 kb
Host smart-9c8bc2b8-915c-47f1-b3af-f245462c391d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573151456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.1573151456
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2141723597
Short name T822
Test name
Test status
Simulation time 129029249 ps
CPU time 1.14 seconds
Started Aug 06 07:29:13 PM PDT 24
Finished Aug 06 07:29:14 PM PDT 24
Peak memory 201084 kb
Host smart-865f8924-c667-4c31-b036-68738f4b6ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141723597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2141723597
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.1464881998
Short name T487
Test name
Test status
Simulation time 7729262945 ps
CPU time 27.27 seconds
Started Aug 06 07:29:27 PM PDT 24
Finished Aug 06 07:29:54 PM PDT 24
Peak memory 201444 kb
Host smart-b07352cd-8eb7-42e0-be3b-cf8a6542819d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464881998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.1464881998
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.2245279251
Short name T425
Test name
Test status
Simulation time 39291191 ps
CPU time 0.89 seconds
Started Aug 06 07:29:11 PM PDT 24
Finished Aug 06 07:29:12 PM PDT 24
Peak memory 201132 kb
Host smart-a18c5632-221a-4310-870f-ee32985c33c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245279251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2245279251
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.1622351784
Short name T602
Test name
Test status
Simulation time 54653236 ps
CPU time 0.89 seconds
Started Aug 06 07:29:28 PM PDT 24
Finished Aug 06 07:29:29 PM PDT 24
Peak memory 200952 kb
Host smart-99f4dd37-c71d-40e7-ae4c-7a8dce486892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622351784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.1622351784
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2105901357
Short name T679
Test name
Test status
Simulation time 22025730 ps
CPU time 0.89 seconds
Started Aug 06 07:29:30 PM PDT 24
Finished Aug 06 07:29:31 PM PDT 24
Peak memory 201152 kb
Host smart-1e3b53c5-8cc1-4fce-af1e-8f3845ca8200
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105901357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.2105901357
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.1978491794
Short name T443
Test name
Test status
Simulation time 18867388 ps
CPU time 0.69 seconds
Started Aug 06 07:29:27 PM PDT 24
Finished Aug 06 07:29:28 PM PDT 24
Peak memory 200340 kb
Host smart-31be4abc-7764-41bd-aeca-665c2f37e25b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978491794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1978491794
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.4036207493
Short name T669
Test name
Test status
Simulation time 22110328 ps
CPU time 0.88 seconds
Started Aug 06 07:29:29 PM PDT 24
Finished Aug 06 07:29:30 PM PDT 24
Peak memory 201092 kb
Host smart-fe2ed571-eaf0-4497-b882-4f4c9fd54be6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036207493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.4036207493
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.3088934134
Short name T779
Test name
Test status
Simulation time 36263543 ps
CPU time 0.93 seconds
Started Aug 06 07:29:29 PM PDT 24
Finished Aug 06 07:29:30 PM PDT 24
Peak memory 200988 kb
Host smart-8aa5e6ee-f099-4f52-93b6-3f0b8c30ce8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088934134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.3088934134
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.1913037936
Short name T587
Test name
Test status
Simulation time 2480675844 ps
CPU time 13.41 seconds
Started Aug 06 07:29:29 PM PDT 24
Finished Aug 06 07:29:42 PM PDT 24
Peak memory 201476 kb
Host smart-664fbaf3-ec92-4d00-bdfc-415688bde1e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913037936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.1913037936
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.1698717692
Short name T43
Test name
Test status
Simulation time 736821266 ps
CPU time 6.07 seconds
Started Aug 06 07:29:28 PM PDT 24
Finished Aug 06 07:29:34 PM PDT 24
Peak memory 201100 kb
Host smart-6ea98f22-eb42-4966-8aeb-f1de1945b240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698717692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.1698717692
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.218173403
Short name T206
Test name
Test status
Simulation time 23558258 ps
CPU time 0.79 seconds
Started Aug 06 07:29:30 PM PDT 24
Finished Aug 06 07:29:31 PM PDT 24
Peak memory 201072 kb
Host smart-8f2695d8-0d67-416c-b596-edc90ce7cae1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218173403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_idle_intersig_mubi.218173403
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.1546687178
Short name T414
Test name
Test status
Simulation time 32286847 ps
CPU time 0.81 seconds
Started Aug 06 07:29:28 PM PDT 24
Finished Aug 06 07:29:29 PM PDT 24
Peak memory 201028 kb
Host smart-0fa427c8-b326-477c-9c48-e1e7491ba30e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546687178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.1546687178
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.3145537431
Short name T22
Test name
Test status
Simulation time 16557035 ps
CPU time 0.78 seconds
Started Aug 06 07:29:29 PM PDT 24
Finished Aug 06 07:29:30 PM PDT 24
Peak memory 201088 kb
Host smart-504f319a-b7ae-48e1-be77-bd01df69e899
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145537431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.3145537431
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.603724419
Short name T565
Test name
Test status
Simulation time 15613556 ps
CPU time 0.77 seconds
Started Aug 06 07:29:27 PM PDT 24
Finished Aug 06 07:29:28 PM PDT 24
Peak memory 201076 kb
Host smart-283e4a73-4ee5-4a75-b64c-b9f54adee104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603724419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.603724419
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.937639855
Short name T694
Test name
Test status
Simulation time 120874981 ps
CPU time 1.22 seconds
Started Aug 06 07:29:30 PM PDT 24
Finished Aug 06 07:29:31 PM PDT 24
Peak memory 201156 kb
Host smart-5ca1a7f3-52bc-4419-b53d-4d87e79e6694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937639855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.937639855
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.416422532
Short name T558
Test name
Test status
Simulation time 58614755 ps
CPU time 0.97 seconds
Started Aug 06 07:29:27 PM PDT 24
Finished Aug 06 07:29:28 PM PDT 24
Peak memory 201076 kb
Host smart-787849c0-aba0-4ad8-9eb6-21eed78e89a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416422532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.416422532
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.2110937976
Short name T145
Test name
Test status
Simulation time 2973930013 ps
CPU time 18.98 seconds
Started Aug 06 07:29:28 PM PDT 24
Finished Aug 06 07:29:47 PM PDT 24
Peak memory 201428 kb
Host smart-74c9a459-661b-42ec-a857-729dc5628d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110937976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.2110937976
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.3137567889
Short name T117
Test name
Test status
Simulation time 88207630 ps
CPU time 0.98 seconds
Started Aug 06 07:29:27 PM PDT 24
Finished Aug 06 07:29:28 PM PDT 24
Peak memory 201084 kb
Host smart-81de9ecc-df0d-48c3-849d-12d6c53f815d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137567889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3137567889
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.2321969452
Short name T413
Test name
Test status
Simulation time 125375871 ps
CPU time 1.14 seconds
Started Aug 06 07:29:32 PM PDT 24
Finished Aug 06 07:29:33 PM PDT 24
Peak memory 201012 kb
Host smart-e64d05be-b0eb-4a1b-af5d-4f73ed3f41fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321969452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.2321969452
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.55523297
Short name T633
Test name
Test status
Simulation time 24255009 ps
CPU time 0.88 seconds
Started Aug 06 07:29:30 PM PDT 24
Finished Aug 06 07:29:31 PM PDT 24
Peak memory 200988 kb
Host smart-ae43943c-bedb-4a53-8414-42488200251f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55523297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_clk_handshake_intersig_mubi.55523297
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.1593116843
Short name T177
Test name
Test status
Simulation time 37488709 ps
CPU time 0.75 seconds
Started Aug 06 07:29:33 PM PDT 24
Finished Aug 06 07:29:33 PM PDT 24
Peak memory 200300 kb
Host smart-2b99623c-e882-4c47-b39d-9e0a46fff80d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593116843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1593116843
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3065746854
Short name T204
Test name
Test status
Simulation time 38554301 ps
CPU time 0.92 seconds
Started Aug 06 07:29:34 PM PDT 24
Finished Aug 06 07:29:35 PM PDT 24
Peak memory 201076 kb
Host smart-1463fdbe-2754-433a-9ef5-d1c9d9bbff2a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065746854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3065746854
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.650099571
Short name T471
Test name
Test status
Simulation time 14688842 ps
CPU time 0.75 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:32 PM PDT 24
Peak memory 201084 kb
Host smart-8d2243fa-7de3-44e4-b7d1-54df93ed0882
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650099571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.650099571
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.2978896577
Short name T1
Test name
Test status
Simulation time 1884136051 ps
CPU time 10.53 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:42 PM PDT 24
Peak memory 201308 kb
Host smart-ea9623e5-6112-49e1-9603-be8a0a571949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978896577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.2978896577
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.2677958344
Short name T235
Test name
Test status
Simulation time 1702960691 ps
CPU time 12.52 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:43 PM PDT 24
Peak memory 201164 kb
Host smart-89b432be-1022-4b1d-b5f7-f79624f752db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677958344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.2677958344
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.4261500956
Short name T531
Test name
Test status
Simulation time 125447670 ps
CPU time 1.29 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:32 PM PDT 24
Peak memory 201040 kb
Host smart-41ba3589-776c-4ee8-9caa-80b6edd1257c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261500956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.4261500956
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.4268981677
Short name T568
Test name
Test status
Simulation time 138927470 ps
CPU time 1.2 seconds
Started Aug 06 07:29:33 PM PDT 24
Finished Aug 06 07:29:34 PM PDT 24
Peak memory 201092 kb
Host smart-6cfe5c06-11b5-4025-ac92-7c8985ab2575
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268981677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.4268981677
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.2073388021
Short name T285
Test name
Test status
Simulation time 77446189 ps
CPU time 1.02 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:32 PM PDT 24
Peak memory 201052 kb
Host smart-52757420-0b56-41c8-98d8-1df92ef5fcb9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073388021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.2073388021
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.813480058
Short name T545
Test name
Test status
Simulation time 14539069 ps
CPU time 0.74 seconds
Started Aug 06 07:29:29 PM PDT 24
Finished Aug 06 07:29:30 PM PDT 24
Peak memory 201112 kb
Host smart-34934b96-6081-4ca2-8b70-bcd2c414fa22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813480058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.813480058
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.245158968
Short name T798
Test name
Test status
Simulation time 367345822 ps
CPU time 1.95 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:33 PM PDT 24
Peak memory 201088 kb
Host smart-ddaa8fa7-3cc9-4fde-8831-4d07a4beb59b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245158968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.245158968
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.3016297118
Short name T239
Test name
Test status
Simulation time 18933927 ps
CPU time 0.83 seconds
Started Aug 06 07:29:30 PM PDT 24
Finished Aug 06 07:29:31 PM PDT 24
Peak memory 201084 kb
Host smart-d43a16f8-97d6-4402-b4af-c5a44e6f0dbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016297118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3016297118
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.3903149123
Short name T11
Test name
Test status
Simulation time 1051092230 ps
CPU time 8.53 seconds
Started Aug 06 07:29:32 PM PDT 24
Finished Aug 06 07:29:40 PM PDT 24
Peak memory 201176 kb
Host smart-8a6d526e-9077-4184-97f7-162edd3476d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903149123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.3903149123
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_trans.3988875026
Short name T673
Test name
Test status
Simulation time 30353501 ps
CPU time 0.81 seconds
Started Aug 06 07:29:30 PM PDT 24
Finished Aug 06 07:29:31 PM PDT 24
Peak memory 201028 kb
Host smart-3d8b0f47-5cca-4940-8c63-e68820953404
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988875026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.3988875026
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.4003632317
Short name T208
Test name
Test status
Simulation time 39405878 ps
CPU time 0.8 seconds
Started Aug 06 07:29:29 PM PDT 24
Finished Aug 06 07:29:30 PM PDT 24
Peak memory 201072 kb
Host smart-07c9df6e-1786-47ca-a972-1e244aabfd4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003632317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.4003632317
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3398375254
Short name T726
Test name
Test status
Simulation time 142948433 ps
CPU time 1.17 seconds
Started Aug 06 07:29:33 PM PDT 24
Finished Aug 06 07:29:34 PM PDT 24
Peak memory 201112 kb
Host smart-827b6ece-63da-447f-8031-2f1757edf571
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398375254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.3398375254
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.2916236946
Short name T276
Test name
Test status
Simulation time 14163686 ps
CPU time 0.7 seconds
Started Aug 06 07:29:33 PM PDT 24
Finished Aug 06 07:29:34 PM PDT 24
Peak memory 201024 kb
Host smart-d08a8234-0eec-4fa6-9442-852b2cc21ee5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916236946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.2916236946
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.2501850327
Short name T156
Test name
Test status
Simulation time 92790437 ps
CPU time 1.15 seconds
Started Aug 06 07:29:33 PM PDT 24
Finished Aug 06 07:29:35 PM PDT 24
Peak memory 201092 kb
Host smart-3d57a405-26ec-464c-a1e5-3768cacbe3cc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501850327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.2501850327
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.211516412
Short name T486
Test name
Test status
Simulation time 19321389 ps
CPU time 0.82 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:32 PM PDT 24
Peak memory 201032 kb
Host smart-e185a4a7-6f48-4745-b0fd-a034f226ab5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211516412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.211516412
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.2314348130
Short name T306
Test name
Test status
Simulation time 1036636514 ps
CPU time 8.51 seconds
Started Aug 06 07:29:30 PM PDT 24
Finished Aug 06 07:29:38 PM PDT 24
Peak memory 201132 kb
Host smart-1a3188bc-63b1-4e35-955a-3c9a45c821a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314348130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2314348130
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.2530533688
Short name T333
Test name
Test status
Simulation time 765920102 ps
CPU time 3.51 seconds
Started Aug 06 07:29:34 PM PDT 24
Finished Aug 06 07:29:38 PM PDT 24
Peak memory 201176 kb
Host smart-9843f8f6-367f-4b71-8d19-78551096d0d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530533688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.2530533688
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.1451857841
Short name T221
Test name
Test status
Simulation time 71935082 ps
CPU time 1.07 seconds
Started Aug 06 07:29:32 PM PDT 24
Finished Aug 06 07:29:33 PM PDT 24
Peak memory 201168 kb
Host smart-e7a08612-ea9f-447e-a611-82c9b3b8fda3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451857841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.1451857841
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2307419702
Short name T28
Test name
Test status
Simulation time 16268672 ps
CPU time 0.78 seconds
Started Aug 06 07:29:34 PM PDT 24
Finished Aug 06 07:29:35 PM PDT 24
Peak memory 201060 kb
Host smart-190ebb97-ad3b-4bf6-9543-c40f51fca9af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307419702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.2307419702
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.2714036902
Short name T185
Test name
Test status
Simulation time 20469402 ps
CPU time 0.84 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:32 PM PDT 24
Peak memory 201032 kb
Host smart-66cfe29f-398c-4b01-9980-e7e04e30d45c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714036902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.2714036902
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.389589019
Short name T821
Test name
Test status
Simulation time 41933046 ps
CPU time 0.83 seconds
Started Aug 06 07:29:32 PM PDT 24
Finished Aug 06 07:29:33 PM PDT 24
Peak memory 200984 kb
Host smart-63e7395b-987f-40fd-ab6a-348b34a00ca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389589019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.389589019
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.1487809492
Short name T47
Test name
Test status
Simulation time 797930858 ps
CPU time 4.63 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:35 PM PDT 24
Peak memory 201324 kb
Host smart-af0fa793-a08d-42d7-8321-6907ba0e58a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487809492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1487809492
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.2885141753
Short name T819
Test name
Test status
Simulation time 23003272 ps
CPU time 0.89 seconds
Started Aug 06 07:29:34 PM PDT 24
Finished Aug 06 07:29:35 PM PDT 24
Peak memory 201084 kb
Host smart-ad07cf92-0f29-4654-845f-ecdd5ce76b9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885141753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.2885141753
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.1831596935
Short name T520
Test name
Test status
Simulation time 8052339767 ps
CPU time 35.21 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:30:06 PM PDT 24
Peak memory 201412 kb
Host smart-322dd4e8-f273-44bf-b687-d30f4b19fc3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831596935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.1831596935
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.1536910540
Short name T492
Test name
Test status
Simulation time 27061692 ps
CPU time 0.92 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:32 PM PDT 24
Peak memory 201020 kb
Host smart-deace3e4-a761-410d-96aa-0e778261bad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536910540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.1536910540
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.308675343
Short name T754
Test name
Test status
Simulation time 28986702 ps
CPU time 0.82 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201108 kb
Host smart-ce4fc317-6167-4067-8d86-dad742e6748b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308675343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkm
gr_alert_test.308675343
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.981077110
Short name T729
Test name
Test status
Simulation time 79193245 ps
CPU time 1.06 seconds
Started Aug 06 07:29:42 PM PDT 24
Finished Aug 06 07:29:43 PM PDT 24
Peak memory 201136 kb
Host smart-b92ae239-4c82-4807-aed3-9698fe4c58c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981077110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.981077110
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.1218678905
Short name T181
Test name
Test status
Simulation time 19480567 ps
CPU time 0.72 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201008 kb
Host smart-61174baa-54c2-4280-8dc7-c228d237d403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218678905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.1218678905
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.145571774
Short name T658
Test name
Test status
Simulation time 86597471 ps
CPU time 1.11 seconds
Started Aug 06 07:29:55 PM PDT 24
Finished Aug 06 07:29:56 PM PDT 24
Peak memory 201092 kb
Host smart-779ec775-77b4-4f75-8fc8-17c238cb3a92
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145571774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_div_intersig_mubi.145571774
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.1231202621
Short name T201
Test name
Test status
Simulation time 31399724 ps
CPU time 0.84 seconds
Started Aug 06 07:29:30 PM PDT 24
Finished Aug 06 07:29:30 PM PDT 24
Peak memory 201080 kb
Host smart-d0c1e666-e853-4fc5-a060-78c734d0c729
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231202621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1231202621
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.2658954250
Short name T420
Test name
Test status
Simulation time 1177603087 ps
CPU time 5.85 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:37 PM PDT 24
Peak memory 201220 kb
Host smart-80a13db9-ab8c-495f-be91-05c3a8e03cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658954250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2658954250
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.2189397605
Short name T788
Test name
Test status
Simulation time 1153768349 ps
CPU time 5.38 seconds
Started Aug 06 07:29:31 PM PDT 24
Finished Aug 06 07:29:36 PM PDT 24
Peak memory 201164 kb
Host smart-e1124e42-3883-45c2-8a7f-b323ceefc315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189397605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.2189397605
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.841794772
Short name T372
Test name
Test status
Simulation time 50449567 ps
CPU time 1.02 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201092 kb
Host smart-24aedce3-8748-45d7-8577-c4148666a8ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841794772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_idle_intersig_mubi.841794772
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1860108689
Short name T91
Test name
Test status
Simulation time 126124673 ps
CPU time 1.19 seconds
Started Aug 06 07:29:50 PM PDT 24
Finished Aug 06 07:29:51 PM PDT 24
Peak memory 201064 kb
Host smart-afb99a2b-51ed-481c-a28d-ccf9ccca9831
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860108689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1860108689
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.470414596
Short name T805
Test name
Test status
Simulation time 22671744 ps
CPU time 0.83 seconds
Started Aug 06 07:29:44 PM PDT 24
Finished Aug 06 07:29:45 PM PDT 24
Peak memory 201072 kb
Host smart-39d6f188-b73b-4e8d-a342-b50929621614
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470414596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.clkmgr_lc_ctrl_intersig_mubi.470414596
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.2367026865
Short name T537
Test name
Test status
Simulation time 39591181 ps
CPU time 0.81 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201044 kb
Host smart-755ed7e0-0c6b-4d32-a5a2-7605fd916c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367026865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.2367026865
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.3462590788
Short name T157
Test name
Test status
Simulation time 149970242 ps
CPU time 1.41 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:53 PM PDT 24
Peak memory 201004 kb
Host smart-55631cb5-8744-417b-8aab-47b9f038b77f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462590788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.3462590788
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.1236067785
Short name T458
Test name
Test status
Simulation time 21355473 ps
CPU time 0.88 seconds
Started Aug 06 07:29:29 PM PDT 24
Finished Aug 06 07:29:30 PM PDT 24
Peak memory 201084 kb
Host smart-82fc1160-fb4b-4950-a57d-6abdb91087ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236067785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1236067785
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.4093918383
Short name T769
Test name
Test status
Simulation time 4928377348 ps
CPU time 34.86 seconds
Started Aug 06 07:29:49 PM PDT 24
Finished Aug 06 07:30:24 PM PDT 24
Peak memory 201424 kb
Host smart-8e07513d-7981-4880-b4e0-ee3a3d6ec25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093918383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.4093918383
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.465620438
Short name T577
Test name
Test status
Simulation time 17172157684 ps
CPU time 262.15 seconds
Started Aug 06 07:29:47 PM PDT 24
Finished Aug 06 07:34:09 PM PDT 24
Peak memory 209792 kb
Host smart-05afda65-d402-489a-8e43-0a8be0f190a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=465620438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.465620438
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.3560273689
Short name T749
Test name
Test status
Simulation time 49147053 ps
CPU time 0.84 seconds
Started Aug 06 07:29:46 PM PDT 24
Finished Aug 06 07:29:47 PM PDT 24
Peak memory 200996 kb
Host smart-41d0fff1-7ded-4fa8-b57a-a59eab0113fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560273689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.3560273689
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.2935376017
Short name T550
Test name
Test status
Simulation time 36574263 ps
CPU time 0.81 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:15 PM PDT 24
Peak memory 201016 kb
Host smart-d8e21dd5-66f6-408b-b6e0-6c8e1f0d4f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935376017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.2935376017
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1290389495
Short name T229
Test name
Test status
Simulation time 58253763 ps
CPU time 0.93 seconds
Started Aug 06 07:27:17 PM PDT 24
Finished Aug 06 07:27:18 PM PDT 24
Peak memory 201112 kb
Host smart-cbe54085-ac9b-4e22-9fa3-2807a22af0e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290389495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1290389495
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2405817358
Short name T296
Test name
Test status
Simulation time 27446815 ps
CPU time 0.74 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:15 PM PDT 24
Peak memory 200296 kb
Host smart-384b2e08-45fa-41fa-8964-f922d6b5c5d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405817358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2405817358
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.3530131264
Short name T264
Test name
Test status
Simulation time 99798314 ps
CPU time 1.18 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:15 PM PDT 24
Peak memory 200652 kb
Host smart-80209b84-2d0a-45b3-9328-a2e5175215cc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530131264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.3530131264
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.3764963413
Short name T652
Test name
Test status
Simulation time 86388224 ps
CPU time 1.05 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:14 PM PDT 24
Peak memory 201048 kb
Host smart-d0708fc5-f530-4e41-91e1-5318c74f480c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764963413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.3764963413
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.3994799776
Short name T682
Test name
Test status
Simulation time 2260548846 ps
CPU time 11.87 seconds
Started Aug 06 07:27:16 PM PDT 24
Finished Aug 06 07:27:28 PM PDT 24
Peak memory 201344 kb
Host smart-4fa7a8ba-b8be-48ba-925c-263275c2dcea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994799776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.3994799776
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.2245813334
Short name T218
Test name
Test status
Simulation time 1361465905 ps
CPU time 5.82 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:19 PM PDT 24
Peak memory 201260 kb
Host smart-51c39b64-3095-46ce-8cfc-3bfea799cd9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245813334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.2245813334
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.1562337314
Short name T680
Test name
Test status
Simulation time 31033840 ps
CPU time 1.02 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:15 PM PDT 24
Peak memory 201088 kb
Host smart-425afe70-6e07-426a-948c-a5c4754445d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562337314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.1562337314
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.3265842530
Short name T701
Test name
Test status
Simulation time 39640046 ps
CPU time 0.92 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:14 PM PDT 24
Peak memory 201148 kb
Host smart-6c8fdace-b431-4d0a-89af-695c3b70fa17
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265842530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.3265842530
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1214447060
Short name T703
Test name
Test status
Simulation time 44619393 ps
CPU time 0.84 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:14 PM PDT 24
Peak memory 201040 kb
Host smart-a044fbc1-0b7d-45aa-bfbd-adcd7284d6af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214447060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.1214447060
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.2824479980
Short name T514
Test name
Test status
Simulation time 17710896 ps
CPU time 0.81 seconds
Started Aug 06 07:27:12 PM PDT 24
Finished Aug 06 07:27:12 PM PDT 24
Peak memory 201060 kb
Host smart-6d2a2629-c738-4d79-b6dd-02b3fb324925
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824479980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.2824479980
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.3120698825
Short name T158
Test name
Test status
Simulation time 538955170 ps
CPU time 3.5 seconds
Started Aug 06 07:27:12 PM PDT 24
Finished Aug 06 07:27:16 PM PDT 24
Peak memory 201288 kb
Host smart-4f229fcb-b95a-4ccc-86a8-76791055f9df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120698825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3120698825
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.3252100412
Short name T39
Test name
Test status
Simulation time 407235139 ps
CPU time 3.21 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:17 PM PDT 24
Peak memory 217980 kb
Host smart-7d1dd549-0d60-4048-965b-bf6a878beb3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252100412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.3252100412
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.3897343165
Short name T386
Test name
Test status
Simulation time 39058361 ps
CPU time 0.89 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:14 PM PDT 24
Peak memory 201012 kb
Host smart-cfdabc20-71a9-4bc0-aa4f-9ed61d57c578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897343165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.3897343165
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.2555058596
Short name T429
Test name
Test status
Simulation time 7771274268 ps
CPU time 26.44 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:40 PM PDT 24
Peak memory 201416 kb
Host smart-bc38e8cc-464f-42e3-b948-0c70cfe53425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555058596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.2555058596
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.1032175217
Short name T73
Test name
Test status
Simulation time 83221498349 ps
CPU time 750.54 seconds
Started Aug 06 07:27:12 PM PDT 24
Finished Aug 06 07:39:42 PM PDT 24
Peak memory 209736 kb
Host smart-ab43d858-1a9e-4ec5-9fd3-6092562221a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1032175217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.1032175217
Directory /workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.clkmgr_trans.414770823
Short name T736
Test name
Test status
Simulation time 88479398 ps
CPU time 1.09 seconds
Started Aug 06 07:27:12 PM PDT 24
Finished Aug 06 07:27:13 PM PDT 24
Peak memory 201040 kb
Host smart-957c1265-0278-46a5-8ae2-9723251be4d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414770823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.414770823
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1022935087
Short name T213
Test name
Test status
Simulation time 34503264 ps
CPU time 0.75 seconds
Started Aug 06 07:29:42 PM PDT 24
Finished Aug 06 07:29:43 PM PDT 24
Peak memory 200320 kb
Host smart-ce8ba487-80c1-492b-98e4-b7c3dde86ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022935087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1022935087
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.3970083952
Short name T265
Test name
Test status
Simulation time 31177430 ps
CPU time 0.88 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201064 kb
Host smart-21d8a32c-ff44-40bd-aaaa-e54c3fd0f3f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970083952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.3970083952
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.2832579803
Short name T517
Test name
Test status
Simulation time 38160570 ps
CPU time 0.77 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201012 kb
Host smart-69091469-58cc-4008-ae80-350cea6df238
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832579803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2832579803
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.3577093945
Short name T600
Test name
Test status
Simulation time 45192052 ps
CPU time 0.83 seconds
Started Aug 06 07:29:50 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201080 kb
Host smart-ef5a21cd-83cb-4a81-8e97-d2d2e65ec6c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577093945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.3577093945
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.3086398752
Short name T540
Test name
Test status
Simulation time 16746306 ps
CPU time 0.79 seconds
Started Aug 06 07:29:45 PM PDT 24
Finished Aug 06 07:29:46 PM PDT 24
Peak memory 201124 kb
Host smart-5726995a-145a-497c-8ea4-088d793c275d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086398752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.3086398752
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.2146409115
Short name T494
Test name
Test status
Simulation time 1398163066 ps
CPU time 10.38 seconds
Started Aug 06 07:29:43 PM PDT 24
Finished Aug 06 07:29:54 PM PDT 24
Peak memory 201064 kb
Host smart-97a94745-a8b9-484d-ac22-f768fda67002
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146409115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2146409115
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.4240613901
Short name T311
Test name
Test status
Simulation time 2573458744 ps
CPU time 8.96 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:30:00 PM PDT 24
Peak memory 201436 kb
Host smart-7763cd5e-e8b7-409b-a530-f7d335e45785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240613901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.4240613901
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2844558922
Short name T718
Test name
Test status
Simulation time 78311359 ps
CPU time 0.99 seconds
Started Aug 06 07:29:45 PM PDT 24
Finished Aug 06 07:29:46 PM PDT 24
Peak memory 201112 kb
Host smart-bd531d1a-fb1a-4f41-906b-7d63e1a08028
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844558922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.2844558922
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1732004746
Short name T609
Test name
Test status
Simulation time 26304875 ps
CPU time 0.87 seconds
Started Aug 06 07:29:50 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201076 kb
Host smart-f875ee91-23f1-41d8-b6c8-ebf3898bc8f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732004746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.1732004746
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1280355281
Short name T700
Test name
Test status
Simulation time 19086008 ps
CPU time 0.82 seconds
Started Aug 06 07:29:48 PM PDT 24
Finished Aug 06 07:29:49 PM PDT 24
Peak memory 201084 kb
Host smart-0c7a1cca-4cd3-4d5a-9bc3-2de6f2ac3440
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280355281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.1280355281
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.2167964854
Short name T359
Test name
Test status
Simulation time 15244002 ps
CPU time 0.76 seconds
Started Aug 06 07:29:49 PM PDT 24
Finished Aug 06 07:29:50 PM PDT 24
Peak memory 201128 kb
Host smart-c282d431-d307-40dc-8141-a2e97b93072b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167964854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2167964854
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.2914203845
Short name T661
Test name
Test status
Simulation time 770667421 ps
CPU time 3.76 seconds
Started Aug 06 07:29:49 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201292 kb
Host smart-a13181c5-fe31-4dec-9e0d-eb55c43a8310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914203845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.2914203845
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.3301294635
Short name T775
Test name
Test status
Simulation time 43017273 ps
CPU time 0.95 seconds
Started Aug 06 07:29:48 PM PDT 24
Finished Aug 06 07:29:50 PM PDT 24
Peak memory 201132 kb
Host smart-cccfd439-036b-4a05-8d8f-df09e1d50f66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301294635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3301294635
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.1890428459
Short name T307
Test name
Test status
Simulation time 3650064867 ps
CPU time 27.92 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:30:19 PM PDT 24
Peak memory 201452 kb
Host smart-fd0b1b97-1274-4ac6-beb7-ecfbc1b8eedb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890428459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.1890428459
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.618657717
Short name T644
Test name
Test status
Simulation time 22097470 ps
CPU time 0.87 seconds
Started Aug 06 07:29:52 PM PDT 24
Finished Aug 06 07:29:53 PM PDT 24
Peak memory 201128 kb
Host smart-66b2d21a-b8e4-4bcd-a9a4-bcafeed5c30c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618657717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.618657717
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.2475088655
Short name T284
Test name
Test status
Simulation time 77339783 ps
CPU time 0.95 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201104 kb
Host smart-3c1ab319-e1cd-4244-9e7d-020c1dfa9c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475088655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.2475088655
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.1411633348
Short name T317
Test name
Test status
Simulation time 30670054 ps
CPU time 0.75 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 200284 kb
Host smart-ab56c86a-cad4-4fdc-b401-0e3931ded646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411633348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.1411633348
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.1677069790
Short name T725
Test name
Test status
Simulation time 29112772 ps
CPU time 0.91 seconds
Started Aug 06 07:29:50 PM PDT 24
Finished Aug 06 07:29:51 PM PDT 24
Peak memory 201076 kb
Host smart-57c33801-7f64-4821-a8be-6ab866233ec4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677069790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.1677069790
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.3573223282
Short name T743
Test name
Test status
Simulation time 60847873 ps
CPU time 0.97 seconds
Started Aug 06 07:29:55 PM PDT 24
Finished Aug 06 07:29:56 PM PDT 24
Peak memory 201040 kb
Host smart-3af3b0fc-bd46-46cf-93e3-6347570b6c8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573223282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3573223282
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.3938517496
Short name T469
Test name
Test status
Simulation time 1932900412 ps
CPU time 7.77 seconds
Started Aug 06 07:29:42 PM PDT 24
Finished Aug 06 07:29:50 PM PDT 24
Peak memory 201308 kb
Host smart-17a8bc55-2ddd-40ff-be10-fe723f9afa2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938517496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.3938517496
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.2224761603
Short name T397
Test name
Test status
Simulation time 253897581 ps
CPU time 2.51 seconds
Started Aug 06 07:29:45 PM PDT 24
Finished Aug 06 07:29:48 PM PDT 24
Peak memory 201144 kb
Host smart-9df7564e-c4fe-446c-aca1-01c5789556f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224761603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.2224761603
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.633228347
Short name T580
Test name
Test status
Simulation time 94572704 ps
CPU time 1.16 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:53 PM PDT 24
Peak memory 201032 kb
Host smart-e0c4b198-744c-4db3-80dc-0f99040443a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633228347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_idle_intersig_mubi.633228347
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1917205454
Short name T379
Test name
Test status
Simulation time 30768407 ps
CPU time 0.82 seconds
Started Aug 06 07:29:46 PM PDT 24
Finished Aug 06 07:29:47 PM PDT 24
Peak memory 201056 kb
Host smart-6a46d35c-d870-4d16-a61f-affcb8a1eb1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917205454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.1917205454
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2123146862
Short name T667
Test name
Test status
Simulation time 89209686 ps
CPU time 1.07 seconds
Started Aug 06 07:29:49 PM PDT 24
Finished Aug 06 07:29:50 PM PDT 24
Peak memory 201120 kb
Host smart-c3169221-6556-4576-be48-187ca4258f29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123146862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.2123146862
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.801414508
Short name T804
Test name
Test status
Simulation time 13482278 ps
CPU time 0.73 seconds
Started Aug 06 07:29:44 PM PDT 24
Finished Aug 06 07:29:45 PM PDT 24
Peak memory 201060 kb
Host smart-1a59886c-495f-4f01-8881-741589f51043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801414508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.801414508
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.4245118793
Short name T553
Test name
Test status
Simulation time 1347123266 ps
CPU time 7.72 seconds
Started Aug 06 07:29:55 PM PDT 24
Finished Aug 06 07:30:03 PM PDT 24
Peak memory 201288 kb
Host smart-7e41407a-5c21-4907-b30e-6a2f16e570cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245118793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.4245118793
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.4037408551
Short name T18
Test name
Test status
Simulation time 24655499 ps
CPU time 0.9 seconds
Started Aug 06 07:29:48 PM PDT 24
Finished Aug 06 07:29:49 PM PDT 24
Peak memory 201132 kb
Host smart-21c9a25f-9761-4d20-9d5b-d746a9709c2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037408551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.4037408551
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.1375109506
Short name T427
Test name
Test status
Simulation time 2747791745 ps
CPU time 20.28 seconds
Started Aug 06 07:29:52 PM PDT 24
Finished Aug 06 07:30:12 PM PDT 24
Peak memory 201472 kb
Host smart-68569f9b-895e-4e91-a7bb-7c58ae9e6c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375109506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.1375109506
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_trans.1305169332
Short name T712
Test name
Test status
Simulation time 109556692 ps
CPU time 1.19 seconds
Started Aug 06 07:29:49 PM PDT 24
Finished Aug 06 07:29:50 PM PDT 24
Peak memory 201100 kb
Host smart-49bae00c-0f25-440b-ae96-3661ef501615
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305169332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1305169332
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3187427636
Short name T48
Test name
Test status
Simulation time 88677951 ps
CPU time 1.15 seconds
Started Aug 06 07:29:53 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201096 kb
Host smart-8438ccbd-c1bc-41a9-a682-b84d065d645a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187427636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.3187427636
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.860650696
Short name T322
Test name
Test status
Simulation time 34648012 ps
CPU time 0.78 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 200256 kb
Host smart-0f192369-aa11-4ed6-b3d6-2044419a8847
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860650696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.860650696
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.2411902903
Short name T581
Test name
Test status
Simulation time 99949379 ps
CPU time 1.08 seconds
Started Aug 06 07:29:48 PM PDT 24
Finished Aug 06 07:29:49 PM PDT 24
Peak memory 201124 kb
Host smart-2d9422b3-7dd4-4710-a814-dea7207adbd5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411902903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.2411902903
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.1707568879
Short name T734
Test name
Test status
Simulation time 158850822 ps
CPU time 1.34 seconds
Started Aug 06 07:29:55 PM PDT 24
Finished Aug 06 07:29:57 PM PDT 24
Peak memory 201056 kb
Host smart-22b09ec9-17ee-487e-85ec-cfee663f94cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707568879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1707568879
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.683941844
Short name T809
Test name
Test status
Simulation time 2476578302 ps
CPU time 19.4 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:30:11 PM PDT 24
Peak memory 201340 kb
Host smart-40b5764f-6049-4625-a85c-79f65c7eaaa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683941844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.683941844
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.744359198
Short name T74
Test name
Test status
Simulation time 153993494 ps
CPU time 1.17 seconds
Started Aug 06 07:29:50 PM PDT 24
Finished Aug 06 07:29:51 PM PDT 24
Peak memory 201164 kb
Host smart-256a2d77-0412-4eab-8419-321e2133e1c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744359198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_ti
meout.744359198
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.2490129920
Short name T624
Test name
Test status
Simulation time 40232751 ps
CPU time 0.86 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201080 kb
Host smart-ed23d034-99ba-4ab8-a009-b8325883439e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490129920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.2490129920
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.3335130526
Short name T297
Test name
Test status
Simulation time 18940918 ps
CPU time 0.79 seconds
Started Aug 06 07:29:49 PM PDT 24
Finished Aug 06 07:29:50 PM PDT 24
Peak memory 201104 kb
Host smart-88d25987-38bf-45d1-8d71-c7d0469cddf6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335130526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.3335130526
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3457526383
Short name T54
Test name
Test status
Simulation time 38475055 ps
CPU time 0.89 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201080 kb
Host smart-4ad0ce7b-c8d6-4357-8331-af9c465cf557
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457526383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.3457526383
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.3390189753
Short name T257
Test name
Test status
Simulation time 25098538 ps
CPU time 0.77 seconds
Started Aug 06 07:29:52 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201036 kb
Host smart-28e81b0a-968e-4a1b-9f09-8a0bf6171a6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390189753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3390189753
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.2384985658
Short name T444
Test name
Test status
Simulation time 687318134 ps
CPU time 3 seconds
Started Aug 06 07:29:52 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201264 kb
Host smart-3be2632a-087e-4aeb-9ec1-8ef465a5551b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384985658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.2384985658
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.257051723
Short name T740
Test name
Test status
Simulation time 21088131 ps
CPU time 0.86 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:29:54 PM PDT 24
Peak memory 201104 kb
Host smart-75668490-3f71-4919-a3ea-283658b93b2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257051723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.257051723
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.3752973645
Short name T532
Test name
Test status
Simulation time 4591442345 ps
CPU time 33.54 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:30:28 PM PDT 24
Peak memory 201464 kb
Host smart-e21c5d7c-f8a3-4f56-a8ab-ac79935ab02c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752973645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.3752973645
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.1365257348
Short name T214
Test name
Test status
Simulation time 14795337 ps
CPU time 0.76 seconds
Started Aug 06 07:29:51 PM PDT 24
Finished Aug 06 07:29:52 PM PDT 24
Peak memory 201056 kb
Host smart-238908b0-3ff9-4df2-a75b-652326144bf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365257348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1365257348
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.3795304915
Short name T34
Test name
Test status
Simulation time 18150364 ps
CPU time 0.83 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:04 PM PDT 24
Peak memory 201100 kb
Host smart-b40fd233-a56a-4b86-b821-51938b71836d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795304915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.3795304915
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.2097065541
Short name T106
Test name
Test status
Simulation time 63340056 ps
CPU time 0.96 seconds
Started Aug 06 07:30:06 PM PDT 24
Finished Aug 06 07:30:07 PM PDT 24
Peak memory 201064 kb
Host smart-3efb87ae-1379-488e-a9ce-a8a968f18e92
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097065541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.2097065541
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.2694980338
Short name T497
Test name
Test status
Simulation time 18087550 ps
CPU time 0.81 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:05 PM PDT 24
Peak memory 200232 kb
Host smart-46c14f17-eeb1-436b-982c-cf02eef0168b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694980338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2694980338
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.3781525097
Short name T468
Test name
Test status
Simulation time 75584429 ps
CPU time 1.06 seconds
Started Aug 06 07:30:00 PM PDT 24
Finished Aug 06 07:30:01 PM PDT 24
Peak memory 201076 kb
Host smart-29a93845-c882-4652-826e-a1e2f08d9def
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781525097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.3781525097
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.1018959615
Short name T210
Test name
Test status
Simulation time 28209915 ps
CPU time 0.82 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:05 PM PDT 24
Peak memory 201088 kb
Host smart-095c581c-5e57-4514-8fc8-9224109eac17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018959615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1018959615
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.2498018441
Short name T593
Test name
Test status
Simulation time 2114948617 ps
CPU time 16.78 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:20 PM PDT 24
Peak memory 201212 kb
Host smart-eee543b8-3f91-40aa-861a-32a85bc84133
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498018441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2498018441
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.900401495
Short name T569
Test name
Test status
Simulation time 986461181 ps
CPU time 5.03 seconds
Started Aug 06 07:30:07 PM PDT 24
Finished Aug 06 07:30:12 PM PDT 24
Peak memory 201192 kb
Host smart-bda577f9-e2ad-452f-83f1-f9204f73c54e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900401495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti
meout.900401495
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.4063676321
Short name T518
Test name
Test status
Simulation time 67847568 ps
CPU time 1.02 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:04 PM PDT 24
Peak memory 201108 kb
Host smart-a4daa475-2d09-49ae-9b19-21b56b2cbcc1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063676321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.4063676321
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3603230067
Short name T676
Test name
Test status
Simulation time 17683234 ps
CPU time 0.82 seconds
Started Aug 06 07:30:02 PM PDT 24
Finished Aug 06 07:30:03 PM PDT 24
Peak memory 201040 kb
Host smart-b2b8edda-13e5-41c0-bf5c-1e7d569ab44a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603230067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3603230067
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3016690527
Short name T349
Test name
Test status
Simulation time 38722193 ps
CPU time 0.82 seconds
Started Aug 06 07:30:02 PM PDT 24
Finished Aug 06 07:30:03 PM PDT 24
Peak memory 201068 kb
Host smart-45e47e29-fec3-4e4b-9ca1-586619c19f15
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016690527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.3016690527
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.4061165713
Short name T597
Test name
Test status
Simulation time 30574032 ps
CPU time 0.81 seconds
Started Aug 06 07:30:02 PM PDT 24
Finished Aug 06 07:30:02 PM PDT 24
Peak memory 201112 kb
Host smart-c3fc21e1-b3a6-4963-8edf-4a45cc8ef792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061165713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.4061165713
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.4231061357
Short name T163
Test name
Test status
Simulation time 322726829 ps
CPU time 1.62 seconds
Started Aug 06 07:30:05 PM PDT 24
Finished Aug 06 07:30:07 PM PDT 24
Peak memory 201056 kb
Host smart-89f47897-1378-4876-a07c-b8c1fb443e59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231061357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.4231061357
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.4128376449
Short name T151
Test name
Test status
Simulation time 94912753 ps
CPU time 1.13 seconds
Started Aug 06 07:29:54 PM PDT 24
Finished Aug 06 07:29:55 PM PDT 24
Peak memory 201040 kb
Host smart-77687c5a-4988-4fa3-8544-7aaa2ad4533d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128376449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4128376449
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.1422078885
Short name T641
Test name
Test status
Simulation time 5657353957 ps
CPU time 41.71 seconds
Started Aug 06 07:30:02 PM PDT 24
Finished Aug 06 07:30:44 PM PDT 24
Peak memory 201408 kb
Host smart-f4e131b2-9b7c-4164-9623-cb88ffe71eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422078885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.1422078885
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.363766548
Short name T705
Test name
Test status
Simulation time 82163132 ps
CPU time 1.08 seconds
Started Aug 06 07:30:01 PM PDT 24
Finished Aug 06 07:30:03 PM PDT 24
Peak memory 201076 kb
Host smart-acb5c79e-ac6e-4b45-a32a-3113a8e422a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363766548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.363766548
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.1589730748
Short name T390
Test name
Test status
Simulation time 58357029 ps
CPU time 0.86 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:05 PM PDT 24
Peak memory 201128 kb
Host smart-b87dd2d2-defc-4481-9881-a474dfc65d0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589730748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.1589730748
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.1983560426
Short name T245
Test name
Test status
Simulation time 17698147 ps
CPU time 0.77 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:05 PM PDT 24
Peak memory 201124 kb
Host smart-9d7a4e0b-041d-4a93-bd1a-34578dfb734f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983560426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.1983560426
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.2330533792
Short name T684
Test name
Test status
Simulation time 15091724 ps
CPU time 0.76 seconds
Started Aug 06 07:30:05 PM PDT 24
Finished Aug 06 07:30:06 PM PDT 24
Peak memory 200252 kb
Host smart-d518eee4-75fa-416f-97c5-765ccfc618e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330533792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2330533792
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.4274084064
Short name T481
Test name
Test status
Simulation time 51001986 ps
CPU time 0.93 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:05 PM PDT 24
Peak memory 201100 kb
Host smart-95a02a07-7dea-4c38-9594-0c9f02b88744
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274084064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.4274084064
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.2101392919
Short name T253
Test name
Test status
Simulation time 116428574 ps
CPU time 1.02 seconds
Started Aug 06 07:30:06 PM PDT 24
Finished Aug 06 07:30:07 PM PDT 24
Peak memory 201068 kb
Host smart-7d78b0ef-9a5f-4004-869c-c78855fa0d22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101392919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.2101392919
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.159834585
Short name T560
Test name
Test status
Simulation time 1155592527 ps
CPU time 9.2 seconds
Started Aug 06 07:30:06 PM PDT 24
Finished Aug 06 07:30:15 PM PDT 24
Peak memory 201092 kb
Host smart-66e2eeff-c2b2-4078-afd6-a82a42e65bd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159834585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.159834585
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.795213739
Short name T501
Test name
Test status
Simulation time 168968461 ps
CPU time 1.23 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:04 PM PDT 24
Peak memory 201208 kb
Host smart-78c986cb-339f-4141-8127-0c76ce3edf0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795213739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_ti
meout.795213739
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.1184109871
Short name T240
Test name
Test status
Simulation time 74986059 ps
CPU time 1.03 seconds
Started Aug 06 07:30:05 PM PDT 24
Finished Aug 06 07:30:06 PM PDT 24
Peak memory 201072 kb
Host smart-85857c4a-b836-4b48-885d-f739e3b85e9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184109871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.1184109871
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.1266528357
Short name T278
Test name
Test status
Simulation time 89553293 ps
CPU time 1.09 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:05 PM PDT 24
Peak memory 201100 kb
Host smart-764ce6d6-38ad-4403-b9cc-df25ad4399c1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266528357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.1266528357
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1056906784
Short name T613
Test name
Test status
Simulation time 60461261 ps
CPU time 0.93 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:05 PM PDT 24
Peak memory 201092 kb
Host smart-0c12d539-6ca1-4a14-a027-e5f4d6ca77c1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056906784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.1056906784
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.2224686364
Short name T320
Test name
Test status
Simulation time 22328235 ps
CPU time 0.7 seconds
Started Aug 06 07:30:02 PM PDT 24
Finished Aug 06 07:30:03 PM PDT 24
Peak memory 201016 kb
Host smart-bf883de7-ef1f-4fcf-9d12-5f230e9a78fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224686364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2224686364
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.2121471799
Short name T162
Test name
Test status
Simulation time 1198522184 ps
CPU time 4.58 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:08 PM PDT 24
Peak memory 201280 kb
Host smart-ada63988-f2cc-4674-8d43-518c99ed8b1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121471799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2121471799
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.802199638
Short name T814
Test name
Test status
Simulation time 58039655 ps
CPU time 0.98 seconds
Started Aug 06 07:30:06 PM PDT 24
Finished Aug 06 07:30:07 PM PDT 24
Peak memory 201104 kb
Host smart-bbd076e5-f66d-4e4c-bd2f-36a104052c56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802199638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.802199638
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.487366608
Short name T594
Test name
Test status
Simulation time 5171064577 ps
CPU time 26.63 seconds
Started Aug 06 07:30:05 PM PDT 24
Finished Aug 06 07:30:32 PM PDT 24
Peak memory 201520 kb
Host smart-fcbc8320-fe7c-48dd-ac67-b085665a7874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487366608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.487366608
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.1822097362
Short name T663
Test name
Test status
Simulation time 25569464 ps
CPU time 0.99 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:04 PM PDT 24
Peak memory 200992 kb
Host smart-16b06565-3ef8-4c5b-838b-8fc934efc1ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822097362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1822097362
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.3011687210
Short name T237
Test name
Test status
Simulation time 16905729 ps
CPU time 0.81 seconds
Started Aug 06 07:30:08 PM PDT 24
Finished Aug 06 07:30:09 PM PDT 24
Peak memory 201148 kb
Host smart-1b761f50-ec29-412e-9522-f24ac7a557e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011687210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.3011687210
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3630261007
Short name T184
Test name
Test status
Simulation time 23120687 ps
CPU time 0.9 seconds
Started Aug 06 07:30:06 PM PDT 24
Finished Aug 06 07:30:07 PM PDT 24
Peak memory 201060 kb
Host smart-9ea09b7e-cd9b-4d9d-9d41-4f5b06db6dc7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630261007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.3630261007
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.2341445447
Short name T289
Test name
Test status
Simulation time 41522286 ps
CPU time 0.75 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:03 PM PDT 24
Peak memory 200284 kb
Host smart-0e931f91-c654-43f7-962c-027553d1c1f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341445447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.2341445447
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.1942928730
Short name T223
Test name
Test status
Simulation time 22052391 ps
CPU time 0.86 seconds
Started Aug 06 07:30:06 PM PDT 24
Finished Aug 06 07:30:07 PM PDT 24
Peak memory 201044 kb
Host smart-9b71ffea-92b5-4b95-8a6c-4f116261048c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942928730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.1942928730
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.390292013
Short name T242
Test name
Test status
Simulation time 258081589 ps
CPU time 1.58 seconds
Started Aug 06 07:30:05 PM PDT 24
Finished Aug 06 07:30:06 PM PDT 24
Peak memory 201140 kb
Host smart-edf98f65-b60a-4ba6-9439-943106174064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390292013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.390292013
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.2032426753
Short name T739
Test name
Test status
Simulation time 686365301 ps
CPU time 4.13 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:07 PM PDT 24
Peak memory 201104 kb
Host smart-2f6c2104-6124-4731-aad5-809c3142a44f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032426753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2032426753
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.494282587
Short name T732
Test name
Test status
Simulation time 1579602676 ps
CPU time 11.44 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:14 PM PDT 24
Peak memory 201184 kb
Host smart-170dc0c9-8d4d-4798-837d-0bac5639cc74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494282587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_ti
meout.494282587
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3677214587
Short name T230
Test name
Test status
Simulation time 38672801 ps
CPU time 1.03 seconds
Started Aug 06 07:30:07 PM PDT 24
Finished Aug 06 07:30:09 PM PDT 24
Peak memory 201000 kb
Host smart-cc023a72-0251-433b-a34e-1dd968021a11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677214587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3677214587
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2494688758
Short name T222
Test name
Test status
Simulation time 34851461 ps
CPU time 0.92 seconds
Started Aug 06 07:30:05 PM PDT 24
Finished Aug 06 07:30:06 PM PDT 24
Peak memory 201104 kb
Host smart-2e9bd690-c087-4710-a4aa-f825c3dc8b68
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494688758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2494688758
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1257409620
Short name T475
Test name
Test status
Simulation time 66480693 ps
CPU time 1.03 seconds
Started Aug 06 07:30:07 PM PDT 24
Finished Aug 06 07:30:09 PM PDT 24
Peak memory 201008 kb
Host smart-07e2e6fd-79d7-4fde-9c3c-ee2375cb3046
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257409620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.1257409620
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.2415817838
Short name T802
Test name
Test status
Simulation time 20037203 ps
CPU time 0.76 seconds
Started Aug 06 07:30:05 PM PDT 24
Finished Aug 06 07:30:06 PM PDT 24
Peak memory 201096 kb
Host smart-8321b471-c95c-4d72-a3aa-7cd491fab63a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415817838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.2415817838
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.1708154025
Short name T457
Test name
Test status
Simulation time 1312261462 ps
CPU time 4.98 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:09 PM PDT 24
Peak memory 201284 kb
Host smart-bc11cc58-465d-4193-a9c8-1849ff218155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708154025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.1708154025
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.1008473672
Short name T360
Test name
Test status
Simulation time 21524315 ps
CPU time 0.89 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:04 PM PDT 24
Peak memory 200956 kb
Host smart-6b2fb6e1-8ad3-43b3-8e03-51887f4c623f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008473672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1008473672
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.3042850719
Short name T755
Test name
Test status
Simulation time 2819664113 ps
CPU time 21.4 seconds
Started Aug 06 07:30:06 PM PDT 24
Finished Aug 06 07:30:28 PM PDT 24
Peak memory 201500 kb
Host smart-d37ec836-fc56-4b59-80fb-e3a46b062c00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042850719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.3042850719
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.944197092
Short name T436
Test name
Test status
Simulation time 22798424 ps
CPU time 0.86 seconds
Started Aug 06 07:30:04 PM PDT 24
Finished Aug 06 07:30:05 PM PDT 24
Peak memory 201116 kb
Host smart-36d78001-78e3-4cb6-a060-904e76ba8380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944197092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.944197092
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.3990623672
Short name T741
Test name
Test status
Simulation time 17818473 ps
CPU time 0.84 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:30:23 PM PDT 24
Peak memory 201108 kb
Host smart-d4528b7e-283f-403c-a913-4b521f75145a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990623672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.3990623672
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.4203174055
Short name T394
Test name
Test status
Simulation time 46853384 ps
CPU time 0.82 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:22 PM PDT 24
Peak memory 201148 kb
Host smart-12286c17-7954-4965-925b-e8c1b0e0237b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203174055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.4203174055
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.2615918475
Short name T440
Test name
Test status
Simulation time 13803885 ps
CPU time 0.73 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:04 PM PDT 24
Peak memory 200320 kb
Host smart-e6ffa59b-f23e-4664-be7d-8ad4c50896e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615918475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2615918475
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.1375822718
Short name T829
Test name
Test status
Simulation time 23512709 ps
CPU time 0.86 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 201072 kb
Host smart-e93d1c76-c486-45b2-949b-b1cc8c26f40c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375822718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.1375822718
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.1914511811
Short name T490
Test name
Test status
Simulation time 22937611 ps
CPU time 0.9 seconds
Started Aug 06 07:30:08 PM PDT 24
Finished Aug 06 07:30:09 PM PDT 24
Peak memory 201092 kb
Host smart-cfddd5ca-e066-426f-b33a-ad17128363aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914511811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1914511811
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.1933233848
Short name T9
Test name
Test status
Simulation time 1283907379 ps
CPU time 7.99 seconds
Started Aug 06 07:30:08 PM PDT 24
Finished Aug 06 07:30:16 PM PDT 24
Peak memory 201212 kb
Host smart-38d6b5b9-bcc9-42d9-b433-2d78eeea847b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933233848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1933233848
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.3035679502
Short name T618
Test name
Test status
Simulation time 1819013202 ps
CPU time 9.8 seconds
Started Aug 06 07:30:00 PM PDT 24
Finished Aug 06 07:30:10 PM PDT 24
Peak memory 201244 kb
Host smart-9f2c3a79-7e83-4dc9-909e-d7ba3b452211
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035679502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.3035679502
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1871907084
Short name T433
Test name
Test status
Simulation time 116271334 ps
CPU time 1.29 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:04 PM PDT 24
Peak memory 201088 kb
Host smart-1327a785-121f-4470-ac3d-1f7d8069494c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871907084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.1871907084
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.1474211007
Short name T541
Test name
Test status
Simulation time 36610066 ps
CPU time 0.79 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:30:23 PM PDT 24
Peak memory 201056 kb
Host smart-4054849e-8eca-4f21-a399-e286fe3882c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474211007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.1474211007
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.1607892262
Short name T183
Test name
Test status
Simulation time 22401781 ps
CPU time 0.84 seconds
Started Aug 06 07:30:05 PM PDT 24
Finished Aug 06 07:30:06 PM PDT 24
Peak memory 201032 kb
Host smart-e83467f7-3f76-4f92-9de1-27385f321501
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607892262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.1607892262
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.1830201517
Short name T573
Test name
Test status
Simulation time 27936708 ps
CPU time 0.8 seconds
Started Aug 06 07:30:02 PM PDT 24
Finished Aug 06 07:30:03 PM PDT 24
Peak memory 201036 kb
Host smart-12ba147f-64e0-4ca1-a654-914a02bd692e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830201517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1830201517
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.126798758
Short name T639
Test name
Test status
Simulation time 1401288327 ps
CPU time 4.42 seconds
Started Aug 06 07:30:20 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 201300 kb
Host smart-5deef252-bd03-4e56-826c-1e4abd28c965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126798758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.126798758
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.3030966172
Short name T793
Test name
Test status
Simulation time 19329592 ps
CPU time 0.88 seconds
Started Aug 06 07:30:07 PM PDT 24
Finished Aug 06 07:30:08 PM PDT 24
Peak memory 201060 kb
Host smart-0d30d8fc-a1c1-4618-b4ea-d519a040249f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030966172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3030966172
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.2569450756
Short name T724
Test name
Test status
Simulation time 4916440476 ps
CPU time 37.71 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:31:00 PM PDT 24
Peak memory 201432 kb
Host smart-93ebd73a-8bff-423c-996d-13d8d619c662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569450756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.2569450756
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_trans.3593570866
Short name T447
Test name
Test status
Simulation time 36488936 ps
CPU time 0.89 seconds
Started Aug 06 07:30:03 PM PDT 24
Finished Aug 06 07:30:04 PM PDT 24
Peak memory 201120 kb
Host smart-f39ac379-3f25-4f45-8ca8-0cc531815ba4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593570866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.3593570866
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.3872670118
Short name T398
Test name
Test status
Simulation time 31024195 ps
CPU time 0.82 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:30:23 PM PDT 24
Peak memory 201088 kb
Host smart-2c0ebe40-841b-4c40-b00a-004fa3ce30f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872670118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.3872670118
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.964127416
Short name T353
Test name
Test status
Simulation time 17220038 ps
CPU time 0.81 seconds
Started Aug 06 07:30:24 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 201076 kb
Host smart-8814317f-a895-45ca-a8da-5d979475d172
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964127416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.964127416
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.3805691504
Short name T731
Test name
Test status
Simulation time 17143449 ps
CPU time 0.71 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:30:23 PM PDT 24
Peak memory 201004 kb
Host smart-5e04d2b0-e70c-4ceb-9190-11d2743bd54b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805691504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3805691504
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.1754183415
Short name T571
Test name
Test status
Simulation time 20636793 ps
CPU time 0.9 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:22 PM PDT 24
Peak memory 201132 kb
Host smart-f70e55a4-eba4-42c2-bf3c-1f1a59c69220
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754183415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.1754183415
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.3484643887
Short name T199
Test name
Test status
Simulation time 24641817 ps
CPU time 0.9 seconds
Started Aug 06 07:30:25 PM PDT 24
Finished Aug 06 07:30:26 PM PDT 24
Peak memory 201320 kb
Host smart-4dae007d-9103-4e7a-a0ac-91321fa49daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484643887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3484643887
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.1842841866
Short name T559
Test name
Test status
Simulation time 195684033 ps
CPU time 2.13 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 201136 kb
Host smart-05026dc6-27af-4d41-a543-87c2e4c1b4f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842841866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.1842841866
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.3955890096
Short name T677
Test name
Test status
Simulation time 870744161 ps
CPU time 4.76 seconds
Started Aug 06 07:30:24 PM PDT 24
Finished Aug 06 07:30:29 PM PDT 24
Peak memory 201208 kb
Host smart-16eac154-92df-4c89-959e-57027062cb2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955890096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.3955890096
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.2483082682
Short name T226
Test name
Test status
Simulation time 176627619 ps
CPU time 1.51 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:23 PM PDT 24
Peak memory 201048 kb
Host smart-635a668f-9fb6-4bfc-b49d-fdc44b36f8df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483082682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.2483082682
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3461236801
Short name T590
Test name
Test status
Simulation time 13451780 ps
CPU time 0.81 seconds
Started Aug 06 07:30:25 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 201076 kb
Host smart-657c3caa-28c9-4013-90bb-afcae8fb2d71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461236801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.3461236801
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.3278039335
Short name T215
Test name
Test status
Simulation time 21656217 ps
CPU time 0.87 seconds
Started Aug 06 07:30:20 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 201128 kb
Host smart-fde8e1d5-529d-4d90-9c0c-aad4ca5c2b0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278039335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.3278039335
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.4022211340
Short name T516
Test name
Test status
Simulation time 13693994 ps
CPU time 0.76 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 201080 kb
Host smart-c240b9c9-22c1-4603-8194-4abb5f0ea066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022211340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.4022211340
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.624575492
Short name T4
Test name
Test status
Simulation time 721305391 ps
CPU time 4.25 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:30:27 PM PDT 24
Peak memory 201332 kb
Host smart-42bd0b04-82fa-4f44-a783-90a40ee0ba05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624575492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.624575492
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.3734343648
Short name T720
Test name
Test status
Simulation time 41726936 ps
CPU time 0.88 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:30:24 PM PDT 24
Peak memory 201128 kb
Host smart-77bd3f72-08ce-442a-a727-2b3db36b4d8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734343648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3734343648
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.1111292634
Short name T598
Test name
Test status
Simulation time 81897902 ps
CPU time 1.06 seconds
Started Aug 06 07:30:19 PM PDT 24
Finished Aug 06 07:30:20 PM PDT 24
Peak memory 200984 kb
Host smart-6a650afd-caca-43aa-bc17-00e6490bcd60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111292634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.1111292634
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.1494753670
Short name T69
Test name
Test status
Simulation time 33819987600 ps
CPU time 280.83 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:35:04 PM PDT 24
Peak memory 217964 kb
Host smart-cf2a0e5b-21b4-4430-aa17-0f7a9d1eb654
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1494753670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.1494753670
Directory /workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.clkmgr_trans.548333840
Short name T241
Test name
Test status
Simulation time 17075065 ps
CPU time 0.76 seconds
Started Aug 06 07:30:20 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 201088 kb
Host smart-bc47e9f6-ab0b-4e53-a8a9-3c55590cf61f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548333840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.548333840
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.1055013870
Short name T627
Test name
Test status
Simulation time 136371069 ps
CPU time 1.06 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:30:23 PM PDT 24
Peak memory 201076 kb
Host smart-98f7ea1e-3f62-4f48-95e1-b5f88cebce50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055013870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.1055013870
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3351028747
Short name T803
Test name
Test status
Simulation time 39904459 ps
CPU time 0.84 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:30:23 PM PDT 24
Peak memory 201076 kb
Host smart-655befac-dabd-46b0-b166-5bd80a6981f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351028747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.3351028747
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.2959502235
Short name T362
Test name
Test status
Simulation time 35964579 ps
CPU time 0.75 seconds
Started Aug 06 07:30:24 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 200532 kb
Host smart-8d9b1f7e-ed89-4116-981c-e4046514e91e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959502235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2959502235
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.2941288339
Short name T381
Test name
Test status
Simulation time 22383043 ps
CPU time 0.76 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:30:24 PM PDT 24
Peak memory 201136 kb
Host smart-4f4558f9-a7ae-4630-b012-c47408b3660e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941288339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.2941288339
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.4038750243
Short name T258
Test name
Test status
Simulation time 26373692 ps
CPU time 0.89 seconds
Started Aug 06 07:30:25 PM PDT 24
Finished Aug 06 07:30:26 PM PDT 24
Peak memory 201064 kb
Host smart-d4002b67-bdf6-421f-ac94-4563ffbc1c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038750243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.4038750243
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.665109596
Short name T784
Test name
Test status
Simulation time 1157250624 ps
CPU time 9.08 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:30 PM PDT 24
Peak memory 201152 kb
Host smart-32bed124-d68e-4a07-b437-66502d58362d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665109596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.665109596
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.1571502877
Short name T275
Test name
Test status
Simulation time 2313922253 ps
CPU time 11.32 seconds
Started Aug 06 07:30:19 PM PDT 24
Finished Aug 06 07:30:31 PM PDT 24
Peak memory 201396 kb
Host smart-14e81761-457e-408f-9f81-1f63405dc8de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571502877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.1571502877
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.2517474445
Short name T7
Test name
Test status
Simulation time 21320631 ps
CPU time 0.87 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:30:24 PM PDT 24
Peak memory 201092 kb
Host smart-2001ce64-5961-4cae-9abd-41e0dc5de454
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517474445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.2517474445
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2858890387
Short name T21
Test name
Test status
Simulation time 20018035 ps
CPU time 0.78 seconds
Started Aug 06 07:30:19 PM PDT 24
Finished Aug 06 07:30:19 PM PDT 24
Peak memory 201080 kb
Host smart-f3dbd86f-9305-499a-8e68-d6a4eceb17dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858890387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2858890387
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.2735574067
Short name T820
Test name
Test status
Simulation time 44764365 ps
CPU time 0.96 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:30:24 PM PDT 24
Peak memory 201120 kb
Host smart-8f4930cb-4a7f-4c0c-b5c1-be09ffeabade
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735574067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.2735574067
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.1969264227
Short name T166
Test name
Test status
Simulation time 15740888 ps
CPU time 0.71 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:22 PM PDT 24
Peak memory 200976 kb
Host smart-c9346efd-234b-48bc-9a31-2e9977ee6078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969264227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1969264227
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.1568131851
Short name T330
Test name
Test status
Simulation time 707064724 ps
CPU time 3.2 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:24 PM PDT 24
Peak memory 201268 kb
Host smart-f0abd8cb-1109-4c30-bb87-301e30bb625b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568131851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1568131851
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.2519900997
Short name T339
Test name
Test status
Simulation time 73954944 ps
CPU time 1 seconds
Started Aug 06 07:30:20 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 201168 kb
Host smart-1b277b7e-36be-4d76-8e78-2d96335a4192
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519900997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2519900997
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.1708160091
Short name T596
Test name
Test status
Simulation time 6750284752 ps
CPU time 49.83 seconds
Started Aug 06 07:30:25 PM PDT 24
Finished Aug 06 07:31:15 PM PDT 24
Peak memory 201432 kb
Host smart-ee5c652a-9430-4243-9a27-fb4be69be42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708160091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.1708160091
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_trans.1195445039
Short name T280
Test name
Test status
Simulation time 14302667 ps
CPU time 0.74 seconds
Started Aug 06 07:30:24 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 201080 kb
Host smart-5abeb9c1-27aa-4a6b-a0bb-2116fdd512e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195445039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.1195445039
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.731667766
Short name T554
Test name
Test status
Simulation time 39690661 ps
CPU time 0.8 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:40 PM PDT 24
Peak memory 201060 kb
Host smart-47cc7091-8261-42eb-abbd-793154e8a164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731667766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkm
gr_alert_test.731667766
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.3459609613
Short name T211
Test name
Test status
Simulation time 20440903 ps
CPU time 0.84 seconds
Started Aug 06 07:30:20 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 201064 kb
Host smart-c88191a6-e1ee-4ed4-acef-9a5c31439710
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459609613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.3459609613
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.779507526
Short name T42
Test name
Test status
Simulation time 31386144 ps
CPU time 0.74 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:30:23 PM PDT 24
Peak memory 200280 kb
Host smart-1c5ec89e-09fe-4cf1-9f02-515bda28ee5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779507526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.779507526
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.3089281673
Short name T428
Test name
Test status
Simulation time 20853411 ps
CPU time 0.8 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:30:24 PM PDT 24
Peak memory 201092 kb
Host smart-d0432c52-8e69-4262-aff8-58f5461981cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089281673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.3089281673
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.2431231737
Short name T523
Test name
Test status
Simulation time 42875163 ps
CPU time 0.83 seconds
Started Aug 06 07:30:24 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 201332 kb
Host smart-64e1d341-9ba2-48ef-9762-88cf09cbc531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431231737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2431231737
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.4008572798
Short name T543
Test name
Test status
Simulation time 2282266262 ps
CPU time 9.29 seconds
Started Aug 06 07:30:20 PM PDT 24
Finished Aug 06 07:30:29 PM PDT 24
Peak memory 201416 kb
Host smart-32736681-b3e5-4fe9-8ce4-619b5c5ef753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008572798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.4008572798
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.2161890932
Short name T321
Test name
Test status
Simulation time 1956086028 ps
CPU time 8.73 seconds
Started Aug 06 07:30:22 PM PDT 24
Finished Aug 06 07:30:31 PM PDT 24
Peak memory 201160 kb
Host smart-f575265c-e439-4666-939d-073c2d992577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161890932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.2161890932
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.2508831467
Short name T395
Test name
Test status
Simulation time 25148974 ps
CPU time 0.94 seconds
Started Aug 06 07:30:24 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 201096 kb
Host smart-82cc629c-c4ce-4de4-8fb3-aa572704c368
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508831467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.2508831467
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1741405979
Short name T509
Test name
Test status
Simulation time 20506859 ps
CPU time 0.83 seconds
Started Aug 06 07:30:20 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 201044 kb
Host smart-af4f81e1-4e4e-4146-8755-ade59baf7d12
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741405979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.1741405979
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1658370041
Short name T672
Test name
Test status
Simulation time 77263169 ps
CPU time 1.09 seconds
Started Aug 06 07:30:20 PM PDT 24
Finished Aug 06 07:30:21 PM PDT 24
Peak memory 201040 kb
Host smart-c3a8599e-3f4a-459d-a7f8-8dcd420c5e19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658370041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.1658370041
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.1922726897
Short name T224
Test name
Test status
Simulation time 12702030 ps
CPU time 0.74 seconds
Started Aug 06 07:30:21 PM PDT 24
Finished Aug 06 07:30:22 PM PDT 24
Peak memory 201128 kb
Host smart-dc3563a3-3d1f-457b-8115-27761e9c0b48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922726897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1922726897
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1327450153
Short name T592
Test name
Test status
Simulation time 1036878165 ps
CPU time 4.82 seconds
Started Aug 06 07:30:38 PM PDT 24
Finished Aug 06 07:30:43 PM PDT 24
Peak memory 201352 kb
Host smart-783e9cc1-d6d9-48f3-a5d4-522b53f414b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327450153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1327450153
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.4085134431
Short name T662
Test name
Test status
Simulation time 31373171 ps
CPU time 0.88 seconds
Started Aug 06 07:30:24 PM PDT 24
Finished Aug 06 07:30:25 PM PDT 24
Peak memory 201104 kb
Host smart-b4ee7e4a-02a9-4530-9585-27b020161e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085134431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.4085134431
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.2694156586
Short name T12
Test name
Test status
Simulation time 5623209674 ps
CPU time 23.5 seconds
Started Aug 06 07:30:37 PM PDT 24
Finished Aug 06 07:31:00 PM PDT 24
Peak memory 201360 kb
Host smart-4e2bc66d-be37-4f0a-ad06-292f6d270f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694156586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.2694156586
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_trans.1023988814
Short name T328
Test name
Test status
Simulation time 23902409 ps
CPU time 0.88 seconds
Started Aug 06 07:30:23 PM PDT 24
Finished Aug 06 07:30:24 PM PDT 24
Peak memory 201104 kb
Host smart-22978e82-cfa3-4d8d-999c-b56ac54c3b4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023988814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1023988814
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.2670539856
Short name T733
Test name
Test status
Simulation time 36763504 ps
CPU time 0.85 seconds
Started Aug 06 07:27:32 PM PDT 24
Finished Aug 06 07:27:33 PM PDT 24
Peak memory 201080 kb
Host smart-10599594-8971-423c-983f-6c1b0196503c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670539856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.2670539856
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.2798794623
Short name T789
Test name
Test status
Simulation time 19239231 ps
CPU time 0.82 seconds
Started Aug 06 07:27:12 PM PDT 24
Finished Aug 06 07:27:13 PM PDT 24
Peak memory 201088 kb
Host smart-09ba55cf-c30c-4e90-a1f0-c3b67dbfc4f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798794623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.2798794623
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.1257831286
Short name T176
Test name
Test status
Simulation time 13508276 ps
CPU time 0.69 seconds
Started Aug 06 07:27:13 PM PDT 24
Finished Aug 06 07:27:14 PM PDT 24
Peak memory 200332 kb
Host smart-1b349d29-5915-482e-bde6-ed800e92d3ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257831286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1257831286
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.527385907
Short name T340
Test name
Test status
Simulation time 122866985 ps
CPU time 1.1 seconds
Started Aug 06 07:27:16 PM PDT 24
Finished Aug 06 07:27:17 PM PDT 24
Peak memory 201040 kb
Host smart-5b28013d-e642-4a04-90ad-a2f9fe3a1464
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527385907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_div_intersig_mubi.527385907
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.3188921622
Short name T341
Test name
Test status
Simulation time 125442979 ps
CPU time 1.18 seconds
Started Aug 06 07:27:16 PM PDT 24
Finished Aug 06 07:27:17 PM PDT 24
Peak memory 200692 kb
Host smart-722dac49-0028-4492-8ec9-58ec966ad7e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188921622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.3188921622
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.2408116825
Short name T388
Test name
Test status
Simulation time 674728921 ps
CPU time 5.46 seconds
Started Aug 06 07:27:11 PM PDT 24
Finished Aug 06 07:27:17 PM PDT 24
Peak memory 201104 kb
Host smart-81809ae4-5162-4d31-ba30-c6f7c8f7f2b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408116825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2408116825
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.886652841
Short name T790
Test name
Test status
Simulation time 2424057074 ps
CPU time 13.48 seconds
Started Aug 06 07:27:12 PM PDT 24
Finished Aug 06 07:27:26 PM PDT 24
Peak memory 201444 kb
Host smart-12117ffa-0eb7-4054-a213-4d01e9dc358f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886652841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_tim
eout.886652841
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1051386804
Short name T506
Test name
Test status
Simulation time 66551763 ps
CPU time 0.96 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:15 PM PDT 24
Peak memory 201120 kb
Host smart-bc83dbf5-74fc-4594-b26b-4f222be07d50
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051386804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.1051386804
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3059066877
Short name T385
Test name
Test status
Simulation time 18976248 ps
CPU time 0.87 seconds
Started Aug 06 07:27:15 PM PDT 24
Finished Aug 06 07:27:16 PM PDT 24
Peak memory 201012 kb
Host smart-403876e0-9f9b-4cda-a6dd-7e50793cb021
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059066877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.3059066877
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2451706581
Short name T476
Test name
Test status
Simulation time 25635074 ps
CPU time 0.93 seconds
Started Aug 06 07:27:16 PM PDT 24
Finished Aug 06 07:27:17 PM PDT 24
Peak memory 201064 kb
Host smart-ff43ab70-25d9-4884-bbbd-6c5aaceed543
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451706581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.2451706581
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.372715923
Short name T189
Test name
Test status
Simulation time 25319460 ps
CPU time 0.79 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:15 PM PDT 24
Peak memory 201048 kb
Host smart-5bf5f000-f9b8-438a-accf-30e771a3aa5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372715923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.372715923
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.1495551812
Short name T636
Test name
Test status
Simulation time 346181553 ps
CPU time 1.69 seconds
Started Aug 06 07:27:30 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 200996 kb
Host smart-638c30aa-2c08-4ab7-8a02-1c291ece5275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495551812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1495551812
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.699876916
Short name T41
Test name
Test status
Simulation time 319342894 ps
CPU time 2.41 seconds
Started Aug 06 07:27:30 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 216456 kb
Host smart-e3f985b2-bc9d-4317-8fca-d034a29e8e72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699876916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr
_sec_cm.699876916
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.4022493065
Short name T610
Test name
Test status
Simulation time 64472057 ps
CPU time 1 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:15 PM PDT 24
Peak memory 201004 kb
Host smart-eb2357b9-7101-43f0-ace6-fc6bd7b544fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022493065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.4022493065
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.3872010446
Short name T375
Test name
Test status
Simulation time 3036706888 ps
CPU time 21.64 seconds
Started Aug 06 07:27:29 PM PDT 24
Finished Aug 06 07:27:51 PM PDT 24
Peak memory 201392 kb
Host smart-4b6c5612-ca4a-4e02-8ae4-53ae350dbf0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872010446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.3872010446
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1460296715
Short name T348
Test name
Test status
Simulation time 141016840 ps
CPU time 1.25 seconds
Started Aug 06 07:27:14 PM PDT 24
Finished Aug 06 07:27:15 PM PDT 24
Peak memory 200812 kb
Host smart-6607e7c9-9c08-4c88-bc3c-678ccf870373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460296715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1460296715
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1470199311
Short name T291
Test name
Test status
Simulation time 14325957 ps
CPU time 0.72 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 201064 kb
Host smart-add14270-e2fd-43ef-b0df-e22e5cc08d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470199311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1470199311
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.2354197616
Short name T196
Test name
Test status
Simulation time 55635283 ps
CPU time 0.85 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:40 PM PDT 24
Peak memory 201076 kb
Host smart-61f9cfaa-51c5-4d85-9624-cade4348bbca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354197616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.2354197616
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.1698555066
Short name T665
Test name
Test status
Simulation time 45521102 ps
CPU time 0.8 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 200260 kb
Host smart-5fc6c36a-16a9-43b5-bc6f-bc332bb1b654
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698555066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1698555066
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.3272259533
Short name T300
Test name
Test status
Simulation time 80658699 ps
CPU time 1.02 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 201140 kb
Host smart-0322bfeb-e442-4081-ac2e-3004d3934b28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272259533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.3272259533
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.4192865913
Short name T774
Test name
Test status
Simulation time 45764326 ps
CPU time 0.95 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:40 PM PDT 24
Peak memory 201052 kb
Host smart-52239abc-c250-4ac8-8471-3c7b744e2eb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192865913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.4192865913
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.2097778825
Short name T472
Test name
Test status
Simulation time 1040168974 ps
CPU time 8.69 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:47 PM PDT 24
Peak memory 201208 kb
Host smart-f0e95320-a464-4269-b61e-dae01520a1b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097778825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.2097778825
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.1580807657
Short name T576
Test name
Test status
Simulation time 999887449 ps
CPU time 4.74 seconds
Started Aug 06 07:30:36 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 201124 kb
Host smart-5f3a5702-369b-4d31-86c0-b1aaa43c25e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580807657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.1580807657
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.2736910606
Short name T357
Test name
Test status
Simulation time 21054703 ps
CPU time 0.73 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 201048 kb
Host smart-09660400-d03d-47bf-96c5-7d69dfb15c5f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736910606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.2736910606
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3659218008
Short name T232
Test name
Test status
Simulation time 61502373 ps
CPU time 1 seconds
Started Aug 06 07:30:42 PM PDT 24
Finished Aug 06 07:30:43 PM PDT 24
Peak memory 201092 kb
Host smart-b4eace5a-f51d-43fa-8e5d-7c8f68efaf32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659218008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.3659218008
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2407453329
Short name T380
Test name
Test status
Simulation time 53345853 ps
CPU time 0.87 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:40 PM PDT 24
Peak memory 201132 kb
Host smart-7499f15a-6766-4e51-a864-5a4b83e1b055
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407453329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.2407453329
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.1042269530
Short name T643
Test name
Test status
Simulation time 18861402 ps
CPU time 0.8 seconds
Started Aug 06 07:30:38 PM PDT 24
Finished Aug 06 07:30:39 PM PDT 24
Peak memory 201096 kb
Host smart-70df698c-9a60-4ea8-a94a-9c0ef2f75238
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042269530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.1042269530
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.107043743
Short name T160
Test name
Test status
Simulation time 1627240580 ps
CPU time 5.86 seconds
Started Aug 06 07:30:38 PM PDT 24
Finished Aug 06 07:30:44 PM PDT 24
Peak memory 201340 kb
Host smart-a1ad1a5f-493f-4575-87c6-89067dd73533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107043743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.107043743
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.1803217787
Short name T246
Test name
Test status
Simulation time 61081436 ps
CPU time 0.98 seconds
Started Aug 06 07:30:38 PM PDT 24
Finished Aug 06 07:30:39 PM PDT 24
Peak memory 201108 kb
Host smart-b87373a4-40fe-479d-b639-cf1f0b8d1bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803217787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.1803217787
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.3606552844
Short name T150
Test name
Test status
Simulation time 61939353 ps
CPU time 1.4 seconds
Started Aug 06 07:30:41 PM PDT 24
Finished Aug 06 07:30:43 PM PDT 24
Peak memory 201068 kb
Host smart-e24f44d6-34bb-421b-b700-45f2aee6c904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606552844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.3606552844
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.1792059559
Short name T203
Test name
Test status
Simulation time 56834615 ps
CPU time 0.9 seconds
Started Aug 06 07:30:37 PM PDT 24
Finished Aug 06 07:30:38 PM PDT 24
Peak memory 201076 kb
Host smart-681209e6-d64f-42da-a16a-460eeaca131a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792059559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.1792059559
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.587062070
Short name T314
Test name
Test status
Simulation time 46173463 ps
CPU time 0.81 seconds
Started Aug 06 07:30:42 PM PDT 24
Finished Aug 06 07:30:43 PM PDT 24
Peak memory 201064 kb
Host smart-7c5dd38b-f97d-4472-a7d0-bb191c10bc9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587062070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkm
gr_alert_test.587062070
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1283617933
Short name T304
Test name
Test status
Simulation time 13235052 ps
CPU time 0.75 seconds
Started Aug 06 07:30:43 PM PDT 24
Finished Aug 06 07:30:44 PM PDT 24
Peak memory 201060 kb
Host smart-4f8bea0c-b949-40e6-ba1b-4bb7f780ae49
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283617933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.1283617933
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.2246247717
Short name T346
Test name
Test status
Simulation time 43642913 ps
CPU time 0.8 seconds
Started Aug 06 07:30:38 PM PDT 24
Finished Aug 06 07:30:39 PM PDT 24
Peak memory 200144 kb
Host smart-ae446418-ec1d-4330-967b-5e7924155b75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246247717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.2246247717
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.4286953504
Short name T544
Test name
Test status
Simulation time 24388863 ps
CPU time 0.89 seconds
Started Aug 06 07:30:41 PM PDT 24
Finished Aug 06 07:30:42 PM PDT 24
Peak memory 201080 kb
Host smart-6c37b526-9552-4c6e-9fb0-9e8823207583
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286953504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.4286953504
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.340218532
Short name T84
Test name
Test status
Simulation time 30120048 ps
CPU time 0.81 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:40 PM PDT 24
Peak memory 201056 kb
Host smart-f1abd12b-7021-4176-818d-0c73b4af9f6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340218532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.340218532
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.2003746846
Short name T534
Test name
Test status
Simulation time 2033075675 ps
CPU time 8.76 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:48 PM PDT 24
Peak memory 201356 kb
Host smart-1419ac0f-a10c-46d3-9726-498d94651a8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003746846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.2003746846
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.3749242076
Short name T438
Test name
Test status
Simulation time 390521655 ps
CPU time 2.13 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 201232 kb
Host smart-2914f4c2-adc8-4218-9659-d0ae21e89479
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749242076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.3749242076
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1350938734
Short name T118
Test name
Test status
Simulation time 69222197 ps
CPU time 1 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 201076 kb
Host smart-7cdaa554-258f-4b03-9d11-c1ec74e64a1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350938734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.1350938734
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2393885246
Short name T238
Test name
Test status
Simulation time 386322743 ps
CPU time 1.98 seconds
Started Aug 06 07:30:42 PM PDT 24
Finished Aug 06 07:30:45 PM PDT 24
Peak memory 201068 kb
Host smart-24115599-10dd-4a69-b227-b97389754579
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393885246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.2393885246
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.4063984538
Short name T192
Test name
Test status
Simulation time 87161423 ps
CPU time 0.99 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 201112 kb
Host smart-1ed71a24-b77e-4b6a-9af1-a66efc6d5f00
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063984538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.4063984538
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.2699329788
Short name T556
Test name
Test status
Simulation time 54349720 ps
CPU time 0.83 seconds
Started Aug 06 07:30:43 PM PDT 24
Finished Aug 06 07:30:44 PM PDT 24
Peak memory 201080 kb
Host smart-e8f07588-dc99-447a-ab35-fb846aa6b8cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699329788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2699329788
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.1622137509
Short name T500
Test name
Test status
Simulation time 1312112758 ps
CPU time 4.91 seconds
Started Aug 06 07:30:43 PM PDT 24
Finished Aug 06 07:30:48 PM PDT 24
Peak memory 201272 kb
Host smart-3813e1b4-9266-45fd-b875-57af07bccaff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622137509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1622137509
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.3703478599
Short name T461
Test name
Test status
Simulation time 23388127 ps
CPU time 0.85 seconds
Started Aug 06 07:30:43 PM PDT 24
Finished Aug 06 07:30:44 PM PDT 24
Peak memory 201032 kb
Host smart-6875b132-9be3-4a16-9225-69be8fbff1fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703478599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.3703478599
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.2469358038
Short name T354
Test name
Test status
Simulation time 5582322852 ps
CPU time 27.01 seconds
Started Aug 06 07:30:44 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201444 kb
Host smart-9b38b86e-1c4d-4688-a7a4-82bc69792eaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469358038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.2469358038
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.2303218417
Short name T70
Test name
Test status
Simulation time 21571512072 ps
CPU time 375.08 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:36:55 PM PDT 24
Peak memory 217208 kb
Host smart-ad294d8c-b77f-4d28-939e-7ec1ee16f88c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2303218417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.2303218417
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.1671616296
Short name T660
Test name
Test status
Simulation time 34834358 ps
CPU time 0.85 seconds
Started Aug 06 07:30:38 PM PDT 24
Finished Aug 06 07:30:39 PM PDT 24
Peak memory 201036 kb
Host smart-ad64a170-7b43-45c8-b202-15f6e49a1ad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671616296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.1671616296
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.992222194
Short name T363
Test name
Test status
Simulation time 15865662 ps
CPU time 0.75 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201152 kb
Host smart-16bc036c-741d-4314-947a-8f94c95eadeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992222194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkm
gr_alert_test.992222194
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.280980348
Short name T406
Test name
Test status
Simulation time 17763540 ps
CPU time 0.82 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:53 PM PDT 24
Peak memory 201000 kb
Host smart-4fd5eef7-5ec2-4a01-9af2-30d33bdf3088
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280980348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.280980348
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.2651610695
Short name T649
Test name
Test status
Simulation time 18815539 ps
CPU time 0.74 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 200320 kb
Host smart-b0aad1ce-a32d-447a-892f-9221955de9d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651610695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2651610695
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.1327264063
Short name T27
Test name
Test status
Simulation time 207769429 ps
CPU time 1.38 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:30:56 PM PDT 24
Peak memory 201172 kb
Host smart-584570fb-95b6-4e01-8242-f26b6cca57fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327264063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.1327264063
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.2975704828
Short name T722
Test name
Test status
Simulation time 31969485 ps
CPU time 0.88 seconds
Started Aug 06 07:30:42 PM PDT 24
Finished Aug 06 07:30:43 PM PDT 24
Peak memory 200984 kb
Host smart-da6d5b41-aa8d-497c-aa7f-6471beb33628
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975704828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.2975704828
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.378972171
Short name T31
Test name
Test status
Simulation time 1063012028 ps
CPU time 5.08 seconds
Started Aug 06 07:30:47 PM PDT 24
Finished Aug 06 07:30:52 PM PDT 24
Peak memory 201124 kb
Host smart-4e1e132e-a8eb-45c7-969a-0282d4d7572d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378972171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.378972171
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.738188042
Short name T347
Test name
Test status
Simulation time 373869842 ps
CPU time 3.34 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:42 PM PDT 24
Peak memory 201220 kb
Host smart-71ba1dd2-7504-476f-89c5-b6986a75be59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738188042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_ti
meout.738188042
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.1699606324
Short name T376
Test name
Test status
Simulation time 126304775 ps
CPU time 1.32 seconds
Started Aug 06 07:30:40 PM PDT 24
Finished Aug 06 07:30:41 PM PDT 24
Peak memory 201088 kb
Host smart-4e176b09-c45e-4d31-b73b-4f6a24f1158e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699606324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.1699606324
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.982002526
Short name T309
Test name
Test status
Simulation time 14253338 ps
CPU time 0.74 seconds
Started Aug 06 07:30:56 PM PDT 24
Finished Aug 06 07:30:56 PM PDT 24
Peak memory 201108 kb
Host smart-80dd1371-e37d-4c00-a17c-cf668c5276ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982002526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.clkmgr_lc_clk_byp_req_intersig_mubi.982002526
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.28368365
Short name T533
Test name
Test status
Simulation time 131724935 ps
CPU time 1.11 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:30:55 PM PDT 24
Peak memory 201104 kb
Host smart-253df88e-6fa9-4b5a-819c-504496bf1571
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28368365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_lc_ctrl_intersig_mubi.28368365
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.2579064452
Short name T45
Test name
Test status
Simulation time 53013952 ps
CPU time 0.83 seconds
Started Aug 06 07:30:39 PM PDT 24
Finished Aug 06 07:30:40 PM PDT 24
Peak memory 201076 kb
Host smart-3e03c066-fdb4-4c2a-859d-89f288b546fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579064452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.2579064452
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.3172376023
Short name T370
Test name
Test status
Simulation time 2399379895 ps
CPU time 7.8 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:31:02 PM PDT 24
Peak memory 201300 kb
Host smart-c32ed39a-16b9-471f-b81b-3d4a0f86d226
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172376023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.3172376023
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.3839277720
Short name T287
Test name
Test status
Simulation time 72068890 ps
CPU time 1.03 seconds
Started Aug 06 07:30:42 PM PDT 24
Finished Aug 06 07:30:43 PM PDT 24
Peak memory 201004 kb
Host smart-9e0b3925-9722-42a9-9248-befc1a629075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839277720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.3839277720
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.1005759172
Short name T146
Test name
Test status
Simulation time 5149764622 ps
CPU time 21.87 seconds
Started Aug 06 07:30:57 PM PDT 24
Finished Aug 06 07:31:19 PM PDT 24
Peak memory 201420 kb
Host smart-b7d7ed53-08e4-4642-896e-b94436315cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005759172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.1005759172
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.2941893384
Short name T72
Test name
Test status
Simulation time 34915932798 ps
CPU time 511.78 seconds
Started Aug 06 07:30:57 PM PDT 24
Finished Aug 06 07:39:28 PM PDT 24
Peak memory 209840 kb
Host smart-b23f88a9-d4c2-44f9-8b8d-312d2b5a1c2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2941893384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.2941893384
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.3317252066
Short name T495
Test name
Test status
Simulation time 38031726 ps
CPU time 0.83 seconds
Started Aug 06 07:30:47 PM PDT 24
Finished Aug 06 07:30:48 PM PDT 24
Peak memory 201068 kb
Host smart-33d193c1-1bd7-4524-9409-cfd7f5aecc39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317252066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.3317252066
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.3439078760
Short name T228
Test name
Test status
Simulation time 17866893 ps
CPU time 0.78 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:30:55 PM PDT 24
Peak memory 201128 kb
Host smart-dcaab540-ccbb-4a97-a04f-084142fe4dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439078760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.3439078760
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2761964778
Short name T687
Test name
Test status
Simulation time 61785564 ps
CPU time 0.96 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201084 kb
Host smart-531fc585-f068-46e4-890a-d8da7e18df66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761964778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.2761964778
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.775386413
Short name T338
Test name
Test status
Simulation time 15374118 ps
CPU time 0.72 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 200252 kb
Host smart-46f7c5fd-6581-4781-913d-96081e42b043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775386413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.775386413
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.3484519878
Short name T329
Test name
Test status
Simulation time 49258962 ps
CPU time 0.97 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201124 kb
Host smart-b32532a8-11e8-4e16-b6fc-1a2e3ac912e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484519878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.3484519878
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.3270955421
Short name T236
Test name
Test status
Simulation time 93486306 ps
CPU time 1.12 seconds
Started Aug 06 07:30:59 PM PDT 24
Finished Aug 06 07:31:00 PM PDT 24
Peak memory 201144 kb
Host smart-9d098c3f-cf8c-41c1-b7b7-07d3c30bbf4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270955421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3270955421
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.2199023314
Short name T459
Test name
Test status
Simulation time 1277943439 ps
CPU time 10.49 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:31:05 PM PDT 24
Peak memory 201108 kb
Host smart-8efaad3c-ca63-4f6b-85f6-8e345d6bd8b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199023314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.2199023314
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.2366734688
Short name T776
Test name
Test status
Simulation time 1344160584 ps
CPU time 7.16 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201188 kb
Host smart-235078b9-bc1b-48f9-9b65-74082529fe4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366734688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.2366734688
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1223977543
Short name T467
Test name
Test status
Simulation time 41066721 ps
CPU time 0.92 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:30:55 PM PDT 24
Peak memory 201048 kb
Host smart-b311f985-adbd-4a65-afda-c5e51f82cd1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223977543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1223977543
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.945275606
Short name T402
Test name
Test status
Simulation time 26260899 ps
CPU time 0.84 seconds
Started Aug 06 07:31:02 PM PDT 24
Finished Aug 06 07:31:03 PM PDT 24
Peak memory 201080 kb
Host smart-fa0e9f4b-723d-4d80-ae3f-6ffb5c2ff0a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945275606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_clk_byp_req_intersig_mubi.945275606
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.4260238296
Short name T217
Test name
Test status
Simulation time 25577854 ps
CPU time 0.86 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201136 kb
Host smart-e181b6ac-7a11-476f-9798-e101b45b5bb1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260238296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.4260238296
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.1501048349
Short name T416
Test name
Test status
Simulation time 16900006 ps
CPU time 0.76 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201068 kb
Host smart-67f870a5-e425-4cec-8dc3-d34ae9c19f44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501048349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.1501048349
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.1056974198
Short name T638
Test name
Test status
Simulation time 1031433458 ps
CPU time 4.31 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:58 PM PDT 24
Peak memory 201224 kb
Host smart-72b3ae8f-fc2f-44d2-acf3-a8ba0e98dd96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056974198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.1056974198
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.3814443776
Short name T462
Test name
Test status
Simulation time 30975773 ps
CPU time 0.83 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201096 kb
Host smart-afe5deb3-4ece-410f-9830-6c372f65fcd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814443776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3814443776
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_trans.1132910260
Short name T327
Test name
Test status
Simulation time 45715327 ps
CPU time 0.83 seconds
Started Aug 06 07:30:59 PM PDT 24
Finished Aug 06 07:31:00 PM PDT 24
Peak memory 201160 kb
Host smart-df2fd8b0-15a1-4bf7-bab2-323ff3cad475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132910260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1132910260
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.1754630803
Short name T365
Test name
Test status
Simulation time 33188307 ps
CPU time 0.82 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201096 kb
Host smart-e45acc47-c1fd-4afc-9091-88bb29a2c282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754630803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.1754630803
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2897797724
Short name T188
Test name
Test status
Simulation time 22709238 ps
CPU time 0.88 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:30:55 PM PDT 24
Peak memory 201104 kb
Host smart-f8d71962-efe2-46b0-9737-54a2f9ca0757
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897797724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.2897797724
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.1497298243
Short name T728
Test name
Test status
Simulation time 23930180 ps
CPU time 0.74 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201064 kb
Host smart-399a23a0-55bb-4677-8803-ffb3aa956057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497298243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.1497298243
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.496124723
Short name T90
Test name
Test status
Simulation time 38370437 ps
CPU time 0.98 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201116 kb
Host smart-1dc1a1e5-db8c-451e-bde8-4b18e8af1740
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496124723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_div_intersig_mubi.496124723
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.482303015
Short name T408
Test name
Test status
Simulation time 18393741 ps
CPU time 0.83 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201044 kb
Host smart-cb19c0ba-d61a-4574-8a02-55af106b9881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482303015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.482303015
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.3282521198
Short name T358
Test name
Test status
Simulation time 2250944171 ps
CPU time 10.14 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:31:04 PM PDT 24
Peak memory 201408 kb
Host smart-168eaf56-b248-443a-a50d-b9af6ed054d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282521198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.3282521198
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.3274044546
Short name T5
Test name
Test status
Simulation time 1818433937 ps
CPU time 14.26 seconds
Started Aug 06 07:30:57 PM PDT 24
Finished Aug 06 07:31:12 PM PDT 24
Peak memory 201184 kb
Host smart-beb525fd-8f05-4f10-971d-01aa7e0321d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274044546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.3274044546
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.1496806658
Short name T274
Test name
Test status
Simulation time 32329348 ps
CPU time 1.01 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201080 kb
Host smart-9e07d076-3c8a-4182-89ec-bcbbe7b8cf25
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496806658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.1496806658
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.2533183991
Short name T399
Test name
Test status
Simulation time 19354667 ps
CPU time 0.82 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201120 kb
Host smart-51f46007-d344-4c2d-b7ab-539768e24005
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533183991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.2533183991
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1656854783
Short name T371
Test name
Test status
Simulation time 31621547 ps
CPU time 0.88 seconds
Started Aug 06 07:30:57 PM PDT 24
Finished Aug 06 07:30:58 PM PDT 24
Peak memory 201056 kb
Host smart-86b01f46-aac3-43f4-9d93-89b9c07630f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656854783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.1656854783
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.4132214090
Short name T435
Test name
Test status
Simulation time 16554349 ps
CPU time 0.75 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201100 kb
Host smart-e7bdeea3-47c8-4b01-bf45-a57f599a635f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132214090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.4132214090
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.3185917469
Short name T656
Test name
Test status
Simulation time 936987537 ps
CPU time 5.53 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:06 PM PDT 24
Peak memory 201336 kb
Host smart-81503c5d-e29b-4a61-a855-c924fcc29143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185917469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.3185917469
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.1614984621
Short name T764
Test name
Test status
Simulation time 46208231 ps
CPU time 0.9 seconds
Started Aug 06 07:30:55 PM PDT 24
Finished Aug 06 07:30:56 PM PDT 24
Peak memory 201032 kb
Host smart-87218356-7764-41a3-8bd4-c6c614600054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614984621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1614984621
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3965932553
Short name T75
Test name
Test status
Simulation time 2036524495 ps
CPU time 14.97 seconds
Started Aug 06 07:31:07 PM PDT 24
Finished Aug 06 07:31:22 PM PDT 24
Peak memory 201412 kb
Host smart-7c79dd43-d5da-4fbd-9d2c-b3b89af964f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965932553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3965932553
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.2412522679
Short name T623
Test name
Test status
Simulation time 125816967021 ps
CPU time 758.19 seconds
Started Aug 06 07:30:56 PM PDT 24
Finished Aug 06 07:43:34 PM PDT 24
Peak memory 217948 kb
Host smart-8280d326-48be-41ee-bc2e-dd6cd199217e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2412522679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.2412522679
Directory /workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.clkmgr_trans.4198426124
Short name T586
Test name
Test status
Simulation time 32393260 ps
CPU time 0.85 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201128 kb
Host smart-a760c05b-f72d-4bbf-a052-f6939f6f683f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198426124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.4198426124
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.3403331748
Short name T515
Test name
Test status
Simulation time 128986269 ps
CPU time 1.19 seconds
Started Aug 06 07:31:01 PM PDT 24
Finished Aug 06 07:31:02 PM PDT 24
Peak memory 201092 kb
Host smart-c74036ba-ff38-44c7-9bcf-30c10df68db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403331748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.3403331748
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.3238356694
Short name T95
Test name
Test status
Simulation time 23313557 ps
CPU time 0.89 seconds
Started Aug 06 07:31:02 PM PDT 24
Finished Aug 06 07:31:03 PM PDT 24
Peak memory 201084 kb
Host smart-bac1d9d3-90b9-4dcf-983a-93ca98780825
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238356694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.3238356694
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.1749063316
Short name T767
Test name
Test status
Simulation time 28475151 ps
CPU time 0.8 seconds
Started Aug 06 07:30:57 PM PDT 24
Finished Aug 06 07:30:58 PM PDT 24
Peak memory 200244 kb
Host smart-4719c68e-3642-4c51-9095-0719f939bd3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749063316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1749063316
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.420482327
Short name T445
Test name
Test status
Simulation time 32467970 ps
CPU time 0.88 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201096 kb
Host smart-55181dc2-a996-44fe-b605-93e4c1d57fe0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420482327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_div_intersig_mubi.420482327
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.945558730
Short name T588
Test name
Test status
Simulation time 44143687 ps
CPU time 0.94 seconds
Started Aug 06 07:30:59 PM PDT 24
Finished Aug 06 07:31:00 PM PDT 24
Peak memory 201144 kb
Host smart-4fc19b96-fb02-45f7-bb3b-45ef071fcfdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945558730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.945558730
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.1110742558
Short name T15
Test name
Test status
Simulation time 1160460391 ps
CPU time 9.35 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:31:02 PM PDT 24
Peak memory 201148 kb
Host smart-f88e9ce8-1508-4d3c-8301-7fc1e0c5f854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110742558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1110742558
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.1987806128
Short name T632
Test name
Test status
Simulation time 159289282 ps
CPU time 1.25 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 201208 kb
Host smart-4ccbc004-3cdd-4b19-bbbc-239d315578a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987806128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.1987806128
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.4099249659
Short name T366
Test name
Test status
Simulation time 39335953 ps
CPU time 0.95 seconds
Started Aug 06 07:31:02 PM PDT 24
Finished Aug 06 07:31:03 PM PDT 24
Peak memory 201092 kb
Host smart-19c54cd1-d0e2-496f-a37b-b7072099e5dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099249659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.4099249659
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.3292752124
Short name T619
Test name
Test status
Simulation time 13309958 ps
CPU time 0.74 seconds
Started Aug 06 07:31:03 PM PDT 24
Finished Aug 06 07:31:04 PM PDT 24
Peak memory 201104 kb
Host smart-ed8cced6-0226-4f6f-b71d-91c28a68c72d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292752124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.3292752124
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.2696921687
Short name T342
Test name
Test status
Simulation time 18504315 ps
CPU time 0.84 seconds
Started Aug 06 07:30:59 PM PDT 24
Finished Aug 06 07:31:00 PM PDT 24
Peak memory 201136 kb
Host smart-72c842ae-4d4a-4423-8219-790b884e8c03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696921687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.2696921687
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.442610552
Short name T88
Test name
Test status
Simulation time 15774247 ps
CPU time 0.75 seconds
Started Aug 06 07:30:56 PM PDT 24
Finished Aug 06 07:30:56 PM PDT 24
Peak memory 201096 kb
Host smart-366e827c-4317-4adf-952b-0cc5de9c0997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442610552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.442610552
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.618660283
Short name T811
Test name
Test status
Simulation time 784677014 ps
CPU time 4.58 seconds
Started Aug 06 07:31:06 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201276 kb
Host smart-d078152d-7991-4510-8f13-f473acf50335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618660283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.618660283
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.3733934361
Short name T351
Test name
Test status
Simulation time 89277775 ps
CPU time 1.05 seconds
Started Aug 06 07:30:54 PM PDT 24
Finished Aug 06 07:30:55 PM PDT 24
Peak memory 201104 kb
Host smart-5ab725b9-7419-4778-b84d-b880a3d0758c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733934361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3733934361
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.3259529559
Short name T30
Test name
Test status
Simulation time 7216603270 ps
CPU time 39.44 seconds
Started Aug 06 07:31:07 PM PDT 24
Finished Aug 06 07:31:46 PM PDT 24
Peak memory 201428 kb
Host smart-9ce0a144-2cd0-4853-8f5f-be5ae12f5fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259529559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.3259529559
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.1700096504
Short name T666
Test name
Test status
Simulation time 84981262431 ps
CPU time 452 seconds
Started Aug 06 07:30:55 PM PDT 24
Finished Aug 06 07:38:28 PM PDT 24
Peak memory 209732 kb
Host smart-eec0fae4-9dbc-4689-9c02-5b4bc2f64823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1700096504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.1700096504
Directory /workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.clkmgr_trans.825536818
Short name T505
Test name
Test status
Simulation time 41347737 ps
CPU time 0.99 seconds
Started Aug 06 07:30:56 PM PDT 24
Finished Aug 06 07:30:57 PM PDT 24
Peak memory 201048 kb
Host smart-80fcaf94-ba36-4502-92e1-47db96ec3441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825536818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.825536818
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.3814111429
Short name T557
Test name
Test status
Simulation time 81704399 ps
CPU time 1.04 seconds
Started Aug 06 07:31:02 PM PDT 24
Finished Aug 06 07:31:04 PM PDT 24
Peak memory 201088 kb
Host smart-49b691dd-f3d5-4fde-a75d-0a090be3279c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814111429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.3814111429
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1454770651
Short name T813
Test name
Test status
Simulation time 114679282 ps
CPU time 1.24 seconds
Started Aug 06 07:31:03 PM PDT 24
Finished Aug 06 07:31:04 PM PDT 24
Peak memory 201108 kb
Host smart-5de4c3fe-5d15-49b7-96c2-5ca110cb7f3b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454770651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.1454770651
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1085009867
Short name T179
Test name
Test status
Simulation time 16774033 ps
CPU time 0.76 seconds
Started Aug 06 07:31:04 PM PDT 24
Finished Aug 06 07:31:05 PM PDT 24
Peak memory 200292 kb
Host smart-52cbf70f-ea44-4358-b60c-8ad9aeea7cde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085009867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1085009867
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.3232689959
Short name T795
Test name
Test status
Simulation time 18555738 ps
CPU time 0.84 seconds
Started Aug 06 07:31:04 PM PDT 24
Finished Aug 06 07:31:05 PM PDT 24
Peak memory 201092 kb
Host smart-83a16217-cc69-4a6b-954d-789199471904
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232689959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.3232689959
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.1154454268
Short name T465
Test name
Test status
Simulation time 27290447 ps
CPU time 0.9 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:30:54 PM PDT 24
Peak memory 200312 kb
Host smart-d582df11-4a2f-47d8-b3f4-6b6e86e1debc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154454268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1154454268
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.507412044
Short name T778
Test name
Test status
Simulation time 333819547 ps
CPU time 2.54 seconds
Started Aug 06 07:31:03 PM PDT 24
Finished Aug 06 07:31:06 PM PDT 24
Peak memory 201144 kb
Host smart-1e5494a2-ced3-452a-84f2-6eaae3be7e11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507412044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.507412044
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.3492679645
Short name T629
Test name
Test status
Simulation time 1482639580 ps
CPU time 6.35 seconds
Started Aug 06 07:30:53 PM PDT 24
Finished Aug 06 07:31:00 PM PDT 24
Peak memory 201208 kb
Host smart-5d7e8a5d-e638-4353-8df2-3261b0a7bd79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492679645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.3492679645
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.2750417997
Short name T437
Test name
Test status
Simulation time 28037761 ps
CPU time 0.83 seconds
Started Aug 06 07:31:02 PM PDT 24
Finished Aug 06 07:31:03 PM PDT 24
Peak memory 201068 kb
Host smart-1b5c653b-6714-41e7-9bf6-f03f4b8db439
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750417997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.2750417997
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1948566387
Short name T383
Test name
Test status
Simulation time 76373695 ps
CPU time 0.98 seconds
Started Aug 06 07:30:56 PM PDT 24
Finished Aug 06 07:30:57 PM PDT 24
Peak memory 201116 kb
Host smart-0acc88b3-1088-44b8-ae9c-ec25db3c9747
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948566387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1948566387
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2221635047
Short name T344
Test name
Test status
Simulation time 375357738 ps
CPU time 1.97 seconds
Started Aug 06 07:31:06 PM PDT 24
Finished Aug 06 07:31:09 PM PDT 24
Peak memory 201080 kb
Host smart-d8474d81-6ee2-40aa-a171-f7f9d40be797
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221635047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.2221635047
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.1707417361
Short name T374
Test name
Test status
Simulation time 28409688 ps
CPU time 0.79 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201068 kb
Host smart-00eadbf5-da71-4da5-8bca-c5713b82aa0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707417361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.1707417361
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.4054051840
Short name T640
Test name
Test status
Simulation time 1297560003 ps
CPU time 7.48 seconds
Started Aug 06 07:31:03 PM PDT 24
Finished Aug 06 07:31:10 PM PDT 24
Peak memory 201288 kb
Host smart-3b4a4529-87d4-4890-b919-09f088cb8b96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054051840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.4054051840
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.829184635
Short name T197
Test name
Test status
Simulation time 33501400 ps
CPU time 0.95 seconds
Started Aug 06 07:31:03 PM PDT 24
Finished Aug 06 07:31:04 PM PDT 24
Peak memory 201052 kb
Host smart-8973bc93-82c1-4533-b12a-fa81ba76b981
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829184635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.829184635
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.3396950970
Short name T147
Test name
Test status
Simulation time 8169714758 ps
CPU time 32.87 seconds
Started Aug 06 07:31:06 PM PDT 24
Finished Aug 06 07:31:39 PM PDT 24
Peak memory 201468 kb
Host smart-91bdfa06-9027-4e3b-aa17-c19dcb77005e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396950970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.3396950970
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.3799267261
Short name T170
Test name
Test status
Simulation time 60752471999 ps
CPU time 342.43 seconds
Started Aug 06 07:30:57 PM PDT 24
Finished Aug 06 07:36:40 PM PDT 24
Peak memory 217872 kb
Host smart-1c594dfe-16a0-4188-a9eb-40d6abf1de79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3799267261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.3799267261
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.3923384474
Short name T631
Test name
Test status
Simulation time 53564312 ps
CPU time 0.96 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201088 kb
Host smart-c2ec370c-dd9d-48f0-9227-d8ed869550ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923384474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3923384474
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.3039761714
Short name T269
Test name
Test status
Simulation time 14838225 ps
CPU time 0.75 seconds
Started Aug 06 07:31:01 PM PDT 24
Finished Aug 06 07:31:02 PM PDT 24
Peak memory 201012 kb
Host smart-275ea6e1-abec-413b-8ec7-3f12276bb742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039761714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.3039761714
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.295564655
Short name T89
Test name
Test status
Simulation time 19946609 ps
CPU time 0.82 seconds
Started Aug 06 07:31:01 PM PDT 24
Finished Aug 06 07:31:02 PM PDT 24
Peak memory 200864 kb
Host smart-b0d332ad-0c85-48d9-967a-9b3e528cc0d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295564655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.295564655
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.117968048
Short name T657
Test name
Test status
Simulation time 39852332 ps
CPU time 0.82 seconds
Started Aug 06 07:30:58 PM PDT 24
Finished Aug 06 07:30:59 PM PDT 24
Peak memory 200308 kb
Host smart-ee4be379-1b9b-4033-9684-a8b87eb58ee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117968048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.117968048
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.327692267
Short name T165
Test name
Test status
Simulation time 38614956 ps
CPU time 0.81 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201100 kb
Host smart-8164944c-c092-4269-9d7f-e563e7e2cb43
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327692267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_div_intersig_mubi.327692267
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.4004895573
Short name T86
Test name
Test status
Simulation time 40551491 ps
CPU time 0.79 seconds
Started Aug 06 07:30:59 PM PDT 24
Finished Aug 06 07:31:00 PM PDT 24
Peak memory 201144 kb
Host smart-e4928d81-5900-484b-9f78-2fa341659783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004895573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.4004895573
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.1659429189
Short name T635
Test name
Test status
Simulation time 2115357054 ps
CPU time 16.19 seconds
Started Aug 06 07:30:59 PM PDT 24
Finished Aug 06 07:31:15 PM PDT 24
Peak memory 201428 kb
Host smart-3e12143d-ce67-4396-8725-ea908e5dccb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659429189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1659429189
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.426799382
Short name T401
Test name
Test status
Simulation time 2061053427 ps
CPU time 14.41 seconds
Started Aug 06 07:31:07 PM PDT 24
Finished Aug 06 07:31:21 PM PDT 24
Peak memory 201332 kb
Host smart-c267e815-b0a8-4044-bef0-8eea809fad5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426799382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_ti
meout.426799382
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.1620045314
Short name T441
Test name
Test status
Simulation time 19422340 ps
CPU time 0.84 seconds
Started Aug 06 07:31:07 PM PDT 24
Finished Aug 06 07:31:08 PM PDT 24
Peak memory 201032 kb
Host smart-a6a1762e-8140-4c01-b18d-2845bf987419
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620045314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.1620045314
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3622684155
Short name T209
Test name
Test status
Simulation time 46281716 ps
CPU time 0.98 seconds
Started Aug 06 07:30:58 PM PDT 24
Finished Aug 06 07:30:59 PM PDT 24
Peak memory 201136 kb
Host smart-913c5989-a327-44f4-b6a6-b0d236e5237f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622684155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3622684155
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1412893129
Short name T482
Test name
Test status
Simulation time 25984551 ps
CPU time 0.91 seconds
Started Aug 06 07:31:01 PM PDT 24
Finished Aug 06 07:31:02 PM PDT 24
Peak memory 201108 kb
Host smart-a8f1ebf6-6846-4111-88a1-2e701734599f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412893129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.1412893129
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.3336733328
Short name T202
Test name
Test status
Simulation time 14838601 ps
CPU time 0.75 seconds
Started Aug 06 07:30:57 PM PDT 24
Finished Aug 06 07:30:58 PM PDT 24
Peak memory 201028 kb
Host smart-c7878371-e538-4cef-9b2b-be4c206297a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336733328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.3336733328
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.333698156
Short name T164
Test name
Test status
Simulation time 417377255 ps
CPU time 2.73 seconds
Started Aug 06 07:30:58 PM PDT 24
Finished Aug 06 07:31:01 PM PDT 24
Peak memory 201128 kb
Host smart-edfaff97-80da-40b4-a3e4-ca0ebe5a92f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333698156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.333698156
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.2422730239
Short name T52
Test name
Test status
Simulation time 79464827 ps
CPU time 1.04 seconds
Started Aug 06 07:31:07 PM PDT 24
Finished Aug 06 07:31:08 PM PDT 24
Peak memory 201092 kb
Host smart-25f9d7b6-29bd-4439-b5b8-c27685767408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422730239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2422730239
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.670316530
Short name T796
Test name
Test status
Simulation time 2983435437 ps
CPU time 21.69 seconds
Started Aug 06 07:31:00 PM PDT 24
Finished Aug 06 07:31:22 PM PDT 24
Peak memory 201484 kb
Host smart-287e4825-06fd-4ba8-86b6-f3d6ef9c57b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670316530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.670316530
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.1805199208
Short name T439
Test name
Test status
Simulation time 25504628 ps
CPU time 0.88 seconds
Started Aug 06 07:31:01 PM PDT 24
Finished Aug 06 07:31:02 PM PDT 24
Peak memory 201116 kb
Host smart-1f5d338c-78fb-4b0b-a866-1f1b3351a421
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805199208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1805199208
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.698492645
Short name T454
Test name
Test status
Simulation time 224418151 ps
CPU time 1.36 seconds
Started Aug 06 07:31:16 PM PDT 24
Finished Aug 06 07:31:18 PM PDT 24
Peak memory 201056 kb
Host smart-66a33b03-43f1-4ef9-be74-7e66b38148c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698492645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm
gr_alert_test.698492645
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.4124269082
Short name T99
Test name
Test status
Simulation time 39887907 ps
CPU time 0.91 seconds
Started Aug 06 07:31:17 PM PDT 24
Finished Aug 06 07:31:18 PM PDT 24
Peak memory 201060 kb
Host smart-aa19420e-2981-4c77-bd28-46d4ee4e7473
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124269082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.4124269082
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.273329896
Short name T690
Test name
Test status
Simulation time 13226624 ps
CPU time 0.7 seconds
Started Aug 06 07:31:14 PM PDT 24
Finished Aug 06 07:31:15 PM PDT 24
Peak memory 200296 kb
Host smart-83bebb9e-4cec-4d4e-8ae9-182a0a347220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273329896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.273329896
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.501058231
Short name T432
Test name
Test status
Simulation time 76407190 ps
CPU time 1.05 seconds
Started Aug 06 07:31:10 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201144 kb
Host smart-1ecdd967-2304-4825-be93-754c89ec4889
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501058231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_div_intersig_mubi.501058231
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.849840177
Short name T262
Test name
Test status
Simulation time 13702899 ps
CPU time 0.76 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:10 PM PDT 24
Peak memory 201020 kb
Host smart-5d2afd66-7df8-4a33-8688-a6082678570b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849840177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.849840177
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.1029049725
Short name T14
Test name
Test status
Simulation time 704653293 ps
CPU time 3.89 seconds
Started Aug 06 07:31:08 PM PDT 24
Finished Aug 06 07:31:12 PM PDT 24
Peak memory 201168 kb
Host smart-0d63d940-f026-4dae-8cd3-1e42e9ff2280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029049725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1029049725
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.89754174
Short name T689
Test name
Test status
Simulation time 2310972673 ps
CPU time 11.61 seconds
Started Aug 06 07:31:11 PM PDT 24
Finished Aug 06 07:31:23 PM PDT 24
Peak memory 201500 kb
Host smart-ab08264b-7888-492b-bf0a-bacdf9869773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89754174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_tim
eout.89754174
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.3348340693
Short name T231
Test name
Test status
Simulation time 28838095 ps
CPU time 1 seconds
Started Aug 06 07:31:08 PM PDT 24
Finished Aug 06 07:31:09 PM PDT 24
Peak memory 201024 kb
Host smart-8cb8e259-8a1c-4dad-b554-951b0e480848
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348340693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.3348340693
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3770408940
Short name T227
Test name
Test status
Simulation time 34036616 ps
CPU time 0.77 seconds
Started Aug 06 07:31:14 PM PDT 24
Finished Aug 06 07:31:14 PM PDT 24
Peak memory 201064 kb
Host smart-2be66935-1108-4f5c-bfa9-4e8f4a9c4959
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770408940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3770408940
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1458950080
Short name T266
Test name
Test status
Simulation time 27083853 ps
CPU time 0.91 seconds
Started Aug 06 07:31:17 PM PDT 24
Finished Aug 06 07:31:18 PM PDT 24
Peak memory 201032 kb
Host smart-7b4cc7e8-643c-4d93-8c94-18de1b26564c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458950080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.1458950080
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.2126857192
Short name T759
Test name
Test status
Simulation time 26521204 ps
CPU time 0.79 seconds
Started Aug 06 07:31:13 PM PDT 24
Finished Aug 06 07:31:14 PM PDT 24
Peak memory 201100 kb
Host smart-5cbb7a58-543c-419a-a953-4a9f96e1dbfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126857192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2126857192
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.154678889
Short name T449
Test name
Test status
Simulation time 211152932 ps
CPU time 1.8 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201132 kb
Host smart-d49a112b-973a-45f0-8e62-1c0c54985421
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154678889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.154678889
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.2111616080
Short name T343
Test name
Test status
Simulation time 16470898 ps
CPU time 0.81 seconds
Started Aug 06 07:31:10 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201052 kb
Host smart-1499065f-5251-4428-ac74-05d18d8431e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111616080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2111616080
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.3817016735
Short name T29
Test name
Test status
Simulation time 2971666758 ps
CPU time 12.86 seconds
Started Aug 06 07:31:08 PM PDT 24
Finished Aug 06 07:31:21 PM PDT 24
Peak memory 201516 kb
Host smart-7020a6de-a084-42f0-9298-5433af91c099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817016735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.3817016735
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.3085684592
Short name T484
Test name
Test status
Simulation time 20558197 ps
CPU time 0.81 seconds
Started Aug 06 07:31:11 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201048 kb
Host smart-3608bab9-48ef-44b6-af3c-3ead77878df8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085684592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3085684592
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.505722558
Short name T570
Test name
Test status
Simulation time 48425314 ps
CPU time 0.89 seconds
Started Aug 06 07:31:18 PM PDT 24
Finished Aug 06 07:31:19 PM PDT 24
Peak memory 201144 kb
Host smart-26863cc7-6b09-449e-9f59-4c9c19b7d696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505722558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkm
gr_alert_test.505722558
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.3908338146
Short name T714
Test name
Test status
Simulation time 31066575 ps
CPU time 0.86 seconds
Started Aug 06 07:31:18 PM PDT 24
Finished Aug 06 07:31:19 PM PDT 24
Peak memory 201088 kb
Host smart-5d1e5d6f-8613-4421-b102-fedacc0cf820
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908338146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.3908338146
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.994146659
Short name T178
Test name
Test status
Simulation time 18241096 ps
CPU time 0.76 seconds
Started Aug 06 07:31:10 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 200256 kb
Host smart-2b1310ea-ed71-4f1e-9b34-fe65c90c5076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994146659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.994146659
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.4167680161
Short name T651
Test name
Test status
Simulation time 20372248 ps
CPU time 0.89 seconds
Started Aug 06 07:31:16 PM PDT 24
Finished Aug 06 07:31:17 PM PDT 24
Peak memory 201116 kb
Host smart-944c1e16-cd90-442d-afe2-f3af6c775caf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167680161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.4167680161
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.1937626358
Short name T717
Test name
Test status
Simulation time 18949535 ps
CPU time 0.79 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:09 PM PDT 24
Peak memory 200972 kb
Host smart-012ddc4b-cfa5-4d49-b6c5-c8bdfc37ca87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937626358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.1937626358
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.3933773723
Short name T361
Test name
Test status
Simulation time 441714523 ps
CPU time 3.97 seconds
Started Aug 06 07:31:15 PM PDT 24
Finished Aug 06 07:31:19 PM PDT 24
Peak memory 201128 kb
Host smart-393ff0ef-403a-4ec1-b2f2-ca7eda064490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933773723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3933773723
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.1003331538
Short name T648
Test name
Test status
Simulation time 2184423103 ps
CPU time 12.26 seconds
Started Aug 06 07:31:10 PM PDT 24
Finished Aug 06 07:31:22 PM PDT 24
Peak memory 201332 kb
Host smart-6b18e38e-5a1e-470f-b079-999f20a6ad07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003331538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.1003331538
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2338098348
Short name T270
Test name
Test status
Simulation time 227318274 ps
CPU time 1.51 seconds
Started Aug 06 07:31:18 PM PDT 24
Finished Aug 06 07:31:19 PM PDT 24
Peak memory 201132 kb
Host smart-b42c62aa-cd46-4f78-89a0-8866bbf8353b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338098348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.2338098348
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.1245184500
Short name T448
Test name
Test status
Simulation time 35583776 ps
CPU time 0.94 seconds
Started Aug 06 07:31:10 PM PDT 24
Finished Aug 06 07:31:11 PM PDT 24
Peak memory 201136 kb
Host smart-f862de6b-b302-4f24-a8cf-f857d60a0f6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245184500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.1245184500
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2187619647
Short name T750
Test name
Test status
Simulation time 46198774 ps
CPU time 0.85 seconds
Started Aug 06 07:31:17 PM PDT 24
Finished Aug 06 07:31:18 PM PDT 24
Peak memory 201036 kb
Host smart-b9226222-9585-4fff-b35a-3a71c0da2e89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187619647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.2187619647
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.2171655582
Short name T530
Test name
Test status
Simulation time 14263441 ps
CPU time 0.75 seconds
Started Aug 06 07:31:08 PM PDT 24
Finished Aug 06 07:31:09 PM PDT 24
Peak memory 201084 kb
Host smart-0dad5b32-73e0-4520-b15d-fe8784045042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171655582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.2171655582
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.4079554517
Short name T419
Test name
Test status
Simulation time 938985820 ps
CPU time 3.54 seconds
Started Aug 06 07:31:16 PM PDT 24
Finished Aug 06 07:31:19 PM PDT 24
Peak memory 201284 kb
Host smart-233c4a86-f0e5-42f7-8079-32885ca39900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079554517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.4079554517
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.22050144
Short name T367
Test name
Test status
Simulation time 22371289 ps
CPU time 0.86 seconds
Started Aug 06 07:31:13 PM PDT 24
Finished Aug 06 07:31:14 PM PDT 24
Peak memory 201084 kb
Host smart-df55d97e-24f4-4990-9edd-29e8e95aa342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22050144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.22050144
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.2039322089
Short name T522
Test name
Test status
Simulation time 5379413075 ps
CPU time 39.89 seconds
Started Aug 06 07:31:16 PM PDT 24
Finished Aug 06 07:31:56 PM PDT 24
Peak memory 201484 kb
Host smart-f8b4fa86-6f01-4519-a7d7-b178a5488eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039322089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.2039322089
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.1466688448
Short name T220
Test name
Test status
Simulation time 127212778 ps
CPU time 1.13 seconds
Started Aug 06 07:31:09 PM PDT 24
Finished Aug 06 07:31:10 PM PDT 24
Peak memory 201164 kb
Host smart-4a541e8b-0ef9-4233-84b8-9e4d24f22511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466688448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1466688448
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.1702207715
Short name T56
Test name
Test status
Simulation time 25952269 ps
CPU time 0.9 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 201092 kb
Host smart-a2176236-19c8-4240-89f4-d93552aeab15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702207715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.1702207715
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.688563021
Short name T451
Test name
Test status
Simulation time 155142072 ps
CPU time 1.24 seconds
Started Aug 06 07:27:29 PM PDT 24
Finished Aug 06 07:27:30 PM PDT 24
Peak memory 201140 kb
Host smart-238a03bf-4bc8-4b12-92ed-73a09c834728
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688563021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.688563021
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.1894593159
Short name T499
Test name
Test status
Simulation time 17218730 ps
CPU time 0.73 seconds
Started Aug 06 07:27:32 PM PDT 24
Finished Aug 06 07:27:33 PM PDT 24
Peak memory 200280 kb
Host smart-63b25b12-e8b1-4397-98d1-e6ae338d93e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894593159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1894593159
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.2576700649
Short name T225
Test name
Test status
Simulation time 58643449 ps
CPU time 0.92 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 201104 kb
Host smart-2247c448-7470-4a7e-981d-7344e86e7674
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576700649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.2576700649
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.530297295
Short name T647
Test name
Test status
Simulation time 23885011 ps
CPU time 0.86 seconds
Started Aug 06 07:27:30 PM PDT 24
Finished Aug 06 07:27:31 PM PDT 24
Peak memory 201076 kb
Host smart-e9a23999-4923-4df6-98a2-cc2642266429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530297295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.530297295
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.1693430588
Short name T615
Test name
Test status
Simulation time 322648354 ps
CPU time 2.97 seconds
Started Aug 06 07:27:29 PM PDT 24
Finished Aug 06 07:27:33 PM PDT 24
Peak memory 201088 kb
Host smart-aea539d9-2724-4b82-8c75-bad25ce7f190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693430588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.1693430588
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.1310465967
Short name T756
Test name
Test status
Simulation time 1955243042 ps
CPU time 8.23 seconds
Started Aug 06 07:27:30 PM PDT 24
Finished Aug 06 07:27:38 PM PDT 24
Peak memory 201168 kb
Host smart-a1b3500c-c83e-4853-ad5c-103ffbebe3d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310465967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.1310465967
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3130229221
Short name T50
Test name
Test status
Simulation time 33223618 ps
CPU time 0.9 seconds
Started Aug 06 07:27:34 PM PDT 24
Finished Aug 06 07:27:35 PM PDT 24
Peak memory 201092 kb
Host smart-40b069d0-0a85-4ee3-aca3-4af24d91d238
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130229221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.3130229221
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.131617811
Short name T345
Test name
Test status
Simulation time 19634115 ps
CPU time 0.79 seconds
Started Aug 06 07:27:30 PM PDT 24
Finished Aug 06 07:27:31 PM PDT 24
Peak memory 201032 kb
Host smart-ce95e662-2cdc-435a-8cde-41b317e80170
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131617811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_clk_byp_req_intersig_mubi.131617811
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.3320975088
Short name T719
Test name
Test status
Simulation time 16955777 ps
CPU time 0.76 seconds
Started Aug 06 07:27:32 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 201092 kb
Host smart-f80cad95-7fb4-4644-b78c-d662c7dbe22a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320975088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.3320975088
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.195183249
Short name T608
Test name
Test status
Simulation time 17553054 ps
CPU time 0.74 seconds
Started Aug 06 07:27:33 PM PDT 24
Finished Aug 06 07:27:34 PM PDT 24
Peak memory 201104 kb
Host smart-7b7ba9bb-af70-44bf-9a4e-c1c46e7dd981
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195183249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.195183249
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.3451314655
Short name T655
Test name
Test status
Simulation time 470709363 ps
CPU time 3.03 seconds
Started Aug 06 07:27:33 PM PDT 24
Finished Aug 06 07:27:36 PM PDT 24
Peak memory 201088 kb
Host smart-8bf732c9-3854-4b19-a6c9-83fa277ea1a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451314655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.3451314655
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.4124308878
Short name T566
Test name
Test status
Simulation time 22950407 ps
CPU time 0.86 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 201036 kb
Host smart-f63a387d-df55-4764-b722-97176b772c90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124308878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.4124308878
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.2364575633
Short name T589
Test name
Test status
Simulation time 2996648326 ps
CPU time 12.28 seconds
Started Aug 06 07:27:34 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 201432 kb
Host smart-84a3fe1b-2f52-4c0f-9f8f-6f1e756a5558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364575633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.2364575633
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.2341578786
Short name T194
Test name
Test status
Simulation time 515716022280 ps
CPU time 2236.27 seconds
Started Aug 06 07:27:35 PM PDT 24
Finished Aug 06 08:04:51 PM PDT 24
Peak memory 217264 kb
Host smart-6619bedf-08b6-4a51-b6bc-e022272c95bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2341578786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.2341578786
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.2218622414
Short name T251
Test name
Test status
Simulation time 29158699 ps
CPU time 0.93 seconds
Started Aug 06 07:27:29 PM PDT 24
Finished Aug 06 07:27:30 PM PDT 24
Peak memory 201076 kb
Host smart-c3b93674-9295-474b-9192-b0c490e6d496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218622414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2218622414
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.1632656145
Short name T824
Test name
Test status
Simulation time 43003665 ps
CPU time 0.81 seconds
Started Aug 06 07:27:28 PM PDT 24
Finished Aug 06 07:27:29 PM PDT 24
Peak memory 201124 kb
Host smart-3041d776-a932-4541-8460-a46abd753179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632656145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.1632656145
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.2611996809
Short name T737
Test name
Test status
Simulation time 86297641 ps
CPU time 1 seconds
Started Aug 06 07:27:29 PM PDT 24
Finished Aug 06 07:27:31 PM PDT 24
Peak memory 201012 kb
Host smart-1e8b83f7-e624-4096-a001-1d9fe5327a82
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611996809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.2611996809
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.462422864
Short name T182
Test name
Test status
Simulation time 13379881 ps
CPU time 0.72 seconds
Started Aug 06 07:27:29 PM PDT 24
Finished Aug 06 07:27:30 PM PDT 24
Peak memory 200284 kb
Host smart-90bc4ffb-6e11-4d2a-a27b-c6e049bc9ddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462422864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.462422864
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.2496139040
Short name T308
Test name
Test status
Simulation time 47352323 ps
CPU time 1 seconds
Started Aug 06 07:27:32 PM PDT 24
Finished Aug 06 07:27:33 PM PDT 24
Peak memory 201096 kb
Host smart-d5e6f7ab-edee-4a5a-8d07-cdd5b3062974
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496139040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.2496139040
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.2431676405
Short name T6
Test name
Test status
Simulation time 53481745 ps
CPU time 0.89 seconds
Started Aug 06 07:27:36 PM PDT 24
Finished Aug 06 07:27:37 PM PDT 24
Peak memory 201080 kb
Host smart-5bb6afab-119c-436e-8d83-5f9052306018
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431676405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2431676405
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.3399576958
Short name T683
Test name
Test status
Simulation time 1731336536 ps
CPU time 8.18 seconds
Started Aug 06 07:27:35 PM PDT 24
Finished Aug 06 07:27:44 PM PDT 24
Peak memory 201132 kb
Host smart-2899f571-7493-4c92-a82a-aa4aa9656e0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399576958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3399576958
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.1091606085
Short name T650
Test name
Test status
Simulation time 502674759 ps
CPU time 4.01 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:35 PM PDT 24
Peak memory 201228 kb
Host smart-08714759-09db-4618-b2b0-92eb224a66bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091606085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.1091606085
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.2710553547
Short name T119
Test name
Test status
Simulation time 25649682 ps
CPU time 0.93 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 201108 kb
Host smart-e3c88cf8-fb33-4631-af0c-e1e72bbfc200
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710553547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.2710553547
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2441293485
Short name T219
Test name
Test status
Simulation time 29216666 ps
CPU time 0.86 seconds
Started Aug 06 07:27:35 PM PDT 24
Finished Aug 06 07:27:36 PM PDT 24
Peak memory 201092 kb
Host smart-161a540d-1b79-4703-b8f6-efd3e994fc9b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441293485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.2441293485
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2131348028
Short name T791
Test name
Test status
Simulation time 104580303 ps
CPU time 1.14 seconds
Started Aug 06 07:27:28 PM PDT 24
Finished Aug 06 07:27:29 PM PDT 24
Peak memory 200988 kb
Host smart-4ee0bd21-2a88-4bd8-a04c-b844a50bcfc2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131348028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.2131348028
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.1133064177
Short name T692
Test name
Test status
Simulation time 21774938 ps
CPU time 0.77 seconds
Started Aug 06 07:27:36 PM PDT 24
Finished Aug 06 07:27:37 PM PDT 24
Peak memory 201060 kb
Host smart-b340cb61-f134-4fff-82cd-79610d44def1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133064177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1133064177
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.2743093043
Short name T766
Test name
Test status
Simulation time 1119689218 ps
CPU time 4.28 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:35 PM PDT 24
Peak memory 201328 kb
Host smart-c460d235-7474-4c5b-816d-d76aeb44db6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743093043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2743093043
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.271497832
Short name T411
Test name
Test status
Simulation time 35599028 ps
CPU time 0.88 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 201052 kb
Host smart-ef8e09e2-9af2-45f4-b2d8-82e6b1e42ef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271497832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.271497832
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.385235781
Short name T216
Test name
Test status
Simulation time 190462985 ps
CPU time 1.66 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:33 PM PDT 24
Peak memory 201152 kb
Host smart-f36ade1e-cc70-4118-82af-c0d419c8ead8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385235781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.385235781
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.4265525215
Short name T653
Test name
Test status
Simulation time 37722873 ps
CPU time 1.04 seconds
Started Aug 06 07:27:32 PM PDT 24
Finished Aug 06 07:27:33 PM PDT 24
Peak memory 201044 kb
Host smart-636e541d-c895-43e7-9c21-df4b91f0e2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265525215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.4265525215
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.2305219489
Short name T564
Test name
Test status
Simulation time 36588400 ps
CPU time 0.79 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201060 kb
Host smart-50a3e64f-c9d8-4b13-90f9-ac061b6fd7fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305219489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.2305219489
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2066490385
Short name T96
Test name
Test status
Simulation time 83146771 ps
CPU time 1.18 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201072 kb
Host smart-58158e97-f69c-4a66-83fe-9c0557e90ef1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066490385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.2066490385
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.1878090481
Short name T180
Test name
Test status
Simulation time 18374558 ps
CPU time 0.75 seconds
Started Aug 06 07:27:44 PM PDT 24
Finished Aug 06 07:27:45 PM PDT 24
Peak memory 200280 kb
Host smart-fb74cf65-fa50-4cb8-a03e-d78b33c09b41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878090481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.1878090481
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.99590516
Short name T634
Test name
Test status
Simulation time 24558317 ps
CPU time 0.9 seconds
Started Aug 06 07:27:44 PM PDT 24
Finished Aug 06 07:27:45 PM PDT 24
Peak memory 201068 kb
Host smart-7754b00f-323d-47c2-b687-cd8d64718e25
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99590516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
clkmgr_div_intersig_mubi.99590516
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.318109840
Short name T583
Test name
Test status
Simulation time 91887064 ps
CPU time 1.05 seconds
Started Aug 06 07:27:29 PM PDT 24
Finished Aug 06 07:27:30 PM PDT 24
Peak memory 201132 kb
Host smart-d837cb97-22f0-4802-907e-a0839962dc88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318109840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.318109840
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.984341434
Short name T19
Test name
Test status
Simulation time 690870255 ps
CPU time 4.35 seconds
Started Aug 06 07:27:28 PM PDT 24
Finished Aug 06 07:27:33 PM PDT 24
Peak memory 201408 kb
Host smart-5d3dbeb9-8629-475b-8365-a2dcd4c56ea6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984341434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.984341434
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.1335183543
Short name T738
Test name
Test status
Simulation time 1467803735 ps
CPU time 8.34 seconds
Started Aug 06 07:27:34 PM PDT 24
Finished Aug 06 07:27:43 PM PDT 24
Peak memory 201216 kb
Host smart-c7b73c8d-ec53-47ea-9061-89f3b30a82fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335183543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.1335183543
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.1253017355
Short name T295
Test name
Test status
Simulation time 58291795 ps
CPU time 1.01 seconds
Started Aug 06 07:27:47 PM PDT 24
Finished Aug 06 07:27:48 PM PDT 24
Peak memory 201112 kb
Host smart-021049fd-53a5-427c-8346-b5c5a6a687ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253017355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.1253017355
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1987327677
Short name T153
Test name
Test status
Simulation time 74706257 ps
CPU time 1.02 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 201108 kb
Host smart-392a8c56-1b02-42c8-bf5e-38f92c666f6b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987327677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.1987327677
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3044390562
Short name T483
Test name
Test status
Simulation time 53517322 ps
CPU time 0.91 seconds
Started Aug 06 07:27:44 PM PDT 24
Finished Aug 06 07:27:45 PM PDT 24
Peak memory 201156 kb
Host smart-72fbad8d-633d-46a3-a85e-c1f31c13d5bf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044390562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3044390562
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.3933540535
Short name T442
Test name
Test status
Simulation time 15666666 ps
CPU time 0.77 seconds
Started Aug 06 07:27:28 PM PDT 24
Finished Aug 06 07:27:29 PM PDT 24
Peak memory 201124 kb
Host smart-20762e7f-82d0-448d-b844-7b2949a14ece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933540535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3933540535
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.1236643044
Short name T693
Test name
Test status
Simulation time 69675704 ps
CPU time 1.05 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 201084 kb
Host smart-9903ef65-c963-4991-a98f-da9ecfd9b93b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236643044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1236643044
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.949058418
Short name T758
Test name
Test status
Simulation time 34129493 ps
CPU time 0.89 seconds
Started Aug 06 07:27:32 PM PDT 24
Finished Aug 06 07:27:33 PM PDT 24
Peak memory 201100 kb
Host smart-bf6b12e7-2d45-41a3-a979-c21184fc5fea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949058418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.949058418
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.4207251856
Short name T511
Test name
Test status
Simulation time 7044942993 ps
CPU time 49.82 seconds
Started Aug 06 07:27:44 PM PDT 24
Finished Aug 06 07:28:34 PM PDT 24
Peak memory 201492 kb
Host smart-86cbf380-763d-438e-a80c-7896fbd7d601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207251856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.4207251856
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.1160427209
Short name T807
Test name
Test status
Simulation time 34565595 ps
CPU time 1 seconds
Started Aug 06 07:27:31 PM PDT 24
Finished Aug 06 07:27:32 PM PDT 24
Peak memory 201080 kb
Host smart-d52d0500-cc3d-433d-aeaf-16a6240c1ed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160427209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1160427209
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.2138854077
Short name T706
Test name
Test status
Simulation time 15876570 ps
CPU time 0.77 seconds
Started Aug 06 07:27:44 PM PDT 24
Finished Aug 06 07:27:45 PM PDT 24
Peak memory 201068 kb
Host smart-7aaccc9b-cb23-4e45-b8b7-54d6c7325f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138854077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.2138854077
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.925369408
Short name T473
Test name
Test status
Simulation time 107813004 ps
CPU time 1.2 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201072 kb
Host smart-6807d004-90f3-4e68-9b21-455f7e3a32a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925369408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.925369408
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.2039962766
Short name T305
Test name
Test status
Simulation time 14203503 ps
CPU time 0.69 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201004 kb
Host smart-92674e81-8fb2-4a6d-bcba-6d1765591653
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039962766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2039962766
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.2917724555
Short name T591
Test name
Test status
Simulation time 58960563 ps
CPU time 0.93 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 201132 kb
Host smart-c0db33bb-4588-4806-9754-1b951549fd85
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917724555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.2917724555
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.1206235317
Short name T626
Test name
Test status
Simulation time 35741490 ps
CPU time 0.87 seconds
Started Aug 06 07:27:47 PM PDT 24
Finished Aug 06 07:27:48 PM PDT 24
Peak memory 201080 kb
Host smart-6a21852a-39e7-413f-b0f7-8682e542c6bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206235317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1206235317
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.207581026
Short name T668
Test name
Test status
Simulation time 2235205870 ps
CPU time 17.41 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:28:04 PM PDT 24
Peak memory 201444 kb
Host smart-82ea6e3f-c1f4-410c-9fd1-bf86b11d3209
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207581026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.207581026
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.4059231121
Short name T810
Test name
Test status
Simulation time 2212314349 ps
CPU time 9.33 seconds
Started Aug 06 07:27:43 PM PDT 24
Finished Aug 06 07:27:52 PM PDT 24
Peak memory 201456 kb
Host smart-42a0090d-7428-44d2-8ec4-da039f29dda6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059231121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.4059231121
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1402891904
Short name T512
Test name
Test status
Simulation time 108840252 ps
CPU time 1.42 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201024 kb
Host smart-7fb111db-ce1e-4429-9614-851aa87609b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402891904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.1402891904
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.2531647728
Short name T315
Test name
Test status
Simulation time 66571154 ps
CPU time 0.87 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201112 kb
Host smart-2013a08b-ec6e-45ca-b77a-5496defac60d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531647728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.2531647728
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.2813807113
Short name T418
Test name
Test status
Simulation time 30774480 ps
CPU time 0.99 seconds
Started Aug 06 07:27:47 PM PDT 24
Finished Aug 06 07:27:48 PM PDT 24
Peak memory 201092 kb
Host smart-6c45bed6-5330-4500-9e98-44a4b41ee443
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813807113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.2813807113
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.3512508706
Short name T169
Test name
Test status
Simulation time 38168031 ps
CPU time 0.79 seconds
Started Aug 06 07:27:44 PM PDT 24
Finished Aug 06 07:27:45 PM PDT 24
Peak memory 201324 kb
Host smart-ae46c2a7-0bae-413d-a2b7-675635ea82f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512508706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3512508706
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.264424911
Short name T277
Test name
Test status
Simulation time 270857635 ps
CPU time 1.57 seconds
Started Aug 06 07:27:47 PM PDT 24
Finished Aug 06 07:27:49 PM PDT 24
Peak memory 201144 kb
Host smart-d3e5e927-efe3-46b2-9d5f-65808c0ac19d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264424911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.264424911
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.1266328068
Short name T87
Test name
Test status
Simulation time 28875097 ps
CPU time 0.93 seconds
Started Aug 06 07:27:48 PM PDT 24
Finished Aug 06 07:27:49 PM PDT 24
Peak memory 201096 kb
Host smart-98d310bf-5bae-4e13-bbc8-a8fb9e655f11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266328068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.1266328068
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.361525804
Short name T735
Test name
Test status
Simulation time 2413127560 ps
CPU time 19.11 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:28:04 PM PDT 24
Peak memory 201416 kb
Host smart-67ff237b-367e-4cab-a7b2-02e9894cce25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361525804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.361525804
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.2469675651
Short name T675
Test name
Test status
Simulation time 31972825 ps
CPU time 1.01 seconds
Started Aug 06 07:27:47 PM PDT 24
Finished Aug 06 07:27:48 PM PDT 24
Peak memory 201032 kb
Host smart-af00374e-817b-4850-8f78-d9343925a225
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469675651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2469675651
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.2845843736
Short name T708
Test name
Test status
Simulation time 16735616 ps
CPU time 0.79 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 201108 kb
Host smart-c6aab0be-6b1d-45a2-ba79-2e9c9f6d36bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845843736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.2845843736
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3019160864
Short name T455
Test name
Test status
Simulation time 16988846 ps
CPU time 0.77 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 201060 kb
Host smart-cfc60b24-a39c-4fae-abb0-fa7fae661469
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019160864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.3019160864
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.3412464938
Short name T35
Test name
Test status
Simulation time 13396229 ps
CPU time 0.72 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 200268 kb
Host smart-a8803b32-447b-4f2b-a832-1afbdbe60f31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412464938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.3412464938
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.2881457102
Short name T335
Test name
Test status
Simulation time 46067143 ps
CPU time 0.85 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201140 kb
Host smart-f831e340-a744-464c-979c-be7b4ad43d31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881457102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.2881457102
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.2868382369
Short name T477
Test name
Test status
Simulation time 37360644 ps
CPU time 0.83 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:46 PM PDT 24
Peak memory 200976 kb
Host smart-337ac01f-db72-4157-adef-accb325f76d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868382369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.2868382369
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.151348014
Short name T355
Test name
Test status
Simulation time 817716598 ps
CPU time 4.03 seconds
Started Aug 06 07:27:43 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201092 kb
Host smart-d3a63af7-e3c2-4b49-8ed6-cc2dae08c3e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151348014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.151348014
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.483906912
Short name T773
Test name
Test status
Simulation time 1221553610 ps
CPU time 8.96 seconds
Started Aug 06 07:27:45 PM PDT 24
Finished Aug 06 07:27:54 PM PDT 24
Peak memory 201216 kb
Host smart-5a9764d9-ec8b-41cc-a023-0f3c1ca734a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483906912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_tim
eout.483906912
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.633805588
Short name T412
Test name
Test status
Simulation time 40902323 ps
CPU time 0.93 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201124 kb
Host smart-b4445dca-18aa-4d9f-9bdb-37be78fd7406
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633805588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.clkmgr_idle_intersig_mubi.633805588
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.4082537475
Short name T198
Test name
Test status
Simulation time 65677396 ps
CPU time 1.02 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:27:47 PM PDT 24
Peak memory 201064 kb
Host smart-18559c44-e6a2-407b-96c3-701179b0fd6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082537475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.4082537475
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3367943314
Short name T409
Test name
Test status
Simulation time 17810385 ps
CPU time 0.8 seconds
Started Aug 06 07:27:43 PM PDT 24
Finished Aug 06 07:27:44 PM PDT 24
Peak memory 201060 kb
Host smart-a7000b49-82d3-4169-a35c-c4d3f83cc0d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367943314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.3367943314
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.2910992816
Short name T334
Test name
Test status
Simulation time 19223492 ps
CPU time 0.79 seconds
Started Aug 06 07:27:48 PM PDT 24
Finished Aug 06 07:27:49 PM PDT 24
Peak memory 201136 kb
Host smart-a21dac95-3488-4460-8c5c-d87d7ecf3265
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910992816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2910992816
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.255962320
Short name T751
Test name
Test status
Simulation time 19555666 ps
CPU time 0.83 seconds
Started Aug 06 07:27:47 PM PDT 24
Finished Aug 06 07:27:48 PM PDT 24
Peak memory 201036 kb
Host smart-9517401c-3a13-48d5-85c9-a70fc2a42176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255962320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.255962320
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.2736600888
Short name T480
Test name
Test status
Simulation time 4671941437 ps
CPU time 25.68 seconds
Started Aug 06 07:27:46 PM PDT 24
Finished Aug 06 07:28:12 PM PDT 24
Peak memory 201508 kb
Host smart-f8db48e2-4c79-4758-a350-b03b0776033d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736600888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.2736600888
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_trans.3525149134
Short name T753
Test name
Test status
Simulation time 56351850 ps
CPU time 0.93 seconds
Started Aug 06 07:27:44 PM PDT 24
Finished Aug 06 07:27:45 PM PDT 24
Peak memory 201032 kb
Host smart-381ae1a2-fdd2-4e5c-a47d-863a8cfa14f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525149134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3525149134
Directory /workspace/9.clkmgr_trans/latest
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