Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	302799	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1260199

1

T5

47

T1

1134

T6

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	401898	1			T5	4		T1	425		T6	17
values[0x0]	537283	1			T5	36		T1	992		T6	17
values[0x1]	623817	1			T5	49		T1	985		T6	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	184947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1378051

1

T5

64

T1

1491

T6

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6144	1			T2	449		T20	1		T27	1
valid_sources[0x01]	6860	1			T16	1		T2	442		T27	5
valid_sources[0x02]	6074	1			T5	2		T2	500		T27	2
valid_sources[0x03]	5396	1			T5	3		T16	1		T2	425
valid_sources[0x04]	5921	1			T2	480		T27	1		T134	5
valid_sources[0x05]	5926	1			T5	1		T2	454		T3	266
valid_sources[0x06]	5828	1			T16	1		T2	448		T22	6
valid_sources[0x07]	5893	1			T2	459		T81	1		T3	310
valid_sources[0x08]	6030	1			T2	456		T27	4		T215	1
valid_sources[0x09]	6518	1			T16	2		T2	494		T17	2
valid_sources[0x0a]	6955	1			T16	2		T2	462		T17	1
valid_sources[0x0b]	6106	1			T16	1		T2	469		T80	3
valid_sources[0x0c]	6987	1			T2	370		T3	297		T29	1
valid_sources[0x0d]	5888	1			T16	2		T2	428		T27	4
valid_sources[0x0e]	6268	1			T16	1		T2	418		T3	301
valid_sources[0x0f]	5526	1			T16	1		T2	496		T19	1
valid_sources[0x10]	5572	1			T5	1		T16	1		T2	492
valid_sources[0x11]	6513	1			T16	1		T2	495		T22	5
valid_sources[0x12]	5519	1			T2	454		T22	3		T27	1
valid_sources[0x13]	6183	1			T5	2		T2	470		T27	1
valid_sources[0x14]	6613	1			T2	489		T27	3		T3	301
valid_sources[0x15]	7694	1			T16	2		T2	502		T22	1
valid_sources[0x16]	6302	1			T2	486		T19	1		T134	3
valid_sources[0x17]	5760	1			T5	1		T2	490		T21	1
valid_sources[0x18]	5672	1			T2	449		T21	2		T27	1
valid_sources[0x19]	5716	1			T5	1		T2	485		T27	1
valid_sources[0x1a]	6033	1			T6	52		T16	1		T2	453
valid_sources[0x1b]	6492	1			T16	1		T2	512		T27	1
valid_sources[0x1c]	6784	1			T16	1		T2	442		T27	4
valid_sources[0x1d]	6310	1			T5	2		T2	476		T27	2
valid_sources[0x1e]	5221	1			T2	433		T27	1		T81	1
valid_sources[0x1f]	7721	1			T5	1		T16	1		T2	444
valid_sources[0x20]	6351	1			T2	481		T19	2		T22	3
valid_sources[0x21]	6636	1			T2	478		T19	5		T20	1
valid_sources[0x22]	6495	1			T2	461		T27	1		T134	4
valid_sources[0x23]	5779	1			T2	480		T132	2		T133	1
valid_sources[0x24]	5657	1			T2	449		T3	299		T29	2
valid_sources[0x25]	6575	1			T2	435		T19	3		T22	2
valid_sources[0x26]	5707	1			T2	472		T27	1		T3	300
valid_sources[0x27]	5131	1			T2	520		T27	4		T3	271
valid_sources[0x28]	6106	1			T2	437		T22	2		T27	4
valid_sources[0x29]	5857	1			T16	2		T2	463		T27	5
valid_sources[0x2a]	6300	1			T16	1		T2	442		T22	3
valid_sources[0x2b]	5086	1			T16	1		T2	456		T22	4
valid_sources[0x2c]	6699	1			T5	1		T2	474		T22	2
valid_sources[0x2d]	5537	1			T2	470		T27	1		T80	3
valid_sources[0x2e]	6043	1			T16	1		T2	460		T21	1
valid_sources[0x2f]	6080	1			T5	2		T2	463		T21	1
valid_sources[0x30]	5688	1			T2	493		T27	2		T3	298
valid_sources[0x31]	5424	1			T16	2		T2	499		T3	300
valid_sources[0x32]	6496	1			T16	1		T2	415		T20	1
valid_sources[0x33]	6114	1			T2	449		T3	300		T29	1
valid_sources[0x34]	6721	1			T2	493		T19	4		T27	3
valid_sources[0x35]	6173	1			T16	1		T2	517		T17	10
valid_sources[0x36]	5985	1			T2	497		T27	2		T132	1
valid_sources[0x37]	5816	1			T16	2		T2	471		T133	1
valid_sources[0x38]	5633	1			T5	1		T16	1		T2	444
valid_sources[0x39]	5887	1			T16	2		T2	462		T22	3
valid_sources[0x3a]	5890	1			T5	2		T2	490		T3	305
valid_sources[0x3b]	5293	1			T2	443		T22	9		T133	1
valid_sources[0x3c]	5328	1			T5	2		T2	454		T27	1
valid_sources[0x3d]	6372	1			T2	420		T133	1		T3	324
valid_sources[0x3e]	7339	1			T5	1		T2	485		T19	17
valid_sources[0x3f]	7580	1			T2	497		T27	2		T81	1
valid_sources[0x40]	5832	1			T2	434		T3	304		T29	1
valid_sources[0x41]	5882	1			T16	1		T2	433		T78	1
valid_sources[0x42]	5710	1			T16	2		T2	484		T21	1
valid_sources[0x43]	5806	1			T16	1		T2	476		T27	3
valid_sources[0x44]	6439	1			T2	515		T21	1		T80	1
valid_sources[0x45]	5918	1			T2	459		T27	1		T81	1
valid_sources[0x46]	5598	1			T2	460		T19	4		T20	1
valid_sources[0x47]	5749	1			T16	1		T2	510		T21	1
valid_sources[0x48]	6104	1			T5	1		T2	480		T21	1
valid_sources[0x49]	6304	1			T5	1		T2	476		T27	2
valid_sources[0x4a]	6512	1			T5	3		T16	2		T2	436
valid_sources[0x4b]	5788	1			T5	2		T16	1		T2	470
valid_sources[0x4c]	7074	1			T16	1		T2	467		T27	1
valid_sources[0x4d]	6750	1			T16	1		T2	483		T78	2
valid_sources[0x4e]	6071	1			T16	3		T2	447		T21	1
valid_sources[0x4f]	5616	1			T2	473		T81	1		T3	310
valid_sources[0x50]	5860	1			T16	2		T2	416		T133	1
valid_sources[0x51]	5761	1			T2	471		T17	3		T27	2
valid_sources[0x52]	5759	1			T2	407		T22	2		T3	307
valid_sources[0x53]	5208	1			T2	472		T27	2		T133	1
valid_sources[0x54]	6247	1			T16	1		T2	440		T3	291
valid_sources[0x55]	6173	1			T2	512		T27	2		T3	317
valid_sources[0x56]	5829	1			T5	1		T2	449		T27	1
valid_sources[0x57]	5421	1			T2	443		T17	3		T27	1
valid_sources[0x58]	5645	1			T2	456		T20	1		T21	1
valid_sources[0x59]	5523	1			T16	1		T2	469		T21	2
valid_sources[0x5a]	5435	1			T2	465		T27	1		T3	265
valid_sources[0x5b]	6810	1			T5	1		T2	467		T19	3
valid_sources[0x5c]	5625	1			T16	1		T2	444		T20	1
valid_sources[0x5d]	5367	1			T16	1		T2	469		T3	297
valid_sources[0x5e]	6213	1			T16	3		T2	492		T133	1
valid_sources[0x5f]	6628	1			T5	1		T2	419		T3	314
valid_sources[0x60]	5892	1			T2	449		T27	4		T3	302
valid_sources[0x61]	8399	1			T1	2402		T2	459		T80	1
valid_sources[0x62]	6254	1			T2	496		T20	1		T133	2
valid_sources[0x63]	8597	1			T5	1		T2	424		T3	294
valid_sources[0x64]	5535	1			T5	1		T2	438		T22	4
valid_sources[0x65]	6337	1			T2	480		T27	2		T215	1
valid_sources[0x66]	6074	1			T2	483		T21	1		T27	1
valid_sources[0x67]	5846	1			T2	432		T17	4		T20	1
valid_sources[0x68]	9299	1			T2	495		T17	2		T22	3
valid_sources[0x69]	5734	1			T16	1		T2	478		T81	1
valid_sources[0x6a]	5586	1			T2	443		T80	2		T3	294
valid_sources[0x6b]	5598	1			T2	474		T19	13		T3	261
valid_sources[0x6c]	5830	1			T16	1		T2	455		T17	1
valid_sources[0x6d]	7092	1			T2	484		T21	1		T133	2
valid_sources[0x6e]	5555	1			T16	1		T2	482		T27	1
valid_sources[0x6f]	5563	1			T16	1		T2	447		T27	2
valid_sources[0x70]	6557	1			T16	1		T2	497		T20	1
valid_sources[0x71]	5409	1			T2	472		T27	3		T132	3
valid_sources[0x72]	5726	1			T5	1		T2	472		T132	1
valid_sources[0x73]	6547	1			T5	1		T16	1		T2	426
valid_sources[0x74]	6381	1			T2	454		T3	291		T29	2
valid_sources[0x75]	5620	1			T16	1		T2	463		T3	292
valid_sources[0x76]	6088	1			T2	455		T17	3		T27	5
valid_sources[0x77]	7547	1			T2	471		T21	1		T27	5
valid_sources[0x78]	5665	1			T2	465		T21	1		T78	2
valid_sources[0x79]	5915	1			T2	496		T27	4		T3	294
valid_sources[0x7a]	5402	1			T2	435		T3	306		T9	121
valid_sources[0x7b]	6078	1			T2	431		T28	397		T3	287
valid_sources[0x7c]	6097	1			T2	478		T78	1		T3	302
valid_sources[0x7d]	5552	1			T16	2		T2	461		T17	3
valid_sources[0x7e]	5930	1			T2	432		T27	1		T3	297
valid_sources[0x7f]	6447	1			T2	469		T22	1		T27	2
valid_sources[0x80]	5494	1			T2	490		T27	1		T133	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

325488

1

T5

1

T1

208

T6

7

values[0x0]

all_enables

biggest_size

482193

1

T5

25

T1

596

T6

6

values[0x1]

all_enables

biggest_size

452518

1

T5

21

T1

330

T6

3