Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T19
0	1	Covered	T1,T2,T78
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T1,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	476565273	7382	0	0
GateOpen_A	476565273	13085	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476565273	7382	0	0
T1	1871047	6	0	0
T2	2014433	337	0	0
T3	0	242	0	0
T6	25661	0	0	0
T16	47794	0	0	0
T17	87991	0	0	0
T18	15579	0	0	0
T19	8981	4	0	0
T20	4338	0	0	0
T21	46208	0	0	0
T22	7061	0	0	0
T78	0	26	0	0
T79	0	22	0	0
T80	0	32	0	0
T83	0	10	0	0
T133	0	4	0	0
T215	0	38	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476565273	13085	0	0
T1	1871047	22	0	0
T2	2014433	365	0	0
T6	25661	0	0	0
T16	47794	0	0	0
T17	87991	4	0	0
T18	15579	0	0	0
T19	8981	8	0	0
T20	4338	0	0	0
T21	46208	0	0	0
T22	7061	4	0	0
T27	0	4	0	0
T78	0	30	0	0
T79	0	22	0	0
T80	0	36	0	0
T83	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T19
0	1	Covered	T1,T2,T78
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	52389901	1767	0	0
GateOpen_A	52389901	3193	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389901	1767	0	0
T1	204675	1	0	0
T2	223224	76	0	0
T3	0	59	0	0
T6	3222	0	0	0
T16	5307	0	0	0
T17	9133	0	0	0
T18	2228	0	0	0
T19	976	1	0	0
T20	491	0	0	0
T21	5121	0	0	0
T22	778	0	0	0
T78	0	6	0	0
T79	0	5	0	0
T80	0	9	0	0
T83	0	2	0	0
T133	0	1	0	0
T215	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52389901	3193	0	0
T1	204675	5	0	0
T2	223224	83	0	0
T6	3222	0	0	0
T16	5307	0	0	0
T17	9133	1	0	0
T18	2228	0	0	0
T19	976	2	0	0
T20	491	0	0	0
T21	5121	0	0	0
T22	778	1	0	0
T27	0	1	0	0
T78	0	7	0	0
T79	0	5	0	0
T80	0	10	0	0
T83	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T19
0	1	Covered	T1,T2,T78
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	104780243	1858	0	0
GateOpen_A	104780243	3284	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104780243	1858	0	0
T1	409356	1	0	0
T2	446453	88	0	0
T3	0	62	0	0
T6	6445	0	0	0
T16	10613	0	0	0
T17	18265	0	0	0
T18	4454	0	0	0
T19	1951	1	0	0
T20	982	0	0	0
T21	10242	0	0	0
T22	1556	0	0	0
T78	0	6	0	0
T79	0	7	0	0
T80	0	8	0	0
T83	0	2	0	0
T133	0	1	0	0
T215	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104780243	3284	0	0
T1	409356	5	0	0
T2	446453	95	0	0
T6	6445	0	0	0
T16	10613	0	0	0
T17	18265	1	0	0
T18	4454	0	0	0
T19	1951	2	0	0
T20	982	0	0	0
T21	10242	0	0	0
T22	1556	1	0	0
T27	0	1	0	0
T78	0	7	0	0
T79	0	7	0	0
T80	0	9	0	0
T83	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T19
0	1	Covered	T1,T2,T78
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	210814531	1868	0	0
GateOpen_A	210814531	3294	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814531	1868	0	0
T1	818798	2	0	0
T2	893226	85	0	0
T3	0	62	0	0
T6	10663	0	0	0
T16	21249	0	0	0
T17	36555	0	0	0
T18	5931	0	0	0
T19	4036	1	0	0
T20	1910	0	0	0
T21	20563	0	0	0
T22	3151	0	0	0
T78	0	6	0	0
T79	0	5	0	0
T80	0	8	0	0
T83	0	3	0	0
T133	0	1	0	0
T215	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210814531	3294	0	0
T1	818798	6	0	0
T2	893226	92	0	0
T6	10663	0	0	0
T16	21249	0	0	0
T17	36555	1	0	0
T18	5931	0	0	0
T19	4036	2	0	0
T20	1910	0	0	0
T21	20563	0	0	0
T22	3151	1	0	0
T27	0	1	0	0
T78	0	7	0	0
T79	0	5	0	0
T80	0	9	0	0
T83	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T19
0	1	Covered	T1,T2,T78
1	0	Covered	T5,T1,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T34,T35,T36
1	1	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	108580598	1889	0	0
GateOpen_A	108580598	3314	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108580598	1889	0	0
T1	438218	2	0	0
T2	451530	88	0	0
T3	0	59	0	0
T6	5331	0	0	0
T16	10625	0	0	0
T17	24038	0	0	0
T18	2966	0	0	0
T19	2018	1	0	0
T20	955	0	0	0
T21	10282	0	0	0
T22	1576	0	0	0
T78	0	8	0	0
T79	0	5	0	0
T80	0	7	0	0
T83	0	3	0	0
T133	0	1	0	0
T215	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108580598	3314	0	0
T1	438218	6	0	0
T2	451530	95	0	0
T6	5331	0	0	0
T16	10625	0	0	0
T17	24038	1	0	0
T18	2966	0	0	0
T19	2018	2	0	0
T20	955	0	0	0
T21	10282	0	0	0
T22	1576	1	0	0
T27	0	1	0	0
T78	0	9	0	0
T79	0	5	0	0
T80	0	8	0	0
T83	0	4	0	0