Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	364896445	41836	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364896445	41836	0	0
T1	4718895	1111	0	0
T2	2272050	3047	0	0
T3	0	1389	0	0
T6	8880	0	0	0
T9	0	809	0	0
T10	0	324	0	0
T11	0	79	0	0
T12	0	44	0	0
T13	0	404	0	0
T14	0	99	0	0
T15	0	187	0	0
T16	8850	0	0	0
T17	122695	0	0	0
T18	7105	0	0	0
T19	10090	0	0	0
T20	9450	0	0	0
T21	25700	0	0	0
T22	16405	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72979289	6256	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	6256	0	0
T1	943779	146	0	0
T2	454410	435	0	0
T3	0	202	0	0
T6	1776	0	0	0
T9	0	129	0	0
T10	0	41	0	0
T11	0	11	0	0
T12	0	7	0	0
T13	0	59	0	0
T14	0	16	0	0
T15	0	31	0	0
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	0	0	0
T21	5140	0	0	0
T22	3281	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72979289	6146	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	6146	0	0
T1	943779	144	0	0
T2	454410	426	0	0
T3	0	199	0	0
T6	1776	0	0	0
T9	0	127	0	0
T10	0	47	0	0
T11	0	11	0	0
T12	0	7	0	0
T13	0	58	0	0
T14	0	16	0	0
T15	0	31	0	0
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	0	0	0
T21	5140	0	0	0
T22	3281	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72979289	8497	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	8497	0	0
T1	943779	224	0	0
T2	454410	684	0	0
T3	0	279	0	0
T6	1776	0	0	0
T9	0	163	0	0
T10	0	66	0	0
T11	0	17	0	0
T12	0	9	0	0
T13	0	80	0	0
T14	0	20	0	0
T15	0	39	0	0
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	0	0	0
T21	5140	0	0	0
T22	3281	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72979289	8392	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	8392	0	0
T1	943779	224	0	0
T2	454410	592	0	0
T3	0	281	0	0
T6	1776	0	0	0
T9	0	164	0	0
T10	0	63	0	0
T11	0	15	0	0
T12	0	9	0	0
T13	0	81	0	0
T14	0	20	0	0
T15	0	38	0	0
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	0	0	0
T21	5140	0	0	0
T22	3281	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72979289	12545	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	12545	0	0
T1	943779	373	0	0
T2	454410	910	0	0
T3	0	428	0	0
T6	1776	0	0	0
T9	0	226	0	0
T10	0	107	0	0
T11	0	25	0	0
T12	0	12	0	0
T13	0	126	0	0
T14	0	27	0	0
T15	0	48	0	0
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	0	0	0
T21	5140	0	0	0
T22	3281	0	0	0