Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	72979289	71027558	0	0
AllClkBypReqTrue_A	72979289	82071	0	0
IoClkBypReqFalse_A	72979289	70975329	0	2322
IoClkBypReqTrue_A	72979289	130364	0	0
LcClkBypAckFalse_A	72979289	71033731	0	0
LcClkBypAckTrue_A	72979289	75898	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	71027558	0	0
T1	943779	942444	0	0
T2	454410	452282	0	0
T5	50164	50037	0	0
T6	1776	1559	0	0
T16	1770	1764	0	0
T17	24539	24490	0	0
T18	1421	1339	0	0
T19	2018	1916	0	0
T20	1890	1611	0	0
T21	5140	5085	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	82071	0	0
T1	943779	433	0	0
T2	454410	5902	0	0
T3	0	2056	0	0
T6	1776	194	0	0
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	49	0	0
T19	2018	0	0	0
T20	1890	104	0	0
T21	5140	0	0	0
T22	3281	0	0	0
T81	0	39	0	0
T82	0	43	0	0
T117	0	139	0	0
T128	0	58	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	70975329	0	2322
T1	943779	942231	0	3
T2	454410	452015	0	3
T5	50164	50035	0	3
T6	1776	1417	0	3
T16	1770	1762	0	3
T17	24539	24488	0	3
T18	1421	1386	0	3
T19	2018	1914	0	3
T20	1890	1585	0	3
T21	5140	5083	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	130364	0	0
T1	943779	634	0	0
T2	454410	8552	0	0
T3	0	2919	0	0
T6	1776	334	0	0
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	128	0	0
T21	5140	0	0	0
T22	3281	0	0	0
T81	0	23	0	0
T117	0	116	0	0
T128	0	52	0	0
T129	0	636	0	0
T130	0	319	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	71033731	0	0
T1	943779	942541	0	0
T2	454410	452332	0	0
T5	50164	50037	0	0
T6	1776	1486	0	0
T16	1770	1764	0	0
T17	24539	24490	0	0
T18	1421	1388	0	0
T19	2018	1916	0	0
T20	1890	1642	0	0
T21	5140	5085	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72979289	75898	0	0
T1	943779	336	0	0
T2	454410	5407	0	0
T3	0	1684	0	0
T6	1776	267	0	0
T16	1770	0	0	0
T17	24539	0	0	0
T18	1421	0	0	0
T19	2018	0	0	0
T20	1890	73	0	0
T21	5140	0	0	0
T22	3281	0	0	0
T81	0	18	0	0
T117	0	53	0	0
T129	0	395	0	0
T130	0	180	0	0
T131	0	109	0	0