Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	905332100	9643	0	0
TransStop_A	905332100	5007	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905332100	9643	0	0
T1	3843768	38	0	0
T2	3760292	489	0	0
T3	0	289	0	0
T6	44428	0	0	0
T9	0	266	0	0
T16	88540	28	0	0
T17	176316	0	0	0
T18	24712	0	0	0
T19	16816	4	0	0
T20	7960	0	0	0
T21	85684	0	0	0
T22	13128	37	0	0
T132	0	16	0	0
T133	0	4	0	0
T134	0	17	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905332100	5007	0	0
T1	3843768	21	0	0
T2	3760292	230	0	0
T3	0	151	0	0
T6	44428	0	0	0
T9	0	118	0	0
T16	88540	9	0	0
T17	176316	0	0	0
T18	24712	0	0	0
T19	16816	4	0	0
T20	7960	0	0	0
T21	85684	0	0	0
T22	13128	16	0	0
T132	0	16	0	0
T133	0	4	0	0
T134	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	226333025	2409	0	0
TransStop_A	226333025	1248	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226333025	2409	0	0
T1	960942	9	0	0
T2	940073	122	0	0
T3	0	78	0	0
T6	11107	0	0	0
T9	0	65	0	0
T16	22135	7	0	0
T17	44079	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21421	0	0	0
T22	3282	9	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226333025	1248	0	0
T1	960942	6	0	0
T2	940073	58	0	0
T3	0	40	0	0
T6	11107	0	0	0
T9	0	30	0	0
T16	22135	3	0	0
T17	44079	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21421	0	0	0
T22	3282	3	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	226333025	2381	0	0
TransStop_A	226333025	1239	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226333025	2381	0	0
T1	960942	11	0	0
T2	940073	112	0	0
T3	0	63	0	0
T6	11107	0	0	0
T9	0	71	0	0
T16	22135	6	0	0
T17	44079	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21421	0	0	0
T22	3282	8	0	0
T132	0	3	0	0
T133	0	1	0	0
T134	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226333025	1239	0	0
T1	960942	5	0	0
T2	940073	50	0	0
T3	0	36	0	0
T6	11107	0	0	0
T9	0	31	0	0
T16	22135	1	0	0
T17	44079	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21421	0	0	0
T22	3282	3	0	0
T132	0	3	0	0
T133	0	1	0	0
T134	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	226333025	2435	0	0
TransStop_A	226333025	1260	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226333025	2435	0	0
T1	960942	5	0	0
T2	940073	127	0	0
T3	0	79	0	0
T6	11107	0	0	0
T9	0	64	0	0
T16	22135	8	0	0
T17	44079	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21421	0	0	0
T22	3282	11	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226333025	1260	0	0
T1	960942	2	0	0
T2	940073	61	0	0
T3	0	38	0	0
T6	11107	0	0	0
T9	0	27	0	0
T16	22135	2	0	0
T17	44079	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21421	0	0	0
T22	3282	5	0	0
T132	0	4	0	0
T133	0	1	0	0
T134	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	226333025	2418	0	0
TransStop_A	226333025	1260	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226333025	2418	0	0
T1	960942	13	0	0
T2	940073	128	0	0
T3	0	69	0	0
T6	11107	0	0	0
T9	0	66	0	0
T16	22135	7	0	0
T17	44079	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21421	0	0	0
T22	3282	9	0	0
T132	0	5	0	0
T133	0	1	0	0
T134	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226333025	1260	0	0
T1	960942	8	0	0
T2	940073	61	0	0
T3	0	37	0	0
T6	11107	0	0	0
T9	0	30	0	0
T16	22135	3	0	0
T17	44079	0	0	0
T18	6178	0	0	0
T19	4204	1	0	0
T20	1990	0	0	0
T21	21421	0	0	0
T22	3282	5	0	0
T132	0	5	0	0
T133	0	1	0	0
T134	0	1	0	0